DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_9p_properties;
+ device_class_set_props(dc, virtio_9p_properties);
dc->vmsd = &vmstate_virtio_9p;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = virtio_9p_device_realize;
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(class);
dc->desc = "ACPI Generic Event Device";
- dc->props = acpi_ged_properties;
+ device_class_set_props(dc, acpi_ged_properties);
dc->vmsd = &vmstate_acpi_ged;
hc->plug = acpi_ged_device_plug_cb;
dc->reset = piix4_pm_reset;
dc->desc = "PM";
dc->vmsd = &vmstate_acpi;
- dc->props = piix4_pm_properties;
+ device_class_set_props(dc, piix4_pm_properties);
/*
* Reason: part of PIIX4 southbridge, needs to be wired up,
* e.g. by mips_malta_init()
dc->vmsd = &vmstate_vmgenid;
dc->realize = vmgenid_realize;
- dc->props = vmgenid_device_properties;
+ device_class_set_props(dc, vmgenid_device_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
dc->realize = armsse_realize;
dc->vmsd = &armsse_vmstate;
- dc->props = info->props;
+ device_class_set_props(dc, info->props);
dc->reset = armsse_reset;
iic->check = armsse_idau_check;
asc->info = info;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = armv7m_realize;
- dc->props = armv7m_properties;
+ device_class_set_props(dc, armv7m_properties);
}
static const TypeInfo armv7m_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = bitband_realize;
- dc->props = bitband_properties;
+ device_class_set_props(dc, bitband_properties);
}
static const TypeInfo bitband_info = {
dc->realize = aspeed_soc_realize;
/* Reason: Uses serial_hds and nd_table in realize() directly */
dc->user_creatable = false;
- dc->props = aspeed_soc_properties;
+ device_class_set_props(dc, aspeed_soc_properties);
}
static const TypeInfo aspeed_soc_type_info = {
bc->info = data;
dc->realize = bcm2836_realize;
- dc->props = bcm2836_props;
+ device_class_set_props(dc, bcm2836_props);
/* Reason: Must be wired up in code (see raspi_init() function) */
dc->user_creatable = false;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = core_properties;
+ device_class_set_props(dc, core_properties);
dc->realize = integratorcm_realize;
dc->vmsd = &vmstate_integratorcm;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = m2sxxx_soc_realize;
- dc->props = m2sxxx_soc_properties;
+ device_class_set_props(dc, m2sxxx_soc_properties);
}
static const TypeInfo m2sxxx_soc_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &mv88w8618_eth_vmsd;
- dc->props = mv88w8618_eth_properties;
+ device_class_set_props(dc, mv88w8618_eth_properties);
dc->realize = mv88w8618_eth_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = nrf51_soc_realize;
- dc->props = nrf51_soc_properties;
+ device_class_set_props(dc, nrf51_soc_properties);
}
static const TypeInfo nrf51_soc_info = {
dc->desc = "PXA2xx I2C Bus Controller";
dc->vmsd = &vmstate_pxa2xx_i2c;
- dc->props = pxa2xx_i2c_properties;
+ device_class_set_props(dc, pxa2xx_i2c_properties);
}
static const TypeInfo pxa2xx_i2c_info = {
dc->realize = pxa2xx_fir_realize;
dc->vmsd = &pxa2xx_fir_vmsd;
- dc->props = pxa2xx_fir_properties;
+ device_class_set_props(dc, pxa2xx_fir_properties);
dc->reset = pxa2xx_fir_reset;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "PXA2xx GPIO controller";
- dc->props = pxa2xx_gpio_properties;
+ device_class_set_props(dc, pxa2xx_gpio_properties);
dc->vmsd = &vmstate_pxa2xx_gpio_regs;
dc->realize = pxa2xx_gpio_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
- dc->props = smmu_dev_properties;
+ device_class_set_props(dc, smmu_dev_properties);
device_class_set_parent_realize(dc, smmu_base_realize,
&sbc->parent_realize);
dc->reset = smmu_base_reset;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_sl_nand_info;
- dc->props = sl_nand_properties;
+ device_class_set_props(dc, sl_nand_properties);
dc->realize = sl_nand_realize;
/* Reason: init() method uses drive_get() */
dc->user_creatable = false;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f205_soc_realize;
- dc->props = stm32f205_soc_properties;
+ device_class_set_props(dc, stm32f205_soc_properties);
}
static const TypeInfo stm32f205_soc_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = stm32f405_soc_realize;
- dc->props = stm32f405_soc_properties;
+ device_class_set_props(dc, stm32f405_soc_properties);
/* No vmstate or reset required: device has no internal state */
}
dc->desc = "StrongARM UART controller";
dc->reset = strongarm_uart_reset;
dc->vmsd = &vmstate_strongarm_uart_regs;
- dc->props = strongarm_uart_properties;
+ device_class_set_props(dc, strongarm_uart_properties);
dc->realize = strongarm_uart_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = versal_realize;
- dc->props = versal_properties;
+ device_class_set_props(dc, versal_properties);
/* No VMSD since we haven't got any top-level SoC state to save. */
}
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->props = xlnx_zynqmp_props;
+ device_class_set_props(dc, xlnx_zynqmp_props);
dc->realize = xlnx_zynqmp_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "Intel 82801AA AC97 Audio";
dc->vmsd = &vmstate_ac97;
- dc->props = ac97_properties;
+ device_class_set_props(dc, ac97_properties);
dc->reset = ac97_on_reset;
}
dc->realize = adlib_realizefn;
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = ADLIB_DESC;
- dc->props = adlib_properties;
+ device_class_set_props(dc, adlib_properties);
}
static const TypeInfo adlib_info = {
dc->reset = cs_reset;
dc->vmsd = &vmstate_cs4231;
- dc->props = cs4231_properties;
+ device_class_set_props(dc, cs4231_properties);
}
static const TypeInfo cs4231_info = {
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "Crystal Semiconductor CS4231A";
dc->vmsd = &vmstate_cs4231a;
- dc->props = cs4231a_properties;
+ device_class_set_props(dc, cs4231a_properties);
}
static const TypeInfo cs4231a_info = {
dc->desc = "ENSONIQ AudioPCI ES1370";
dc->vmsd = &vmstate_es1370;
dc->reset = es1370_on_reset;
- dc->props = es1370_properties;
+ device_class_set_props(dc, es1370_properties);
}
static const TypeInfo es1370_info = {
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "Gravis Ultrasound GF1";
dc->vmsd = &vmstate_gus;
- dc->props = gus_properties;
+ device_class_set_props(dc, gus_properties);
}
static const TypeInfo gus_info = {
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->reset = hda_audio_reset;
dc->vmsd = &vmstate_hda_audio;
- dc->props = hda_audio_properties;
+ device_class_set_props(dc, hda_audio_properties);
}
static const TypeInfo hda_audio_info = {
k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
dc->reset = intel_hda_reset;
dc->vmsd = &vmstate_intel_hda;
- dc->props = intel_hda_properties;
+ device_class_set_props(dc, intel_hda_properties);
}
static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
k->unrealize = hda_codec_dev_unrealize;
set_bit(DEVICE_CATEGORY_SOUND, k->categories);
k->bus_type = TYPE_HDA_BUS;
- k->props = hda_props;
+ device_class_set_props(k, hda_props);
}
static const TypeInfo hda_codec_device_type_info = {
dc->realize = milkymist_ac97_realize;
dc->reset = milkymist_ac97_reset;
dc->vmsd = &vmstate_milkymist_ac97;
- dc->props = milkymist_ac97_properties;
+ device_class_set_props(dc, milkymist_ac97_properties);
}
static const TypeInfo milkymist_ac97_info = {
dc->realize = pcspk_realizefn;
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->vmsd = &vmstate_spk;
- dc->props = pcspk_properties;
+ device_class_set_props(dc, pcspk_properties);
/* Reason: realize sets global pcspk_state */
/* Reason: pit object link */
dc->user_creatable = false;
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->reset = pl041_device_reset;
dc->vmsd = &vmstate_pl041;
- dc->props = pl041_device_properties;
+ device_class_set_props(dc, pl041_device_properties);
}
static const TypeInfo pl041_device_info = {
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
dc->desc = "Creative Sound Blaster 16";
dc->vmsd = &vmstate_sb16;
- dc->props = sb16_properties;
+ device_class_set_props(dc, sb16_properties);
}
static const TypeInfo sb16_info = {
sc->recv = wm8750_rx;
sc->send = wm8750_tx;
dc->vmsd = &vmstate_wm8750;
- dc->props = wm8750_properties;
+ device_class_set_props(dc, wm8750_properties);
}
static const TypeInfo wm8750_info = {
k->realize = floppy_drive_realize;
set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
k->bus_type = TYPE_FLOPPY_BUS;
- k->props = floppy_drive_properties;
+ device_class_set_props(k, floppy_drive_properties);
k->desc = "virtual floppy drive";
}
dc->fw_name = "fdc";
dc->reset = fdctrl_external_reset_isa;
dc->vmsd = &vmstate_isa_fdc;
- dc->props = isa_fdc_properties;
+ device_class_set_props(dc, isa_fdc_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = sysbus_fdc_properties;
+ device_class_set_props(dc, sysbus_fdc_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = sun4m_fdc_properties;
+ device_class_set_props(dc, sun4m_fdc_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
k->set_cs = m25p80_cs;
k->cs_polarity = SSI_CS_LOW;
dc->vmsd = &vmstate_m25p80;
- dc->props = m25p80_properties;
+ device_class_set_props(dc, m25p80_properties);
dc->reset = m25p80_reset;
mc->pi = data;
}
dc->realize = nand_realize;
dc->reset = nand_reset;
dc->vmsd = &vmstate_nand;
- dc->props = nand_properties;
+ device_class_set_props(dc, nand_properties);
}
static const TypeInfo nand_info = {
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
dc->desc = "Non-Volatile Memory Express";
- dc->props = nvme_props;
+ device_class_set_props(dc, nvme_props);
dc->vmsd = &nvme_vmstate;
}
dc->realize = onenand_realize;
dc->reset = onenand_system_reset;
- dc->props = onenand_properties;
+ device_class_set_props(dc, onenand_properties);
}
static const TypeInfo onenand_info = {
dc->reset = pflash_cfi01_system_reset;
dc->realize = pflash_cfi01_realize;
- dc->props = pflash_cfi01_properties;
+ device_class_set_props(dc, pflash_cfi01_properties);
dc->vmsd = &vmstate_pflash;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
dc->realize = pflash_cfi02_realize;
dc->unrealize = pflash_cfi02_unrealize;
- dc->props = pflash_cfi02_properties;
+ device_class_set_props(dc, pflash_cfi02_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
k->realize = swim_drive_realize;
set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
k->bus_type = TYPE_SWIM_BUS;
- k->props = swim_drive_properties;
+ device_class_set_props(k, swim_drive_properties);
k->desc = "virtual SWIM drive";
}
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = vhost_user_blk_properties;
+ device_class_set_props(dc, vhost_user_blk_properties);
dc->vmsd = &vmstate_vhost_user_blk;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = vhost_user_blk_device_realize;
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_blk_properties;
+ device_class_set_props(dc, virtio_blk_properties);
dc->vmsd = &vmstate_virtio_blk;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = virtio_blk_device_realize;
xendev_class->frontend_changed = xen_block_frontend_changed;
xendev_class->unrealize = xen_block_unrealize;
- dev_class->props = xen_block_props;
+ device_class_set_props(dev_class, xen_block_props);
}
static const TypeInfo xen_block_type_info = {
dc->realize = bcm2835_aux_realize;
dc->vmsd = &vmstate_bcm2835_aux;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
- dc->props = bcm2835_aux_props;
+ device_class_set_props(dc, bcm2835_aux_props);
}
static const TypeInfo bcm2835_aux_info = {
dc->realize = cadence_uart_realize;
dc->vmsd = &vmstate_cadence_uart;
dc->reset = cadence_uart_reset;
- dc->props = cadence_uart_properties;
+ device_class_set_props(dc, cadence_uart_properties);
}
static const TypeInfo cadence_uart_info = {
dc->realize = cmsdk_apb_uart_realize;
dc->vmsd = &cmsdk_apb_uart_vmstate;
dc->reset = cmsdk_apb_uart_reset;
- dc->props = cmsdk_apb_uart_properties;
+ device_class_set_props(dc, cmsdk_apb_uart_properties);
}
static const TypeInfo cmsdk_apb_uart_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = debugcon_isa_realizefn;
- dc->props = debugcon_isa_properties;
+ device_class_set_props(dc, debugcon_isa_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
dc->realize = digic_uart_realize;
dc->reset = digic_uart_reset;
dc->vmsd = &vmstate_digic_uart;
- dc->props = digic_uart_properties;
+ device_class_set_props(dc, digic_uart_properties);
}
static const TypeInfo digic_uart_info = {
dc->reset = escc_reset;
dc->realize = escc_realize;
dc->vmsd = &vmstate_escc;
- dc->props = escc_properties;
+ device_class_set_props(dc, escc_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = etraxfs_ser_reset;
- dc->props = etraxfs_ser_properties;
+ device_class_set_props(dc, etraxfs_ser_properties);
dc->realize = etraxfs_ser_realize;
}
dc->realize = exynos4210_uart_realize;
dc->reset = exynos4210_uart_reset;
- dc->props = exynos4210_uart_properties;
+ device_class_set_props(dc, exynos4210_uart_properties);
dc->vmsd = &vmstate_exynos4210_uart;
}
dc->realize = grlib_apbuart_realize;
dc->reset = grlib_apbuart_reset;
- dc->props = grlib_apbuart_properties;
+ device_class_set_props(dc, grlib_apbuart_properties);
}
static const TypeInfo grlib_apbuart_info = {
dc->reset = imx_serial_reset_at_boot;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->desc = "i.MX series UART";
- dc->props = imx_serial_properties;
+ device_class_set_props(dc, imx_serial_properties);
}
static const TypeInfo imx_serial_info = {
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
- dc->props = ipoctal_properties;
+ device_class_set_props(dc, ipoctal_properties);
dc->vmsd = &vmstate_ipoctal;
}
dc->reset = juart_reset;
dc->vmsd = &vmstate_lm32_juart;
- dc->props = lm32_juart_properties;
+ device_class_set_props(dc, lm32_juart_properties);
dc->realize = lm32_juart_realize;
}
dc->reset = uart_reset;
dc->vmsd = &vmstate_lm32_uart;
- dc->props = lm32_uart_properties;
+ device_class_set_props(dc, lm32_uart_properties);
dc->realize = lm32_uart_realize;
}
dc->realize = mcf_uart_realize;
dc->reset = mcf_uart_reset;
- dc->props = mcf_uart_properties;
+ device_class_set_props(dc, mcf_uart_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
dc->realize = milkymist_uart_realize;
dc->reset = milkymist_uart_reset;
dc->vmsd = &vmstate_milkymist_uart;
- dc->props = milkymist_uart_properties;
+ device_class_set_props(dc, milkymist_uart_properties);
}
static const TypeInfo milkymist_uart_info = {
dc->reset = nrf51_uart_reset;
dc->realize = nrf51_uart_realize;
- dc->props = nrf51_uart_properties;
+ device_class_set_props(dc, nrf51_uart_properties);
dc->vmsd = &nrf51_uart_vmstate;
}
dc->realize = parallel_isa_realizefn;
dc->vmsd = &vmstate_parallel_isa;
- dc->props = parallel_isa_properties;
+ device_class_set_props(dc, parallel_isa_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
dc->realize = pl011_realize;
dc->vmsd = &vmstate_pl011;
- dc->props = pl011_properties;
+ device_class_set_props(dc, pl011_properties);
}
static const TypeInfo pl011_arm_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
SCLPEventClass *ec = SCLP_EVENT_CLASS(klass);
- dc->props = console_properties;
+ device_class_set_props(dc, console_properties);
dc->reset = console_reset;
dc->vmsd = &vmstate_sclplmconsole;
ec->init = console_init;
DeviceClass *dc = DEVICE_CLASS(klass);
SCLPEventClass *ec = SCLP_EVENT_CLASS(klass);
- dc->props = console_properties;
+ device_class_set_props(dc, console_properties);
dc->reset = console_reset;
dc->vmsd = &vmstate_sclpconsole;
ec->init = console_init;
dc->realize = serial_isa_realizefn;
dc->vmsd = &vmstate_isa_serial;
- dc->props = serial_isa_properties;
+ device_class_set_props(dc, serial_isa_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
pc->revision = 1;
pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
dc->vmsd = &vmstate_pci_multi_serial;
- dc->props = multi_2x_serial_pci_properties;
+ device_class_set_props(dc, multi_2x_serial_pci_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
pc->revision = 1;
pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
dc->vmsd = &vmstate_pci_multi_serial;
- dc->props = multi_4x_serial_pci_properties;
+ device_class_set_props(dc, multi_4x_serial_pci_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
pc->revision = 1;
pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
dc->vmsd = &vmstate_pci_serial;
- dc->props = serial_pci_properties;
+ device_class_set_props(dc, serial_pci_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
dc->realize = serial_realize;
dc->unrealize = serial_unrealize;
dc->vmsd = &vmstate_serial;
- dc->props = serial_properties;
+ device_class_set_props(dc, serial_properties);
}
static const TypeInfo serial_info = {
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->props = serial_mm_properties;
+ device_class_set_props(dc, serial_mm_properties);
dc->realize = serial_mm_realize;
}
k->dt_type = "serial";
k->dt_compatible = "hvterm1";
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
- dc->props = spapr_vty_properties;
+ device_class_set_props(dc, spapr_vty_properties);
dc->vmsd = &vmstate_spapr_vty;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = stm32f2xx_usart_reset;
- dc->props = stm32f2xx_usart_properties;
+ device_class_set_props(dc, stm32f2xx_usart_properties);
dc->realize = stm32f2xx_usart_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
EmulatedCcw3270Class *ck = EMULATED_CCW_3270_CLASS(klass);
- dc->props = terminal_properties;
+ device_class_set_props(dc, terminal_properties);
dc->vmsd = &terminal3270_vmstate;
ck->init = terminal_init;
ck->read_payload_3270 = read_payload_3270;
k->set_guest_connected = set_guest_connected;
k->enable_backend = virtconsole_enable_backend;
k->guest_writable = guest_writable;
- dc->props = virtserialport_properties;
+ device_class_set_props(dc, virtserialport_properties);
}
static const TypeInfo virtserialport_info = {
k->bus_type = TYPE_VIRTIO_SERIAL_BUS;
k->realize = virtser_port_device_realize;
k->unrealize = virtser_port_device_unrealize;
- k->props = virtser_props;
+ device_class_set_props(k, virtser_props);
}
static const TypeInfo virtio_serial_port_type_info = {
QLIST_INIT(&vserdevices.devices);
- dc->props = virtio_serial_properties;
+ device_class_set_props(dc, virtio_serial_properties);
dc->vmsd = &vmstate_virtio_console;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
vdc->realize = virtio_serial_device_realize;
dc->reset = xilinx_uartlite_reset;
dc->realize = xilinx_uartlite_realize;
- dc->props = xilinx_uartlite_properties;
+ device_class_set_props(dc, xilinx_uartlite_properties);
}
static const TypeInfo xilinx_uartlite_info = {
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
- dc->props = cpu_common_props;
+ device_class_set_props(dc, cpu_common_props);
/*
* Reason: CPUs still need special care by board code: wiring up
* IRQs, adding reset handlers, halting non-first CPUs, ...
*/
dc->realize = generic_loader_realize;
dc->unrealize = generic_loader_unrealize;
- dc->props = generic_loader_props;
+ device_class_set_props(dc, generic_loader_props);
dc->desc = "Generic Loader";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = or_irq_reset;
- dc->props = or_irq_properties;
+ device_class_set_props(dc, or_irq_properties);
dc->realize = or_irq_realize;
dc->vmsd = &vmstate_or_irq;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = platform_bus_realize;
- dc->props = platform_bus_properties;
+ device_class_set_props(dc, platform_bus_properties);
}
static const TypeInfo platform_bus_info = {
vc->get_id = device_vmstate_if_get_id;
}
+void device_class_set_props(DeviceClass *dc, Property *props)
+{
+ dc->props = props;
+}
+
void device_class_set_parent_reset(DeviceClass *dc,
DeviceReset dev_reset,
DeviceReset *parent_reset)
DeviceClass *dc = DEVICE_CLASS(klass);
/* No state to reset or migrate */
- dc->props = split_irq_properties;
+ device_class_set_props(dc, split_irq_properties);
dc->realize = split_irq_realize;
/* Reason: Needs to be wired up to work */
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = a15mp_priv_realize;
- dc->props = a15mp_priv_properties;
+ device_class_set_props(dc, a15mp_priv_properties);
/* We currently have no savable state */
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = a9mp_priv_realize;
- dc->props = a9mp_priv_properties;
+ device_class_set_props(dc, a9mp_priv_properties);
}
static const TypeInfo a9mp_priv_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = mpcore_priv_realize;
- dc->props = mpcore_priv_properties;
+ device_class_set_props(dc, mpcore_priv_properties);
}
static const TypeInfo mpcore_priv_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = cpu_cluster_properties;
+ device_class_set_props(dc, cpu_cluster_properties);
dc->realize = cpu_cluster_realize;
/* This is not directly for users, CPU children must be attached by code */
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = realview_mpcore_realize;
- dc->props = mpcore_rirq_properties;
+ device_class_set_props(dc, mpcore_rirq_properties);
}
static const TypeInfo mpcore_rirq_info = {
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = ati_vga_reset;
- dc->props = ati_vga_properties;
+ device_class_set_props(dc, ati_vga_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = bcm2835_fb_props;
+ device_class_set_props(dc, bcm2835_fb_props);
dc->realize = bcm2835_fb_realize;
dc->reset = bcm2835_fb_reset;
dc->vmsd = &vmstate_bcm2835_fb;
k->romfile = "vgabios-bochs-display.bin";
k->exit = bochs_display_exit;
dc->vmsd = &vmstate_bochs_display;
- dc->props = bochs_display_properties;
+ device_class_set_props(dc, bochs_display_properties);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}
dc->realize = cg3_realizefn;
dc->reset = cg3_reset;
dc->vmsd = &vmstate_cg3;
- dc->props = cg3_properties;
+ device_class_set_props(dc, cg3_properties);
}
static const TypeInfo cg3_info = {
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->desc = "Cirrus CLGD 54xx VGA";
dc->vmsd = &vmstate_pci_cirrus_vga;
- dc->props = pci_vga_cirrus_properties;
+ device_class_set_props(dc, pci_vga_cirrus_properties);
dc->hotpluggable = false;
}
dc->vmsd = &vmstate_cirrus_vga;
dc->realize = isa_cirrus_vga_realizefn;
- dc->props = isa_cirrus_vga_properties;
+ device_class_set_props(dc, isa_cirrus_vga_properties);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}
dc->desc = "G364 framebuffer";
dc->reset = g364fb_sysbus_reset;
dc->vmsd = &vmstate_g364fb;
- dc->props = g364fb_sysbus_properties;
+ device_class_set_props(dc, g364fb_sysbus_properties);
}
static const TypeInfo g364fb_sysbus_info = {
dc->reset = i2c_ddc_reset;
dc->vmsd = &vmstate_i2c_ddc;
- dc->props = i2c_ddc_properties;
+ device_class_set_props(dc, i2c_ddc_properties);
isc->event = i2c_ddc_event;
isc->recv = i2c_ddc_rx;
isc->send = i2c_ddc_tx;
dc->desc = "SysBus Macintosh framebuffer";
dc->reset = macfb_sysbus_reset;
dc->vmsd = &vmstate_macfb;
- dc->props = macfb_sysbus_properties;
+ device_class_set_props(dc, macfb_sysbus_properties);
}
static void macfb_nubus_class_init(ObjectClass *klass, void *data)
dc->desc = "Nubus Macintosh framebuffer";
dc->reset = macfb_nubus_reset;
dc->vmsd = &vmstate_macfb;
- dc->props = macfb_nubus_properties;
+ device_class_set_props(dc, macfb_nubus_properties);
}
static TypeInfo macfb_sysbus_info = {
dc->reset = milkymist_vgafb_reset;
dc->vmsd = &vmstate_milkymist_vgafb;
- dc->props = milkymist_vgafb_properties;
+ device_class_set_props(dc, milkymist_vgafb_properties);
dc->realize = milkymist_vgafb_realize;
}
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->reset = qxl_reset_handler;
dc->vmsd = &qxl_vmstate;
- dc->props = qxl_properties;
+ device_class_set_props(dc, qxl_properties);
}
static const TypeInfo qxl_pci_type_info = {
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->realize = ramfb_realizefn;
- dc->props = ramfb_properties;
+ device_class_set_props(dc, ramfb_properties);
dc->desc = "ram framebuffer standalone device";
dc->user_creatable = true;
}
dc->realize = sm501_realize_sysbus;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->desc = "SM501 Multimedia Companion";
- dc->props = sm501_sysbus_properties;
+ device_class_set_props(dc, sm501_sysbus_properties);
dc->reset = sm501_reset_sysbus;
dc->vmsd = &vmstate_sm501_sysbus;
}
k->class_id = PCI_CLASS_DISPLAY_OTHER;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->desc = "SM501 Display Controller";
- dc->props = sm501_pci_properties;
+ device_class_set_props(dc, sm501_pci_properties);
dc->reset = sm501_reset_pci;
dc->hotpluggable = false;
dc->vmsd = &vmstate_sm501_pci;
dc->realize = tcx_realizefn;
dc->reset = tcx_reset;
dc->vmsd = &vmstate_tcx;
- dc->props = tcx_properties;
+ device_class_set_props(dc, tcx_properties);
}
static const TypeInfo tcx_info = {
dc->realize = vga_isa_realizefn;
dc->reset = vga_isa_reset;
dc->vmsd = &vmstate_vga_common;
- dc->props = vga_isa_properties;
+ device_class_set_props(dc, vga_isa_properties);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}
k->realize = pci_std_vga_realize;
k->romfile = "vgabios-stdvga.bin";
k->class_id = PCI_CLASS_DISPLAY_VGA;
- dc->props = vga_pci_properties;
+ device_class_set_props(dc, vga_pci_properties);
dc->hotpluggable = false;
}
k->realize = pci_secondary_vga_realize;
k->exit = pci_secondary_vga_exit;
k->class_id = PCI_CLASS_DISPLAY_OTHER;
- dc->props = secondary_pci_properties;
+ device_class_set_props(dc, secondary_pci_properties);
dc->reset = pci_secondary_vga_reset;
}
vdc->get_config = vhost_user_gpu_get_config;
vdc->set_config = vhost_user_gpu_set_config;
- dc->props = vhost_user_gpu_properties;
+ device_class_set_props(dc, vhost_user_gpu_properties);
}
static const TypeInfo vhost_user_gpu_info = {
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
- dc->props = virtio_gpu_pci_base_properties;
+ device_class_set_props(dc, virtio_gpu_pci_base_properties);
dc->hotpluggable = false;
k->realize = virtio_gpu_pci_base_realize;
pcidev_k->class_id = PCI_CLASS_DISPLAY_OTHER;
vdc->set_config = virtio_gpu_set_config;
dc->vmsd = &vmstate_virtio_gpu;
- dc->props = virtio_gpu_properties;
+ device_class_set_props(dc, virtio_gpu_properties);
}
static const TypeInfo virtio_gpu_info = {
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
- dc->props = virtio_vga_base_properties;
+ device_class_set_props(dc, virtio_vga_base_properties);
dc->vmsd = &vmstate_virtio_vga_base;
dc->hotpluggable = false;
device_class_set_parent_reset(dc, virtio_vga_base_reset,
k->subsystem_id = SVGA_PCI_DEVICE_ID;
dc->reset = vmsvga_reset;
dc->vmsd = &vmstate_vmware_vga;
- dc->props = vga_vmware_properties;
+ device_class_set_props(dc, vga_vmware_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}
dc->realize = i82374_realize;
dc->vmsd = &vmstate_i82374;
- dc->props = i82374_properties;
+ device_class_set_props(dc, i82374_properties);
}
static const TypeInfo i82374_info = {
dc->realize = i8257_realize;
dc->reset = i8257_reset;
dc->vmsd = &vmstate_i8257;
- dc->props = i8257_properties;
+ device_class_set_props(dc, i8257_properties);
idc->get_transfer_mode = i8257_dma_get_transfer_mode;
idc->has_autoinitialization = i8257_dma_has_autoinitialization;
dc->vmsd = &vmstate_pl080;
dc->realize = pl080_realize;
- dc->props = pl080_properties;
+ device_class_set_props(dc, pl080_properties);
dc->reset = pl080_reset;
}
dc->realize = pl330_realize;
dc->reset = pl330_reset;
- dc->props = pl330_properties;
+ device_class_set_props(dc, pl330_properties);
dc->vmsd = &vmstate_pl330;
}
dc->desc = "PXA2xx DMA controller";
dc->vmsd = &vmstate_pxa2xx_dma;
- dc->props = pxa2xx_dma_properties;
+ device_class_set_props(dc, pxa2xx_dma_properties);
dc->realize = pxa2xx_dma_realize;
}
dc->realize = xilinx_axidma_realize,
dc->reset = xilinx_axidma_reset;
- dc->props = axidma_properties;
+ device_class_set_props(dc, axidma_properties);
}
static StreamSlaveClass xilinx_axidma_data_stream_class = {
dc->reset = zdma_reset;
dc->realize = zdma_realize;
- dc->props = zdma_props;
+ device_class_set_props(dc, zdma_props);
dc->vmsd = &vmstate_zdma;
}
dc->realize = imx_gpio_realize;
dc->reset = imx_gpio_reset;
- dc->props = imx_gpio_properties;
+ device_class_set_props(dc, imx_gpio_properties);
dc->vmsd = &vmstate_imx_gpio;
dc->desc = "i.MX GPIO controller";
}
dc->realize = omap_gpio_realize;
dc->reset = omap_gpif_reset;
- dc->props = omap_gpio_properties;
+ device_class_set_props(dc, omap_gpio_properties);
/* Reason: pointer property "clk" */
dc->user_creatable = false;
}
dc->realize = omap2_gpio_realize;
dc->reset = omap2_gpif_reset;
- dc->props = omap2_gpio_properties;
+ device_class_set_props(dc, omap2_gpio_properties);
/* Reason: pointer properties "iclk", "fclk0", ..., "fclk5" */
dc->user_creatable = false;
}
dc->vmsd = &aspeed_i2c_vmstate;
dc->reset = aspeed_i2c_reset;
- dc->props = aspeed_i2c_properties;
+ device_class_set_props(dc, aspeed_i2c_properties);
dc->realize = aspeed_i2c_realize;
dc->desc = "Aspeed I2C Controller";
}
DeviceClass *k = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_MISC, k->categories);
k->bus_type = TYPE_I2C_BUS;
- k->props = i2c_props;
+ device_class_set_props(k, i2c_props);
}
static const TypeInfo i2c_slave_type_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = omap_i2c_properties;
+ device_class_set_props(dc, omap_i2c_properties);
dc->reset = omap_i2c_reset;
/* Reason: pointer properties "iclk", "fclk" */
dc->user_creatable = false;
dc->reset = vtd_reset;
dc->vmsd = &vtd_vmstate;
- dc->props = vtd_properties;
+ device_class_set_props(dc, vtd_properties);
dc->hotpluggable = false;
x86_class->realize = vtd_realize;
x86_class->int_remap = vtd_int_remap;
dc->realize = kvmclock_realize;
dc->vmsd = &kvmclock_vmsd;
- dc->props = kvmclock_properties;
+ device_class_set_props(dc, kvmclock_properties);
}
static const TypeInfo kvmclock_info = {
k->set_channel_gate = kvm_pit_set_gate;
k->get_channel_info = kvm_pit_get_channel_info;
dc->reset = kvm_pit_reset;
- dc->props = kvm_pit_properties;
+ device_class_set_props(dc, kvm_pit_properties);
}
static const TypeInfo kvm_pit_info = {
k->pre_save = kvm_ioapic_get;
k->post_load = kvm_ioapic_put;
dc->reset = kvm_ioapic_reset;
- dc->props = kvm_ioapic_properties;
+ device_class_set_props(dc, kvm_ioapic_properties);
}
static const TypeInfo kvm_ioapic_info = {
dc->realize = vmmouse_realizefn;
dc->reset = vmmouse_reset;
dc->vmsd = &vmstate_vmmouse;
- dc->props = vmmouse_properties;
+ device_class_set_props(dc, vmmouse_properties);
}
static const TypeInfo vmmouse_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = x86_iommu_realize;
- dc->props = x86_iommu_properties;
+ device_class_set_props(dc, x86_iommu_properties);
}
bool x86_iommu_ir_supported(X86IOMMUState *s)
k->realize = xen_pv_realize;
k->class_id = PCI_CLASS_SYSTEM_OTHER;
dc->desc = "Xen PV Device";
- dc->props = xen_pv_props;
+ device_class_set_props(dc, xen_pv_props);
dc->vmsd = &vmstate_xen_pvdevice;
}
dc->realize = sysbus_ahci_realize;
dc->vmsd = &vmstate_sysbus_ahci;
- dc->props = sysbus_ahci_properties;
+ device_class_set_props(dc, sysbus_ahci_properties);
dc->reset = sysbus_ahci_reset;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
k->class_id = PCI_CLASS_STORAGE_IDE;
k->config_read = cmd646_pci_config_read;
k->config_write = cmd646_pci_config_write;
- dc->props = cmd646_ide_properties;
+ device_class_set_props(dc, cmd646_ide_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
dc->realize = isa_ide_realizefn;
dc->fw_name = "ide";
dc->reset = isa_ide_reset;
- dc->props = isa_ide_properties;
+ device_class_set_props(dc, isa_ide_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
dc->realize = macio_ide_realizefn;
dc->reset = macio_ide_reset;
- dc->props = macio_ide_properties;
+ device_class_set_props(dc, macio_ide_properties);
dc->vmsd = &vmstate_pmac;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
dc->realize = mmio_ide_realizefn;
dc->reset = mmio_ide_reset;
- dc->props = mmio_ide_properties;
+ device_class_set_props(dc, mmio_ide_properties);
dc->vmsd = &vmstate_ide_mmio;
}
k->realize = ide_hd_realize;
dc->fw_name = "drive";
dc->desc = "virtual IDE disk";
- dc->props = ide_hd_properties;
+ device_class_set_props(dc, ide_hd_properties);
}
static const TypeInfo ide_hd_info = {
k->realize = ide_cd_realize;
dc->fw_name = "drive";
dc->desc = "virtual IDE CD-ROM";
- dc->props = ide_cd_properties;
+ device_class_set_props(dc, ide_cd_properties);
}
static const TypeInfo ide_cd_info = {
k->realize = ide_drive_realize;
dc->fw_name = "drive";
dc->desc = "virtual IDE disk or CD-ROM (legacy)";
- dc->props = ide_drive_properties;
+ device_class_set_props(dc, ide_drive_properties);
}
static const TypeInfo ide_drive_info = {
k->realize = ide_qdev_realize;
set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
k->bus_type = TYPE_IDE_BUS;
- k->props = ide_props;
+ device_class_set_props(k, ide_props);
}
static const TypeInfo ide_device_type_info = {
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = adb_device_realizefn;
- dc->props = adb_device_properties;
+ device_class_set_props(dc, adb_device_properties);
dc->bus_type = TYPE_ADB_BUS;
}
dc->realize = milkymist_softusb_realize;
dc->reset = milkymist_softusb_reset;
dc->vmsd = &vmstate_milkymist_softusb;
- dc->props = milkymist_softusb_properties;
+ device_class_set_props(dc, milkymist_softusb_properties);
}
static const TypeInfo milkymist_softusb_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
VirtIOInputClass *vic = VIRTIO_INPUT_CLASS(klass);
- dc->props = virtio_input_hid_properties;
+ device_class_set_props(dc, virtio_input_hid_properties);
vic->realize = virtio_input_hid_realize;
vic->unrealize = virtio_input_hid_unrealize;
vic->change_active = virtio_input_hid_change_active;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = virtio_mouse_properties;
+ device_class_set_props(dc, virtio_mouse_properties);
}
static void virtio_mouse_init(Object *obj)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = virtio_tablet_properties;
+ device_class_set_props(dc, virtio_tablet_properties);
}
static void virtio_tablet_init(Object *obj)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_virtio_input_host;
- dc->props = virtio_input_host_properties;
+ device_class_set_props(dc, virtio_input_host_properties);
vic->realize = virtio_input_host_realize;
vic->unrealize = virtio_input_host_unrealize;
vic->handle_status = virtio_input_host_handle_status;
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_input_properties;
+ device_class_set_props(dc, virtio_input_properties);
dc->vmsd = &vmstate_virtio_input;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
vdc->realize = virtio_input_device_realize;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = apic_reset_common;
- dc->props = apic_properties_common;
+ device_class_set_props(dc, apic_properties_common);
dc->realize = apic_common_realize;
dc->unrealize = apic_common_unrealize;
/*
dc->reset = arm_gic_common_reset;
dc->realize = arm_gic_common_realize;
- dc->props = arm_gic_common_properties;
+ device_class_set_props(dc, arm_gic_common_properties);
dc->vmsd = &vmstate_gic;
albifc->arm_linux_init = arm_gic_common_linux_init;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = gicv2m_properties;
+ device_class_set_props(dc, gicv2m_properties);
dc->realize = gicv2m_realize;
}
dc->reset = arm_gicv3_common_reset;
dc->realize = arm_gicv3_common_realize;
- dc->props = arm_gicv3_common_properties;
+ device_class_set_props(dc, arm_gicv3_common_properties);
dc->vmsd = &vmstate_gicv3;
albifc->arm_linux_init = arm_gic_common_linux_init;
}
KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
dc->realize = kvm_arm_its_realize;
- dc->props = kvm_arm_its_props;
+ device_class_set_props(dc, kvm_arm_its_props);
device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
icc->send_msi = kvm_its_send_msi;
icc->pre_save = kvm_arm_its_pre_save;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_nvic;
- dc->props = props_nvic;
+ device_class_set_props(dc, props_nvic);
dc->reset = armv7m_nvic_reset;
dc->realize = armv7m_nvic_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = exynos4210_combiner_reset;
- dc->props = exynos4210_combiner_properties;
+ device_class_set_props(dc, exynos4210_combiner_properties);
dc->vmsd = &vmstate_exynos4210_combiner;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = exynos4210_gic_properties;
+ device_class_set_props(dc, exynos4210_gic_properties);
dc->realize = exynos4210_gic_realize;
}
dc->reset = exynos4210_irq_gate_reset;
dc->vmsd = &vmstate_exynos4210_irq_gate;
- dc->props = exynos4210_irq_gate_properties;
+ device_class_set_props(dc, exynos4210_irq_gate_properties);
dc->realize = exynos4210_irq_gate_realize;
}
InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
dc->vmsd = &vmstate_pic_common;
- dc->props = pic_properties_common;
+ device_class_set_props(dc, pic_properties_common);
dc->realize = pic_common_realize;
/*
* Reason: unlike ordinary ISA devices, the PICs need additional
*/
k->post_load = ioapic_update_kvm_routes;
dc->reset = ioapic_reset_common;
- dc->props = ioapic_properties;
+ device_class_set_props(dc, ioapic_properties);
}
static const TypeInfo ioapic_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = mips_gic_properties;
+ device_class_set_props(dc, mips_gic_properties);
dc->realize = mips_gic_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = omap_inth_reset;
- dc->props = omap_intc_properties;
+ device_class_set_props(dc, omap_intc_properties);
/* Reason: pointer property "clk" */
dc->user_creatable = false;
dc->realize = omap_intc_realize;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = omap_inth_reset;
- dc->props = omap2_intc_properties;
+ device_class_set_props(dc, omap2_intc_properties);
/* Reason: pointer property "iclk", "fclk" */
dc->user_creatable = false;
dc->realize = omap2_intc_realize;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = or1k_ompic_properties;
+ device_class_set_props(dc, or1k_ompic_properties);
dc->realize = or1k_ompic_realize;
dc->vmsd = &vmstate_or1k_ompic;
}
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = openpic_realize;
- dc->props = openpic_properties;
+ device_class_set_props(dc, openpic_properties);
dc->reset = openpic_reset;
dc->vmsd = &vmstate_openpic;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = kvm_openpic_realize;
- dc->props = kvm_openpic_properties;
+ device_class_set_props(dc, kvm_openpic_properties);
dc->reset = kvm_openpic_reset;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
dc->desc = "PowerNV XIVE Interrupt Controller";
device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize);
dc->realize = pnv_xive_realize;
- dc->props = pnv_xive_properties;
+ device_class_set_props(dc, pnv_xive_properties);
xrc->get_eas = pnv_xive_get_eas;
xrc->get_end = pnv_xive_get_end;
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->props = s390_flic_common_properties;
+ device_class_set_props(dc, s390_flic_common_properties);
dc->realize = s390_flic_common_realize;
}
SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass);
dc->desc = "sPAPR XIVE Interrupt Controller";
- dc->props = spapr_xive_properties;
+ device_class_set_props(dc, spapr_xive_properties);
device_class_set_parent_realize(dc, spapr_xive_realize,
&sxc->parent_realize);
dc->vmsd = &vmstate_spapr_xive;
dc->realize = icp_realize;
dc->unrealize = icp_unrealize;
- dc->props = icp_properties;
+ device_class_set_props(dc, icp_properties);
/*
* Reason: part of XICS interrupt controller, needs to be wired up
* by icp_create().
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ics_realize;
- dc->props = ics_properties;
+ device_class_set_props(dc, ics_properties);
dc->reset = ics_reset;
dc->vmsd = &vmstate_ics;
/*
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = xilinx_intc_properties;
+ device_class_set_props(dc, xilinx_intc_properties);
}
static const TypeInfo xilinx_intc_info = {
dc->desc = "XIVE Interrupt Thread Context";
dc->realize = xive_tctx_realize;
dc->vmsd = &vmstate_xive_tctx;
- dc->props = xive_tctx_properties;
+ device_class_set_props(dc, xive_tctx_properties);
/*
* Reason: part of XIVE interrupt controller, needs to be wired up
* by xive_tctx_create().
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "XIVE Interrupt Source";
- dc->props = xive_source_properties;
+ device_class_set_props(dc, xive_source_properties);
dc->realize = xive_source_realize;
dc->vmsd = &vmstate_xive_source;
/*
XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
dc->desc = "XIVE Router Engine";
- dc->props = xive_router_properties;
+ device_class_set_props(dc, xive_router_properties);
/* Parent is SysBusDeviceClass. No need to call its realize hook */
dc->realize = xive_router_realize;
xnc->notify = xive_router_notify;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "XIVE END Source";
- dc->props = xive_end_source_properties;
+ device_class_set_props(dc, xive_end_source_properties);
dc->realize = xive_end_source_realize;
/*
* Reason: part of XIVE interrupt controller, needs to be wired up,
dc->reset = xlnx_pmu_io_intc_reset;
dc->realize = xlnx_pmu_io_intc_realize;
dc->vmsd = &vmstate_xlnx_pmu_io_intc;
- dc->props = xlnx_pmu_io_intc_properties;
+ device_class_set_props(dc, xlnx_pmu_io_intc_properties);
}
static const TypeInfo xlnx_pmu_io_intc_info = {
k->bus_type = TYPE_IPACK_BUS;
k->realize = ipack_device_realize;
k->unrealize = ipack_device_unrealize;
- k->props = ipack_device_props;
+ device_class_set_props(k, ipack_device_props);
}
const VMStateDescription vmstate_ipack_device = {
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->props = ipmi_bmc_properties;
+ device_class_set_props(dc, ipmi_bmc_properties);
}
static TypeInfo ipmi_bmc_type_info = {
bk->handle_reset = ipmi_bmc_extern_handle_reset;
dc->hotpluggable = false;
dc->realize = ipmi_bmc_extern_realize;
- dc->props = ipmi_bmc_extern_properties;
+ device_class_set_props(dc, ipmi_bmc_extern_properties);
}
static const TypeInfo ipmi_bmc_extern_type = {
dc->hotpluggable = false;
dc->realize = ipmi_sim_realize;
- dc->props = ipmi_sim_properties;
+ device_class_set_props(dc, ipmi_sim_properties);
bk->handle_command = ipmi_sim_handle_command;
}
IPMIInterfaceClass *iic = IPMI_INTERFACE_CLASS(oc);
dc->realize = isa_ipmi_bt_realize;
- dc->props = ipmi_isa_properties;
+ device_class_set_props(dc, ipmi_isa_properties);
iic->get_backend_data = isa_ipmi_bt_get_backend_data;
ipmi_bt_class_init(iic);
IPMIInterfaceClass *iic = IPMI_INTERFACE_CLASS(oc);
dc->realize = ipmi_isa_realize;
- dc->props = ipmi_isa_properties;
+ device_class_set_props(dc, ipmi_isa_properties);
iic->get_backend_data = isa_ipmi_kcs_get_backend_data;
ipmi_kcs_class_init(iic);
dc->reset = ich9_lpc_reset;
k->realize = ich9_lpc_realize;
dc->vmsd = &vmstate_ich9_lpc;
- dc->props = ich9_lpc_properties;
+ device_class_set_props(dc, ich9_lpc_properties);
k->config_write = ich9_lpc_config_write;
dc->desc = "ICH9 LPC bridge";
k->vendor_id = PCI_VENDOR_ID_INTEL;
dc->realize = pc87312_realize;
dc->reset = pc87312_reset;
dc->vmsd = &vmstate_pc87312;
- dc->props = pc87312_properties;
+ device_class_set_props(dc, pc87312_properties);
sc->parallel = (ISASuperIOFuncs){
.count = 1,
dc->desc = "PM";
dc->vmsd = &vmstate_acpi;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->props = via_pm_properties;
+ device_class_set_props(dc, via_pm_properties);
}
static const TypeInfo via_pm_info = {
ddc->realize = nvdimm_realize;
mdc->get_memory_region = nvdimm_md_get_memory_region;
- dc->props = nvdimm_properties;
+ device_class_set_props(dc, nvdimm_properties);
nvc->read_label_data = nvdimm_read_label_data;
nvc->write_label_data = nvdimm_write_label_data;
dc->realize = pc_dimm_realize;
dc->unrealize = pc_dimm_unrealize;
- dc->props = pc_dimm_properties;
+ device_class_set_props(dc, pc_dimm_properties);
dc->desc = "DIMM memory module";
ddc->get_vmstate_memory_region = pc_dimm_get_memory_region;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = mips_cps_realize;
- dc->props = mips_cps_properties;
+ device_class_set_props(dc, mips_cps_properties);
}
static const TypeInfo mips_cps_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = a9_scu_properties;
+ device_class_set_props(dc, a9_scu_properties);
dc->vmsd = &vmstate_a9_scu;
dc->reset = a9_scu_reset;
}
dc->realize = applesmc_isa_realize;
dc->reset = qdev_applesmc_isa_reset;
- dc->props = applesmc_isa_properties;
+ device_class_set_props(dc, applesmc_isa_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = arm11_scu_realize;
- dc->props = arm11_scu_properties;
+ device_class_set_props(dc, arm11_scu_properties);
}
static const TypeInfo arm11_scu_type_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_l2x0;
- dc->props = l2x0_properties;
+ device_class_set_props(dc, l2x0_properties);
dc->reset = l2x0_priv_reset;
}
dc->realize = arm_sysctl_realize;
dc->reset = arm_sysctl_reset;
dc->vmsd = &vmstate_arm_sysctl;
- dc->props = arm_sysctl_properties;
+ device_class_set_props(dc, arm_sysctl_properties);
}
static const TypeInfo arm_sysctl_info = {
* does not need a reset function or VMState.
*/
- dc->props = armsse_cpuid_props;
+ device_class_set_props(dc, armsse_cpuid_props);
}
static const TypeInfo armsse_cpuid_info = {
dc->reset = aspeed_scu_reset;
dc->desc = "ASPEED System Control Unit";
dc->vmsd = &vmstate_aspeed_scu;
- dc->props = aspeed_scu_properties;
+ device_class_set_props(dc, aspeed_scu_properties);
}
static const TypeInfo aspeed_scu_info = {
dc->reset = aspeed_sdmc_reset;
dc->desc = "ASPEED SDRAM Memory Controller";
dc->vmsd = &vmstate_aspeed_sdmc;
- dc->props = aspeed_sdmc_properties;
+ device_class_set_props(dc, aspeed_sdmc_properties);
}
static const TypeInfo aspeed_sdmc_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = bcm2835_property_props;
+ device_class_set_props(dc, bcm2835_property_props);
dc->realize = bcm2835_property_realize;
dc->vmsd = &vmstate_bcm2835_property;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = debug_exit_realizefn;
- dc->props = debug_exit_properties;
+ device_class_set_props(dc, debug_exit_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
dc->realize = ecc_realize;
dc->reset = ecc_reset;
dc->vmsd = &vmstate_ecc;
- dc->props = ecc_properties;
+ device_class_set_props(dc, ecc_properties);
}
static const TypeInfo ecc_info = {
dc->vmsd = &iotkit_sysctl_vmstate;
dc->reset = iotkit_sysctl_reset;
- dc->props = iotkit_sysctl_props;
+ device_class_set_props(dc, iotkit_sysctl_props);
dc->realize = iotkit_sysctl_realize;
}
* does not need a reset function or VMState.
*/
- dc->props = iotkit_sysinfo_props;
+ device_class_set_props(dc, iotkit_sysinfo_props);
}
static const TypeInfo iotkit_sysinfo_info = {
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->realize = ivshmem_plain_realize;
- dc->props = ivshmem_plain_properties;
+ device_class_set_props(dc, ivshmem_plain_properties);
dc->vmsd = &ivshmem_plain_vmsd;
}
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->realize = ivshmem_doorbell_realize;
- dc->props = ivshmem_doorbell_properties;
+ device_class_set_props(dc, ivshmem_doorbell_properties);
dc->vmsd = &ivshmem_doorbell_vmsd;
}
dc->realize = mac_via_realize;
dc->reset = mac_via_reset;
dc->vmsd = &vmstate_mac_via;
- dc->props = mac_via_properties;
+ device_class_set_props(dc, mac_via_properties);
}
static TypeInfo mac_via_info = {
dc->realize = cuda_realize;
dc->reset = cuda_reset;
dc->vmsd = &vmstate_cuda;
- dc->props = cuda_properties;
+ device_class_set_props(dc, cuda_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
pdc->realize = macio_newworld_realize;
pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
dc->vmsd = &vmstate_macio_newworld;
- dc->props = macio_newworld_properties;
+ device_class_set_props(dc, macio_newworld_properties);
}
static Property macio_properties[] = {
k->vendor_id = PCI_VENDOR_ID_APPLE;
k->class_id = PCI_CLASS_OTHERS << 8;
- dc->props = macio_properties;
+ device_class_set_props(dc, macio_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
/* Reason: Uses serial_hds in macio_instance_init */
dc->user_creatable = false;
dc->realize = pmu_realize;
dc->reset = pmu_reset;
dc->vmsd = &vmstate_pmu;
- dc->props = pmu_properties;
+ device_class_set_props(dc, pmu_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
static void mips_gcr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = mips_gcr_properties;
+ device_class_set_props(dc, mips_gcr_properties);
dc->vmsd = &vmstate_mips_gcr;
dc->reset = mips_gcr_reset;
dc->realize = mips_gcr_realize;
dc->realize = mips_cpc_realize;
dc->reset = mips_cpc_reset;
dc->vmsd = &vmstate_mips_cpc;
- dc->props = mips_cpc_properties;
+ device_class_set_props(dc, mips_cpc_properties);
}
static const TypeInfo mips_cpc_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = mips_itu_properties;
+ device_class_set_props(dc, mips_itu_properties);
dc->realize = mips_itu_realize;
dc->reset = mips_itu_reset;
}
dc->reset = mos6522_reset;
dc->vmsd = &vmstate_mos6522;
- dc->props = mos6522_properties;
+ device_class_set_props(dc, mos6522_properties);
mdc->parent_reset = dc->reset;
mdc->set_sr_int = mos6522_set_sr_int;
mdc->portB_write = mos6522_portB_write;
dc->vmsd = &mps2_fpgaio_vmstate;
dc->reset = mps2_fpgaio_reset;
- dc->props = mps2_fpgaio_properties;
+ device_class_set_props(dc, mps2_fpgaio_properties);
}
static const TypeInfo mps2_fpgaio_info = {
dc->realize = mps2_scc_realize;
dc->vmsd = &mps2_scc_vmstate;
dc->reset = mps2_scc_reset;
- dc->props = mps2_scc_properties;
+ device_class_set_props(dc, mps2_scc_properties);
}
static const TypeInfo mps2_scc_info = {
dc->vmsd = &vmstate_msf2_sysreg;
dc->reset = msf2_sysreg_reset;
- dc->props = msf2_sysreg_properties;
+ device_class_set_props(dc, msf2_sysreg_properties);
dc->realize = msf2_sysreg_realize;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = nrf51_rng_properties;
+ device_class_set_props(dc, nrf51_rng_properties);
dc->vmsd = &vmstate_rng;
dc->reset = nrf51_rng_reset;
}
dc->desc = "PCI Test Device";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->reset = qdev_pci_testdev_reset;
- dc->props = pci_testdev_properties;
+ device_class_set_props(dc, pci_testdev_properties);
}
static const TypeInfo pci_testdev_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pvpanic_isa_realizefn;
- dc->props = pvpanic_isa_properties;
+ device_class_set_props(dc, pvpanic_isa_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
dc->realize = tz_mpc_realize;
dc->vmsd = &tz_mpc_vmstate;
dc->reset = tz_mpc_reset;
- dc->props = tz_mpc_properties;
+ device_class_set_props(dc, tz_mpc_properties);
}
static const TypeInfo tz_mpc_info = {
dc->realize = tz_msc_realize;
dc->vmsd = &tz_msc_vmstate;
dc->reset = tz_msc_reset;
- dc->props = tz_msc_properties;
+ device_class_set_props(dc, tz_msc_properties);
}
static const TypeInfo tz_msc_info = {
dc->realize = tz_ppc_realize;
dc->vmsd = &tz_ppc_vmstate;
dc->reset = tz_ppc_reset;
- dc->props = tz_ppc_properties;
+ device_class_set_props(dc, tz_ppc_properties);
}
static const TypeInfo tz_ppc_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = unimp_realize;
- dc->props = unimp_properties;
+ device_class_set_props(dc, unimp_properties);
}
static const TypeInfo unimp_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aw_emac_realize;
- dc->props = aw_emac_properties;
+ device_class_set_props(dc, aw_emac_properties);
dc->reset = aw_emac_reset;
dc->vmsd = &vmstate_aw_emac;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = gem_realize;
- dc->props = gem_properties;
+ device_class_set_props(dc, gem_properties);
dc->vmsd = &vmstate_cadence_gem;
dc->reset = gem_reset;
}
dc->realize = dp8393x_realize;
dc->reset = dp8393x_reset;
dc->vmsd = &vmstate_dp8393x;
- dc->props = dp8393x_properties;
+ device_class_set_props(dc, dp8393x_properties);
}
static const TypeInfo dp8393x_info = {
dc->desc = "Intel Gigabit Ethernet";
dc->reset = qdev_e1000_reset;
dc->vmsd = &vmstate_e1000;
- dc->props = e1000_properties;
+ device_class_set_props(dc, e1000_properties);
}
static void e1000_instance_init(Object *obj)
dc->desc = "Intel 82574L GbE Controller";
dc->reset = e1000e_qdev_reset;
dc->vmsd = &e1000e_vmstate;
- dc->props = e1000e_properties;
e1000e_prop_disable_vnet = qdev_prop_uint8;
e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
e1000e_prop_subsys = qdev_prop_uint16;
e1000e_prop_subsys.description = "PCI device Subsystem ID";
+ device_class_set_props(dc, e1000e_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
info = eepro100_get_class_by_name(object_class_get_name(klass));
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
- dc->props = e100_properties;
+ device_class_set_props(dc, e100_properties);
dc->desc = info->desc;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->realize = etraxfs_eth_realize;
dc->reset = etraxfs_eth_reset;
- dc->props = etraxfs_eth_properties;
+ device_class_set_props(dc, etraxfs_eth_properties);
/* Reason: dma_out, dma_in are not user settable */
dc->user_creatable = false;
}
dc->realize = etsec_realize;
dc->reset = etsec_reset;
- dc->props = etsec_properties;
+ device_class_set_props(dc, etsec_properties);
/* Supported by ppce500 machine */
dc->user_creatable = true;
}
dc->vmsd = &vmstate_ftgmac100;
dc->reset = ftgmac100_reset;
- dc->props = ftgmac100_properties;
+ device_class_set_props(dc, ftgmac100_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->realize = ftgmac100_realize;
dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
dc->reset = aspeed_mii_reset;
dc->realize = aspeed_mii_realize;
dc->desc = "Aspeed MII controller";
- dc->props = aspeed_mii_properties;
+ device_class_set_props(dc, aspeed_mii_properties);
}
static const TypeInfo aspeed_mii_info = {
dc->vmsd = &vmstate_imx_eth;
dc->reset = imx_eth_reset;
- dc->props = imx_eth_properties;
+ device_class_set_props(dc, imx_eth_properties);
dc->realize = imx_eth_realize;
dc->desc = "i.MX FEC/ENET Ethernet Controller";
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = lan9118_reset;
- dc->props = lan9118_properties;
+ device_class_set_props(dc, lan9118_properties);
dc->vmsd = &vmstate_lan9118;
dc->realize = lan9118_realize;
}
dc->fw_name = "ethernet";
dc->reset = lance_reset;
dc->vmsd = &vmstate_lance;
- dc->props = lance_properties;
+ device_class_set_props(dc, lance_properties);
}
static const TypeInfo lance_info = {
dc->realize = mcf_fec_realize;
dc->desc = "MCF Fast Ethernet Controller network device";
dc->reset = mcf_fec_reset;
- dc->props = mcf_fec_properties;
+ device_class_set_props(dc, mcf_fec_properties);
}
static const TypeInfo mcf_fec_info = {
dc->realize = milkymist_minimac2_realize;
dc->reset = milkymist_minimac2_reset;
dc->vmsd = &vmstate_milkymist_minimac2;
- dc->props = milkymist_minimac2_properties;
+ device_class_set_props(dc, milkymist_minimac2_properties);
}
static const TypeInfo milkymist_minimac2_info = {
dc->desc = "MIPS Simulator network device";
dc->reset = mipsnet_sysbus_reset;
dc->vmsd = &vmstate_mipsnet;
- dc->props = mipsnet_properties;
+ device_class_set_props(dc, mipsnet_properties);
}
static const TypeInfo mipsnet_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = isa_ne2000_realizefn;
- dc->props = ne2000_isa_properties;
+ device_class_set_props(dc, ne2000_isa_properties);
dc->vmsd = &vmstate_isa_ne2000;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
k->device_id = PCI_DEVICE_ID_REALTEK_8029;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->vmsd = &vmstate_pci_ne2000;
- dc->props = ne2000_properties;
+ device_class_set_props(dc, ne2000_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->desc = "Opencores 10/100 Mbit Ethernet";
dc->reset = qdev_open_eth_reset;
- dc->props = open_eth_properties;
+ device_class_set_props(dc, open_eth_properties);
}
static const TypeInfo open_eth_info = {
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->reset = pci_reset;
dc->vmsd = &vmstate_pci_pcnet;
- dc->props = pcnet_properties;
+ device_class_set_props(dc, pcnet_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->desc = "Rocker Switch";
dc->reset = rocker_reset;
- dc->props = rocker_properties;
+ device_class_set_props(dc, rocker_properties);
dc->vmsd = &rocker_vmsd;
}
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->reset = rtl8139_reset;
dc->vmsd = &vmstate_rtl8139;
- dc->props = rtl8139_properties;
+ device_class_set_props(dc, rtl8139_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
dc->realize = smc91c111_realize;
dc->reset = smc91c111_reset;
dc->vmsd = &vmstate_smc91c111;
- dc->props = smc91c111_properties;
+ device_class_set_props(dc, smc91c111_properties);
}
static const TypeInfo smc91c111_info = {
k->dt_compatible = "IBM,l-lan";
k->signal_mask = 0x1;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
- dc->props = spapr_vlan_properties;
+ device_class_set_props(dc, spapr_vlan_properties);
k->rtce_window_size = 0x10000000;
dc->vmsd = &vmstate_spapr_llan;
}
dc->realize = stellaris_enet_realize;
dc->reset = stellaris_enet_reset;
- dc->props = stellaris_enet_properties;
+ device_class_set_props(dc, stellaris_enet_properties);
dc->vmsd = &vmstate_stellaris_enet;
}
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->vmsd = &vmstate_sungem;
dc->reset = sungem_reset;
- dc->props = sungem_properties;
+ device_class_set_props(dc, sungem_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->vmsd = &vmstate_hme;
dc->reset = sunhme_reset;
- dc->props = sunhme_properties;
+ device_class_set_props(dc, sunhme_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
k->subsystem_id = 0x104f;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
dc->vmsd = &vmstate_pci_tulip;
- dc->props = tulip_properties;
+ device_class_set_props(dc, tulip_properties);
dc->reset = tulip_qdev_reset;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_net_properties;
+ device_class_set_props(dc, virtio_net_properties);
dc->vmsd = &vmstate_virtio_net;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
vdc->realize = virtio_net_device_realize;
dc->desc = "VMWare Paravirtualized Ethernet v3";
dc->reset = vmxnet3_qdev_reset;
dc->vmsd = &vmstate_vmxnet3;
- dc->props = vmxnet3_properties;
+ device_class_set_props(dc, vmxnet3_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
dc->realize = xgmac_enet_realize;
dc->vmsd = &vmstate_xgmac;
- dc->props = xgmac_properties;
+ device_class_set_props(dc, xgmac_properties);
}
static const TypeInfo xgmac_enet_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xilinx_enet_realize;
- dc->props = xilinx_enet_properties;
+ device_class_set_props(dc, xilinx_enet_properties);
dc->reset = xilinx_axienet_reset;
}
dc->realize = xilinx_ethlite_realize;
dc->reset = xilinx_ethlite_reset;
- dc->props = xilinx_ethlite_properties;
+ device_class_set_props(dc, xilinx_ethlite_properties);
}
static const TypeInfo xilinx_ethlite_info = {
dc->realize = nvram_sysbus_realize;
dc->vmsd = &vmstate_nvram;
- dc->props = nvram_sysbus_properties;
+ device_class_set_props(dc, nvram_sysbus_properties);
}
static const TypeInfo nvram_sysbus_info = {
k->recv = &at24c_eeprom_recv;
k->send = &at24c_eeprom_send;
- dc->props = at24c_eeprom_props;
+ device_class_set_props(dc, at24c_eeprom_props);
dc->reset = at24c_eeprom_reset;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = fw_cfg_io_realize;
- dc->props = fw_cfg_io_properties;
+ device_class_set_props(dc, fw_cfg_io_properties);
}
static const TypeInfo fw_cfg_io_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = fw_cfg_mem_realize;
- dc->props = fw_cfg_mem_properties;
+ device_class_set_props(dc, fw_cfg_mem_properties);
}
static const TypeInfo fw_cfg_mem_info = {
dc->unrealize = macio_nvram_unrealizefn;
dc->reset = macio_nvram_reset;
dc->vmsd = &vmstate_macio_nvram;
- dc->props = macio_nvram_properties;
+ device_class_set_props(dc, macio_nvram_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = nrf51_nvm_properties;
+ device_class_set_props(dc, nrf51_nvm_properties);
dc->vmsd = &vmstate_nvm;
dc->realize = nrf51_nvm_realize;
dc->reset = nrf51_nvm_reset;
k->dt_type = "nvram";
k->dt_compatible = "qemu,spapr-nvram";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = spapr_nvram_properties;
+ device_class_set_props(dc, spapr_nvram_properties);
dc->vmsd = &vmstate_spapr_nvram;
/* Reason: Internal device only, uses spapr_rtas_register() in realize() */
dc->user_creatable = false;
k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
dc->desc = "PCI Express Root Port";
dc->vmsd = &vmstate_rp_dev;
- dc->props = gen_rp_props;
+ device_class_set_props(dc, gen_rp_props);
device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
k->is_bridge = true;
dc->desc = "Standard PCI Bridge";
dc->reset = qdev_pci_bridge_dev_reset;
- dc->props = pci_bridge_dev_properties;
+ device_class_set_props(dc, pci_bridge_dev_properties);
dc->vmsd = &pci_bridge_dev_vmstate;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
hc->plug = pci_bridge_dev_plug_cb;
k->class_id = PCI_CLASS_BRIDGE_HOST;
dc->desc = "PCI Expander Bridge";
- dc->props = pxb_dev_properties;
+ device_class_set_props(dc, pxb_dev_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
k->class_id = PCI_CLASS_BRIDGE_HOST;
dc->desc = "PCI Express Expander Bridge";
- dc->props = pxb_dev_properties;
+ device_class_set_props(dc, pxb_dev_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
k->exit = pcie_pci_bridge_exit;
k->config_write = pcie_pci_bridge_write_config;
dc->vmsd = &pcie_pci_bridge_dev_vmstate;
- dc->props = pcie_pci_bridge_dev_properties;
+ device_class_set_props(dc, pcie_pci_bridge_dev_properties);
dc->reset = &pcie_pci_bridge_reset;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
hc->plug = pci_bridge_dev_plug_cb;
k->exit = rp_exit;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->reset = rp_reset;
- dc->props = rp_props;
+ device_class_set_props(dc, rp_props);
}
static const TypeInfo rp_info = {
dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
dc->reset = xio3130_downstream_reset;
dc->vmsd = &vmstate_xio3130_downstream;
- dc->props = xio3130_downstream_props;
+ device_class_set_props(dc, xio3130_downstream_props);
}
static const TypeInfo xio3130_downstream_info = {
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
dc->realize = grackle_realize;
- dc->props = grackle_properties;
+ device_class_set_props(dc, grackle_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "pci";
sbc->explicit_ofw_unit_address = grackle_ofw_unit_address;
hc->root_bus_path = i440fx_pcihost_root_bus_path;
dc->realize = i440fx_pcihost_realize;
dc->fw_name = "pci";
- dc->props = i440fx_props;
+ device_class_set_props(dc, i440fx_props);
/* Reason: needs to be wired up by pc_init1 */
dc->user_creatable = false;
}
dc->realize = e500_pcihost_realize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->props = pcihost_properties;
+ device_class_set_props(dc, pcihost_properties);
dc->vmsd = &vmstate_ppce500_pci;
}
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->realize = raven_pcihost_realizefn;
- dc->props = raven_pcihost_properties;
+ device_class_set_props(dc, raven_pcihost_properties);
dc->fw_name = "pci";
}
hc->root_bus_path = q35_host_root_bus_path;
dc->realize = q35_host_realize;
- dc->props = q35_host_props;
+ device_class_set_props(dc, q35_host_props);
/* Reason: needs to be wired up by pc_q35_init */
dc->user_creatable = false;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
k->realize = mch_realize;
k->config_write = mch_write_config;
dc->reset = mch_reset;
- dc->props = mch_props;
+ device_class_set_props(dc, mch_props);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "Host bridge";
dc->vmsd = &vmstate_mch;
dc->realize = sabre_realize;
dc->reset = sabre_reset;
- dc->props = sabre_properties;
+ device_class_set_props(dc, sabre_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "pci";
sbc->explicit_ofw_unit_address = sabre_ofw_unit_address;
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
dc->realize = pci_unin_main_realize;
- dc->props = pci_unin_main_pci_host_props;
+ device_class_set_props(dc, pci_unin_main_pci_host_props);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "pci";
sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address;
dc->realize = pci_vpb_realize;
dc->reset = pci_vpb_reset;
dc->vmsd = &pci_vpb_vmstate;
- dc->props = pci_vpb_properties;
+ device_class_set_props(dc, pci_vpb_properties);
}
static const TypeInfo pci_vpb_info = {
dc->realize = xilinx_pcie_host_realize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "pci";
- dc->props = xilinx_pcie_host_props;
+ device_class_set_props(dc, xilinx_pcie_host_props);
}
static const TypeInfo xilinx_pcie_host_info = {
k->realize = pci_qdev_realize;
k->unrealize = pci_qdev_unrealize;
k->bus_type = TYPE_PCI_BUS;
- k->props = pci_props;
+ device_class_set_props(k, pci_props);
}
static void pci_device_class_base_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->props = pcie_port_props;
+ device_class_set_props(dc, pcie_port_props);
}
static const TypeInfo pcie_port_type_info = {
DeviceClass *dc = DEVICE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
- dc->props = pcie_slot_props;
+ device_class_set_props(dc, pcie_slot_props);
hc->pre_plug = pcie_cap_slot_pre_plug_cb;
hc->plug = pcie_cap_slot_plug_cb;
hc->unplug = pcie_cap_slot_unplug_cb;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = pnv_chip_realize;
- dc->props = pnv_chip_properties;
+ device_class_set_props(dc, pnv_chip_properties);
dc->desc = "PowerNV Chip";
}
dc->realize = pnv_core_realize;
dc->unrealize = pnv_core_unrealize;
- dc->props = pnv_core_properties;
+ device_class_set_props(dc, pnv_core_properties);
}
#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = pnv_quad_realize;
- dc->props = pnv_quad_properties;
+ device_class_set_props(dc, pnv_quad_properties);
}
static const TypeInfo pnv_quad_info = {
dc->realize = pnv_homer_realize;
dc->desc = "PowerNV HOMER Memory";
- dc->props = pnv_homer_properties;
+ device_class_set_props(dc, pnv_homer_properties);
}
static const TypeInfo pnv_homer_type_info = {
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
- dc->props = pnv_lpc_properties;
+ device_class_set_props(dc, pnv_lpc_properties);
}
static const TypeInfo pnv_lpc_info = {
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
- dc->props = pnv_occ_properties;
+ device_class_set_props(dc, pnv_occ_properties);
}
static const TypeInfo pnv_occ_type_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pnv_pnor_realize;
- dc->props = pnv_pnor_properties;
+ device_class_set_props(dc, pnv_pnor_properties);
}
static const TypeInfo pnv_pnor_info = {
xdc->dt_xscom = pnv_psi_dt_xscom;
dc->desc = "PowerNV PSI Controller";
- dc->props = pnv_psi_properties;
+ device_class_set_props(dc, pnv_psi_properties);
dc->reset = pnv_psi_reset;
}
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->realize = ppc460ex_pcie_realize;
- dc->props = ppc460ex_pcie_props;
+ device_class_set_props(dc, ppc460ex_pcie_props);
dc->hotpluggable = false;
}
dc->realize = prep_systemio_realize;
dc->vmsd = &vmstate_prep_systemio;
- dc->props = prep_systemio_properties;
+ device_class_set_props(dc, prep_systemio_properties);
}
static TypeInfo prep_systemio800_info = {
dc->realize = rs6000mc_realize;
dc->vmsd = &vmstate_rs6000mc;
- dc->props = rs6000mc_properties;
+ device_class_set_props(dc, rs6000mc_properties);
}
static const TypeInfo rs6000mc_info = {
dc->realize = spapr_cpu_core_realize;
dc->unrealize = spapr_cpu_core_unrealize;
dc->reset = spapr_cpu_core_reset;
- dc->props = spapr_cpu_core_properties;
+ device_class_set_props(dc, spapr_cpu_core_properties);
scc->cpu_type = data;
}
hc->root_bus_path = spapr_phb_root_bus_path;
dc->realize = spapr_phb_realize;
dc->unrealize = spapr_phb_unrealize;
- dc->props = spapr_phb_properties;
+ device_class_set_props(dc, spapr_phb_properties);
dc->reset = spapr_phb_reset;
dc->vmsd = &vmstate_spapr_pci;
/* Supported by TYPE_SPAPR_MACHINE */
dc->realize = spapr_rng_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = spapr_rng_properties;
+ device_class_set_props(dc, spapr_rng_properties);
dc->hotpluggable = false;
}
dk->realize = spapr_tpm_proxy_realize;
dk->unrealize = spapr_tpm_proxy_unrealize;
dk->user_creatable = true;
- dk->props = spapr_tpm_proxy_properties;
+ device_class_set_props(dk, spapr_tpm_proxy_properties);
}
static const TypeInfo spapr_tpm_proxy_info = {
k->class_id = PCI_CLASS_NETWORK_OTHER;
dc->desc = "RDMA Device";
- dc->props = pvrdma_dev_properties;
+ device_class_set_props(dc, pvrdma_dev_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
ir->print_statistics = pvrdma_print_statistics;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = riscv_harts_props;
+ device_class_set_props(dc, riscv_harts_props);
dc->realize = riscv_harts_realize;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sifive_clint_realize;
- dc->props = sifive_clint_properties;
+ device_class_set_props(dc, sifive_clint_properties);
}
static const TypeInfo sifive_clint_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = sifive_plic_properties;
+ device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = sifive_u_otp_properties;
+ device_class_set_props(dc, sifive_u_otp_properties);
dc->realize = sifive_u_otp_realize;
dc->reset = sifive_u_otp_reset;
}
dc->realize = m48t59_isa_realize;
dc->reset = m48t59_reset_isa;
- dc->props = m48t59_isa_properties;
+ device_class_set_props(dc, m48t59_isa_properties);
nc->read = m48txx_isa_read;
nc->write = m48txx_isa_write;
nc->toggle_lock = m48txx_isa_toggle_lock;
dc->realize = m48t59_realize;
dc->reset = m48t59_reset_sysbus;
- dc->props = m48t59_sysbus_properties;
+ device_class_set_props(dc, m48t59_sysbus_properties);
dc->vmsd = &vmstate_m48t59;
nc->read = m48txx_sysbus_read;
nc->write = m48txx_sysbus_write;
dc->realize = rtc_realizefn;
dc->reset = rtc_resetdev;
dc->vmsd = &vmstate_rtc;
- dc->props = mc146818rtc_properties;
+ device_class_set_props(dc, mc146818rtc_properties);
}
static const TypeInfo mc146818rtc_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_pl031;
- dc->props = pl031_properties;
+ device_class_set_props(dc, pl031_properties);
}
static const TypeInfo pl031_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = emulated_ccw_3270_properties;
+ device_class_set_props(dc, emulated_ccw_3270_properties);
dc->bus_type = TYPE_VIRTUAL_CSS_BUS;
dc->realize = emulated_ccw_3270_realize;
dc->hotpluggable = false;
k->realize = ccw_device_realize;
k->refill_ids = ccw_device_refill_ids;
- dc->props = ccw_device_properties;
+ device_class_set_props(dc, ccw_device_properties);
dc->reset = ccw_device_reset;
}
hc->unplug = ccw_device_unplug;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->props = virtual_css_bridge_properties;
+ device_class_set_props(dc, virtual_css_bridge_properties);
object_class_property_add_bool(klass, "cssid-unrestricted",
prop_get_true, NULL, NULL);
object_class_property_set_description(klass, "cssid-unrestricted",
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = s390_ipl_realize;
- dc->props = s390_ipl_properties;
+ device_class_set_props(dc, s390_ipl_properties);
dc->reset = s390_ipl_reset;
dc->vmsd = &vmstate_ipl;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->reset = s390_pci_device_reset;
dc->bus_type = TYPE_S390_PCI_BUS;
dc->realize = s390_pci_device_realize;
- dc->props = s390_pci_device_properties;
+ device_class_set_props(dc, s390_pci_device_properties);
dc->vmsd = &s390_pci_device_vmstate;
}
k->realize = vhost_vsock_ccw_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = vhost_vsock_ccw_properties;
+ device_class_set_props(dc, vhost_vsock_ccw_properties);
}
static void vhost_vsock_ccw_instance_init(Object *obj)
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_9p_realize;
- dc->props = virtio_ccw_9p_properties;
+ device_class_set_props(dc, virtio_ccw_9p_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_balloon_realize;
- dc->props = virtio_ccw_balloon_properties;
+ device_class_set_props(dc, virtio_ccw_balloon_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_blk_realize;
- dc->props = virtio_ccw_blk_properties;
+ device_class_set_props(dc, virtio_ccw_blk_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_crypto_realize;
- dc->props = virtio_ccw_crypto_properties;
+ device_class_set_props(dc, virtio_ccw_crypto_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_gpu_realize;
- dc->props = virtio_ccw_gpu_properties;
+ device_class_set_props(dc, virtio_ccw_gpu_properties);
dc->hotpluggable = false;
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_input_realize;
- dc->props = virtio_ccw_input_properties;
+ device_class_set_props(dc, virtio_ccw_input_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_net_realize;
- dc->props = virtio_ccw_net_properties;
+ device_class_set_props(dc, virtio_ccw_net_properties);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_rng_realize;
- dc->props = virtio_ccw_rng_properties;
+ device_class_set_props(dc, virtio_ccw_rng_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_scsi_realize;
- dc->props = virtio_ccw_scsi_properties;
+ device_class_set_props(dc, virtio_ccw_scsi_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = vhost_ccw_scsi_realize;
- dc->props = vhost_ccw_scsi_properties;
+ device_class_set_props(dc, vhost_ccw_scsi_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
VirtIOCCWDeviceClass *k = VIRTIO_CCW_DEVICE_CLASS(klass);
k->realize = virtio_ccw_serial_realize;
- dc->props = virtio_ccw_serial_properties;
+ device_class_set_props(dc, virtio_ccw_serial_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
e->osts = info->osts;
e->product_name = info->product_name;
e->product_version = info->product_version;
- dc->props = info->props;
+ device_class_set_props(dc, info->props);
dc->reset = megasas_scsi_reset;
dc->vmsd = info->vmsd;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
pc->subsystem_id = 0x8000;
pc->class_id = PCI_CLASS_STORAGE_SCSI;
- dc->props = mptsas_properties;
+ device_class_set_props(dc, mptsas_properties);
dc->reset = mptsas_reset;
dc->vmsd = &vmstate_mptsas;
dc->desc = "LSI SAS 1068";
k->bus_type = TYPE_SCSI_BUS;
k->realize = scsi_qdev_realize;
k->unrealize = scsi_qdev_unrealize;
- k->props = scsi_props;
+ device_class_set_props(k, scsi_props);
}
static void scsi_dev_instance_init(Object *obj)
sc->alloc_req = scsi_new_request;
sc->unit_attention_reported = scsi_disk_unit_attention_reported;
dc->desc = "virtual SCSI disk";
- dc->props = scsi_hd_properties;
+ device_class_set_props(dc, scsi_hd_properties);
dc->vmsd = &vmstate_scsi_disk_state;
}
sc->alloc_req = scsi_new_request;
sc->unit_attention_reported = scsi_disk_unit_attention_reported;
dc->desc = "virtual SCSI CD-ROM";
- dc->props = scsi_cd_properties;
+ device_class_set_props(dc, scsi_cd_properties);
dc->vmsd = &vmstate_scsi_disk_state;
}
sdc->update_sense = scsi_block_update_sense;
sdc->need_fua_emulation = scsi_block_no_fua;
dc->desc = "SCSI block device passthrough";
- dc->props = scsi_block_properties;
+ device_class_set_props(dc, scsi_block_properties);
dc->vmsd = &vmstate_scsi_disk_state;
}
dc->fw_name = "disk";
dc->desc = "virtual SCSI disk or CD-ROM (legacy)";
dc->reset = scsi_disk_reset;
- dc->props = scsi_disk_properties;
+ device_class_set_props(dc, scsi_disk_properties);
dc->vmsd = &vmstate_scsi_disk_state;
}
dc->fw_name = "disk";
dc->desc = "pass through generic scsi device (/dev/sg*)";
dc->reset = scsi_generic_reset;
- dc->props = scsi_generic_properties;
+ device_class_set_props(dc, scsi_generic_properties);
dc->vmsd = &vmstate_scsi_device;
}
k->dt_compatible = "IBM,v-scsi";
k->signal_mask = 0x00000001;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = spapr_vscsi_properties;
+ device_class_set_props(dc, spapr_vscsi_properties);
k->rtce_window_size = 0x10000000;
dc->vmsd = &vmstate_spapr_vscsi;
}
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(klass);
- dc->props = vhost_scsi_properties;
+ device_class_set_props(dc, vhost_scsi_properties);
dc->vmsd = &vmstate_virtio_vhost_scsi;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = vhost_scsi_realize;
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(klass);
- dc->props = vhost_user_scsi_properties;
+ device_class_set_props(dc, vhost_user_scsi_properties);
dc->vmsd = &vmstate_vhost_scsi;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = vhost_user_scsi_realize;
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
- dc->props = virtio_scsi_properties;
+ device_class_set_props(dc, virtio_scsi_properties);
dc->vmsd = &vmstate_virtio_scsi;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = virtio_scsi_device_realize;
&pvs_k->parent_dc_realize);
dc->reset = pvscsi_reset;
dc->vmsd = &vmstate_pvscsi;
- dc->props = pvscsi_properties;
+ device_class_set_props(dc, pvscsi_properties);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
hc->unplug = pvscsi_hot_unplug;
hc->plug = pvscsi_hotplug;
SDCardClass *sc = SD_CARD_CLASS(klass);
dc->realize = sd_realize;
- dc->props = sd_properties;
+ device_class_set_props(dc, sd_properties);
dc->vmsd = &sd_vmstate;
dc->reset = sd_reset;
dc->bus_type = TYPE_SD_BUS;
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;
k->class_id = PCI_CLASS_SYSTEM_SDHCI;
- dc->props = sdhci_pci_properties;
+ device_class_set_props(dc, sdhci_pci_properties);
sdhci_common_class_init(klass, data);
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = sdhci_sysbus_properties;
+ device_class_set_props(dc, sdhci_sysbus_properties);
dc->realize = sdhci_sysbus_realize;
dc->unrealize = sdhci_sysbus_unrealize;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = prom_properties;
+ device_class_set_props(dc, prom_properties);
dc->realize = prom_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ram_realize;
- dc->props = ram_properties;
+ device_class_set_props(dc, ram_properties);
}
static const TypeInfo ram_info = {
dc->reset = iommu_reset;
dc->vmsd = &vmstate_iommu;
- dc->props = iommu_properties;
+ device_class_set_props(dc, iommu_properties);
}
static const TypeInfo iommu_info = {
k->device_id = PCI_DEVICE_ID_SUN_EBUS;
k->revision = 0x01;
k->class_id = PCI_CLASS_BRIDGE_OTHER;
- dc->props = ebus_properties;
+ device_class_set_props(dc, ebus_properties);
}
static const TypeInfo ebus_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = prom_properties;
+ device_class_set_props(dc, prom_properties);
dc->realize = prom_realize;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ram_realize;
- dc->props = ram_properties;
+ device_class_set_props(dc, ram_properties);
}
static const TypeInfo ram_info = {
dc->realize = aspeed_smc_realize;
dc->reset = aspeed_smc_reset;
- dc->props = aspeed_smc_properties;
+ device_class_set_props(dc, aspeed_smc_properties);
dc->vmsd = &vmstate_aspeed_smc;
mc->ctrl = data;
}
dc->realize = xilinx_spi_realize;
dc->reset = xlx_spi_reset;
- dc->props = xilinx_spi_properties;
+ device_class_set_props(dc, xilinx_spi_properties);
dc->vmsd = &vmstate_xilinx_spi;
}
dc->realize = xilinx_spips_realize;
dc->reset = xilinx_spips_reset;
- dc->props = xilinx_spips_properties;
+ device_class_set_props(dc, xilinx_spips_properties);
dc->vmsd = &vmstate_xilinx_spips;
xsc->reg_ops = &spips_ops;
dc->realize = xlnx_zynqmp_qspips_realize;
dc->reset = xlnx_zynqmp_qspips_reset;
dc->vmsd = &vmstate_xlnx_zynqmp_qspips;
- dc->props = xilinx_zynqmp_qspips_properties;
+ device_class_set_props(dc, xilinx_zynqmp_qspips_properties);
xsc->reg_ops = &xlnx_zynqmp_qspips_ops;
xsc->rx_fifo_size = RXFF_A_Q;
xsc->tx_fifo_size = TXFF_A_Q;
dc->realize = a9_gtimer_realize;
dc->vmsd = &vmstate_a9_gtimer;
dc->reset = a9_gtimer_reset;
- dc->props = a9_gtimer_properties;
+ device_class_set_props(dc, a9_gtimer_properties);
}
static const TypeInfo a9_gtimer_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = a10_pit_reset;
- dc->props = a10_pit_properties;
+ device_class_set_props(dc, a10_pit_properties);
dc->desc = "allwinner a10 timer";
dc->vmsd = &vmstate_a10_pit;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = altera_timer_realize;
- dc->props = altera_timer_properties;
+ device_class_set_props(dc, altera_timer_properties);
dc->reset = altera_timer_reset;
}
dc->realize = arm_mptimer_realize;
dc->vmsd = &vmstate_arm_mptimer;
dc->reset = arm_mptimer_reset;
- dc->props = arm_mptimer_properties;
+ device_class_set_props(dc, arm_mptimer_properties);
}
static const TypeInfo arm_mptimer_info = {
DeviceClass *k = DEVICE_CLASS(klass);
k->realize = sp804_realize;
- k->props = sp804_properties;
+ device_class_set_props(k, sp804_properties);
k->vmsd = &vmstate_sp804;
}
dc->reset = aspeed_timer_reset;
dc->desc = "ASPEED Timer";
dc->vmsd = &vmstate_aspeed_timer_state;
- dc->props = aspeed_timer_properties;
+ device_class_set_props(dc, aspeed_timer_properties);
}
static const TypeInfo aspeed_timer_info = {
dc->realize = cmsdk_apb_dualtimer_realize;
dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
dc->reset = cmsdk_apb_dualtimer_reset;
- dc->props = cmsdk_apb_dualtimer_properties;
+ device_class_set_props(dc, cmsdk_apb_dualtimer_properties);
}
static const TypeInfo cmsdk_apb_dualtimer_info = {
dc->realize = cmsdk_apb_timer_realize;
dc->vmsd = &cmsdk_apb_timer_vmstate;
dc->reset = cmsdk_apb_timer_reset;
- dc->props = cmsdk_apb_timer_properties;
+ device_class_set_props(dc, cmsdk_apb_timer_properties);
}
static const TypeInfo cmsdk_apb_timer_info = {
dc->realize = grlib_gptimer_realize;
dc->reset = grlib_gptimer_reset;
- dc->props = grlib_gptimer_properties;
+ device_class_set_props(dc, grlib_gptimer_properties);
}
static const TypeInfo grlib_gptimer_info = {
dc->realize = hpet_realize;
dc->reset = hpet_reset;
dc->vmsd = &vmstate_hpet;
- dc->props = hpet_device_properties;
+ device_class_set_props(dc, hpet_device_properties);
}
static const TypeInfo hpet_device_info = {
k->get_channel_info = pit_get_channel_info_common;
k->post_load = pit_post_load;
dc->reset = pit_reset;
- dc->props = pit_properties;
+ device_class_set_props(dc, pit_properties);
}
static const TypeInfo pit_info = {
dc->realize = lm32_timer_realize;
dc->reset = timer_reset;
dc->vmsd = &vmstate_lm32_timer;
- dc->props = lm32_timer_properties;
+ device_class_set_props(dc, lm32_timer_properties);
}
static const TypeInfo lm32_timer_info = {
dc->realize = milkymist_sysctl_realize;
dc->reset = milkymist_sysctl_reset;
dc->vmsd = &vmstate_milkymist_sysctl;
- dc->props = milkymist_sysctl_properties;
+ device_class_set_props(dc, milkymist_sysctl_properties);
}
static const TypeInfo milkymist_sysctl_info = {
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = mss_timer_properties;
+ device_class_set_props(dc, mss_timer_properties);
dc->vmsd = &vmstate_mss_timer;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "PXA25x timer";
- dc->props = pxa25x_timer_dev_properties;
+ device_class_set_props(dc, pxa25x_timer_dev_properties);
}
static const TypeInfo pxa25x_timer_dev_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "PXA27x timer";
- dc->props = pxa27x_timer_dev_properties;
+ device_class_set_props(dc, pxa27x_timer_dev_properties);
}
static const TypeInfo pxa27x_timer_dev_info = {
dc->reset = slavio_timer_reset;
dc->vmsd = &vmstate_slavio_timer;
- dc->props = slavio_timer_properties;
+ device_class_set_props(dc, slavio_timer_properties);
}
static const TypeInfo slavio_timer_info = {
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = stm32f2xx_timer_reset;
- dc->props = stm32f2xx_timer_properties;
+ device_class_set_props(dc, stm32f2xx_timer_properties);
dc->vmsd = &vmstate_stm32f2xx_timer;
}
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xilinx_timer_realize;
- dc->props = xilinx_timer_properties;
+ device_class_set_props(dc, xilinx_timer_properties);
}
static const TypeInfo xilinx_timer_info = {
TPMIfClass *tc = TPM_IF_CLASS(klass);
dc->realize = tpm_crb_realize;
- dc->props = tpm_crb_properties;
+ device_class_set_props(dc, tpm_crb_properties);
dc->vmsd = &vmstate_tpm_crb;
dc->user_creatable = true;
tc->model = TPM_MODEL_TPM_CRB;
TPMIfClass *tc = TPM_IF_CLASS(klass);
dc->realize = tpm_tis_realizefn;
- dc->props = tpm_tis_properties;
+ device_class_set_props(dc, tpm_tis_properties);
dc->reset = tpm_tis_reset;
dc->vmsd = &vmstate_tpm_tis;
tc->model = TPM_MODEL_TPM_TIS;
k->bus_type = TYPE_USB_BUS;
k->realize = usb_qdev_realize;
k->unrealize = usb_qdev_unrealize;
- k->props = usb_props;
+ device_class_set_props(k, usb_props);
}
static const TypeInfo usb_device_type_info = {
cc->apdu_from_guest = emulated_apdu_from_guest;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->desc = "emulated smartcard";
- dc->props = emulated_card_properties;
+ device_class_set_props(dc, emulated_card_properties);
}
static const TypeInfo emulated_card_info = {
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->desc = "passthrough smartcard";
dc->vmsd = &passthru_vmstate;
- dc->props = passthru_card_properties;
+ device_class_set_props(dc, passthru_card_properties);
}
static const TypeInfo passthru_card_info = {
USBDeviceClass *k = USB_DEVICE_CLASS(klass);
dc->vmsd = &vmstate_usb_audio;
- dc->props = usb_audio_properties;
+ device_class_set_props(dc, usb_audio_properties);
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
k->product_desc = "QEMU USB Audio Interface";
k->realize = usb_audio_realize;
uc->realize = usb_tablet_realize;
uc->product_desc = "QEMU USB Tablet";
dc->vmsd = &vmstate_usb_ptr;
- dc->props = usb_tablet_properties;
+ device_class_set_props(dc, usb_tablet_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
uc->realize = usb_mouse_realize;
uc->product_desc = "QEMU USB Mouse";
dc->vmsd = &vmstate_usb_ptr;
- dc->props = usb_mouse_properties;
+ device_class_set_props(dc, usb_mouse_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
uc->realize = usb_keyboard_realize;
uc->product_desc = "QEMU USB Keyboard";
dc->vmsd = &vmstate_usb_kbd;
- dc->props = usb_keyboard_properties;
+ device_class_set_props(dc, usb_keyboard_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "hub";
dc->vmsd = &vmstate_usb_hub;
- dc->props = usb_hub_properties;
+ device_class_set_props(dc, usb_hub_properties);
}
static const TypeInfo hub_info = {
dc->desc = "USB Media Transfer Protocol device";
dc->fw_name = "mtp";
dc->vmsd = &vmstate_usb_mtp;
- dc->props = mtp_properties;
+ device_class_set_props(dc, mtp_properties);
}
static TypeInfo mtp_info = {
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->fw_name = "network";
dc->vmsd = &vmstate_usb_net;
- dc->props = net_properties;
+ device_class_set_props(dc, net_properties);
}
static const TypeInfo net_info = {
uc->product_desc = "QEMU USB Serial";
uc->usb_desc = &desc_serial;
- dc->props = serial_properties;
+ device_class_set_props(dc, serial_properties);
}
static const TypeInfo serial_info = {
uc->product_desc = "QEMU USB Braille";
uc->usb_desc = &desc_braille;
- dc->props = braille_properties;
+ device_class_set_props(dc, braille_properties);
}
static const TypeInfo braille_info = {
uc->unrealize = ccid_unrealize;
dc->desc = "CCID Rev 1.1 smartcard reader";
dc->vmsd = &ccid_vmstate;
- dc->props = ccid_properties;
+ device_class_set_props(dc, ccid_properties);
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
hc->unplug = qdev_simple_device_unplug_cb;
}
k->bus_type = TYPE_CCID_BUS;
k->realize = ccid_card_realize;
k->unrealize = ccid_card_unrealize;
- k->props = ccid_props;
+ device_class_set_props(k, ccid_props);
}
static const TypeInfo ccid_card_type_info = {
USBDeviceClass *uc = USB_DEVICE_CLASS(klass);
uc->realize = usb_msd_storage_realize;
- dc->props = msd_properties;
+ device_class_set_props(dc, msd_properties);
}
static void usb_msd_get_bootindex(Object *obj, Visitor *v, const char *name,
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
dc->fw_name = "storage";
dc->vmsd = &vmstate_usb_uas;
- dc->props = uas_properties;
+ device_class_set_props(dc, uas_properties);
}
static const TypeInfo uas_info = {
k->class_id = PCI_CLASS_SERIAL_USB;
k->config_write = usb_ehci_pci_write_config;
dc->vmsd = &vmstate_ehci_pci;
- dc->props = ehci_pci_properties;
+ device_class_set_props(dc, ehci_pci_properties);
dc->reset = usb_ehci_pci_reset;
}
dc->realize = usb_ehci_sysbus_realize;
dc->vmsd = &vmstate_ehci_sysbus;
- dc->props = ehci_sysbus_properties;
+ device_class_set_props(dc, ehci_sysbus_properties);
dc->reset = usb_ehci_sysbus_reset;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
}
k->class_id = PCI_CLASS_SERIAL_USB;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
dc->desc = "Apple USB Controller";
- dc->props = ohci_pci_properties;
+ device_class_set_props(dc, ohci_pci_properties);
dc->hotpluggable = false;
dc->vmsd = &vmstate_ohci;
dc->reset = usb_ohci_reset_pci;
dc->realize = ohci_realize_pxa;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
dc->desc = "OHCI USB Controller";
- dc->props = ohci_sysbus_properties;
+ device_class_set_props(dc, ohci_sysbus_properties);
dc->reset = usb_ohci_reset_sysbus;
}
if (!info->unplug) {
/* uhci controllers in companion setups can't be hotplugged */
dc->hotpluggable = false;
- dc->props = uhci_properties_companion;
+ device_class_set_props(dc, uhci_properties_companion);
} else {
- dc->props = uhci_properties_standalone;
+ device_class_set_props(dc, uhci_properties_standalone);
}
u->info = *info;
}
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = nec_xhci_properties;
+ device_class_set_props(dc, nec_xhci_properties);
k->vendor_id = PCI_VENDOR_ID_NEC;
k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
k->revision = 0x03;
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_xhci;
- dc->props = xhci_properties;
+ device_class_set_props(dc, xhci_properties);
dc->reset = xhci_reset;
set_bit(DEVICE_CATEGORY_USB, dc->categories);
k->realize = usb_xhci_realize;
uc->alloc_streams = usb_host_alloc_streams;
uc->free_streams = usb_host_free_streams;
dc->vmsd = &vmstate_usb_host;
- dc->props = usb_host_dev_properties;
+ device_class_set_props(dc, usb_host_dev_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
uc->alloc_streams = usbredir_alloc_streams;
uc->free_streams = usbredir_free_streams;
dc->vmsd = &usbredir_vmstate;
- dc->props = usbredir_properties;
+ device_class_set_props(dc, usbredir_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = vfio_ap_properties;
+ device_class_set_props(dc, vfio_ap_properties);
dc->vmsd = &vfio_ap_vmstate;
dc->desc = "VFIO-based AP device assignment";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
DeviceClass *dc = DEVICE_CLASS(klass);
S390CCWDeviceClass *cdc = S390_CCW_DEVICE_CLASS(klass);
- dc->props = vfio_ccw_properties;
+ device_class_set_props(dc, vfio_ccw_properties);
dc->vmsd = &vfio_ccw_vmstate;
dc->desc = "VFIO-based subchannel assignment";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass);
dc->reset = vfio_pci_reset;
- dc->props = vfio_pci_dev_properties;
+ device_class_set_props(dc, vfio_pci_dev_properties);
dc->desc = "VFIO-based PCI device assignment";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
pdc->realize = vfio_realize;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = vfio_pci_dev_nohotplug_properties;
+ device_class_set_props(dc, vfio_pci_dev_nohotplug_properties);
dc->hotpluggable = false;
}
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
dc->realize = vfio_platform_realize;
- dc->props = vfio_platform_dev_properties;
+ device_class_set_props(dc, vfio_platform_dev_properties);
dc->vmsd = &vfio_platform_vmstate;
dc->desc = "VFIO-based platform device assignment";
sbc->connect_irq_notifier = vfio_start_irqfd_injection;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = vhost_scsi_pci_realize;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = vhost_scsi_pci_properties;
+ device_class_set_props(dc, vhost_scsi_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
pcidev_k->revision = 0x00;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = vhost_user_blk_pci_properties;
+ device_class_set_props(dc, vhost_user_blk_pci_properties);
k->realize = vhost_user_blk_pci_realize;
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = vhost_user_fs_pci_realize;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = vhost_user_fs_pci_properties;
+ device_class_set_props(dc, vhost_user_fs_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = 0; /* Set by virtio-pci based on virtio id */
pcidev_k->revision = 0x00;
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = vuf_properties;
+ device_class_set_props(dc, vuf_properties);
dc->vmsd = &vuf_vmstate;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
vdc->realize = vuf_device_realize;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = vhost_user_scsi_pci_realize;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = vhost_user_scsi_pci_properties;
+ device_class_set_props(dc, vhost_user_scsi_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
pcidev_k->revision = 0x00;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = vhost_vsock_pci_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = vhost_vsock_pci_properties;
+ device_class_set_props(dc, vhost_vsock_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_VSOCK;
pcidev_k->revision = 0x00;
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = vhost_vsock_properties;
+ device_class_set_props(dc, vhost_vsock_properties);
dc->vmsd = &vmstate_virtio_vhost_vsock;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->realize = vhost_vsock_device_realize;
pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
pcidev_k->class_id = 0x2;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = virtio_9p_pci_properties;
+ device_class_set_props(dc, virtio_9p_pci_properties);
}
static void virtio_9p_pci_instance_init(Object *obj)
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = virtio_balloon_pci_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = virtio_balloon_pci_properties;
+ device_class_set_props(dc, virtio_balloon_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BALLOON;
pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_balloon_properties;
+ device_class_set_props(dc, virtio_balloon_properties);
dc->vmsd = &vmstate_virtio_balloon;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->realize = virtio_balloon_device_realize;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = virtio_blk_pci_properties;
+ device_class_set_props(dc, virtio_blk_pci_properties);
k->realize = virtio_blk_pci_realize;
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_BLOCK;
k->realize = virtio_crypto_pci_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = virtio_crypto_pci_properties;
+ device_class_set_props(dc, virtio_crypto_pci_properties);
pcidev_k->class_id = PCI_CLASS_OTHERS;
}
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_crypto_properties;
+ device_class_set_props(dc, virtio_crypto_properties);
dc->vmsd = &vmstate_virtio_crypto;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->realize = virtio_crypto_device_realize;
VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
- dc->props = virtio_input_pci_properties;
+ device_class_set_props(dc, virtio_input_pci_properties);
k->realize = virtio_input_pci_realize;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->realize = virtio_mmio_realizefn;
dc->reset = virtio_mmio_reset;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- dc->props = virtio_mmio_properties;
+ device_class_set_props(dc, virtio_mmio_properties);
}
static const TypeInfo virtio_mmio_info = {
k->revision = VIRTIO_PCI_ABI_VERSION;
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
- dc->props = virtio_net_properties;
+ device_class_set_props(dc, virtio_net_properties);
vpciklass->realize = virtio_net_pci_realize;
}
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass);
- dc->props = virtio_pci_properties;
+ device_class_set_props(dc, virtio_pci_properties);
k->realize = virtio_pci_realize;
k->exit = virtio_pci_exit;
k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = virtio_pci_generic_properties;
+ device_class_set_props(dc, virtio_pci_generic_properties);
}
static void virtio_pci_transitional_instance_init(Object *obj)
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
VirtIOPMEMClass *vpc = VIRTIO_PMEM_CLASS(klass);
- dc->props = virtio_pmem_properties;
+ device_class_set_props(dc, virtio_pmem_properties);
vdc->realize = virtio_pmem_realize;
vdc->unrealize = virtio_pmem_unrealize;
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
- dc->props = virtio_rng_properties;
+ device_class_set_props(dc, virtio_rng_properties);
dc->vmsd = &vmstate_virtio_rng;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->realize = virtio_rng_device_realize;
k->realize = virtio_scsi_pci_realize;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
- dc->props = virtio_scsi_pci_properties;
+ device_class_set_props(dc, virtio_scsi_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_SCSI;
pcidev_k->revision = 0x00;
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = virtio_serial_pci_realize;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
- dc->props = virtio_serial_pci_properties;
+ device_class_set_props(dc, virtio_serial_pci_properties);
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_CONSOLE;
pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
dc->realize = virtio_device_realize;
dc->unrealize = virtio_device_unrealize;
dc->bus_type = TYPE_VIRTIO_BUS;
- dc->props = virtio_properties;
+ device_class_set_props(dc, virtio_properties);
vdc->start_ioeventfd = virtio_device_start_ioeventfd_impl;
vdc->stop_ioeventfd = virtio_device_stop_ioeventfd_impl;
dc->realize = cmsdk_apb_watchdog_realize;
dc->vmsd = &cmsdk_apb_watchdog_vmstate;
dc->reset = cmsdk_apb_watchdog_reset;
- dc->props = cmsdk_apb_watchdog_properties;
+ device_class_set_props(dc, cmsdk_apb_watchdog_properties);
}
static const TypeInfo cmsdk_apb_watchdog_info = {
dc->reset = aspeed_wdt_reset;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->vmsd = &vmstate_aspeed_wdt;
- dc->props = aspeed_wdt_properties;
+ device_class_set_props(dc, aspeed_wdt_properties);
}
static const TypeInfo aspeed_wdt_info = {
dev_class->realize = xen_device_realize;
dev_class->unrealize = xen_device_unrealize;
- dev_class->props = xen_device_props;
+ device_class_set_props(dev_class, xen_device_props);
dev_class->bus_type = TYPE_XEN_BUS;
}
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = xendev_properties;
+ device_class_set_props(dc, xendev_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
/* xen-backend devices can be plugged/unplugged dynamically */
dc->user_creatable = true;
{
DeviceClass *dc = DEVICE_CLASS(klass);
- dc->props = xen_sysdev_properties;
+ device_class_set_props(dc, xen_sysdev_properties);
dc->bus_type = TYPE_XENSYSBUS;
}
k->config_write = xen_pt_pci_write_config;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->desc = "Assign an host PCI device with Xen";
- dc->props = xen_pci_passthrough_properties;
+ device_class_set_props(dc, xen_pci_passthrough_properties);
};
static void xen_pci_passthrough_finalize(Object *obj)
*/
void device_reset(DeviceState *dev);
+void device_class_set_props(DeviceClass *dc, Property *props);
+
void device_class_set_parent_reset(DeviceClass *dc,
DeviceReset dev_reset,
DeviceReset *parent_reset);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->user_creatable = false;
- dc->props = migration_properties;
+ device_class_set_props(dc, migration_properties);
}
static void migration_instance_finalize(Object *obj)
device_class_set_parent_realize(dc, arm_cpu_realizefn,
&acc->parent_realize);
- dc->props = arm_cpu_properties;
+ device_class_set_props(dc, arm_cpu_properties);
cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset);
cc->class_by_name = arm_cpu_class_by_name;
xcc->model_description =
"Enables all features supported by the accelerator in the current host";
- dc->props = max_x86_cpu_properties;
+ device_class_set_props(dc, max_x86_cpu_properties);
}
static void max_x86_cpu_initfn(Object *obj)
&xcc->parent_realize);
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
&xcc->parent_unrealize);
- dc->props = x86_cpu_properties;
+ device_class_set_props(dc, x86_cpu_properties);
cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset);
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_mb_cpu;
- dc->props = mb_properties;
+ device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 5;
cc->disas_set_info = mb_disas_set_info;
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
&ncc->parent_realize);
- dc->props = nios2_properties;
+ device_class_set_props(dc, nios2_properties);
cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset);
cc->class_by_name = nios2_cpu_class_by_name;
dc->fw_name = "PowerPC,POWER7";
dc->desc = "POWER7";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power7;
pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
dc->fw_name = "PowerPC,POWER8";
dc->desc = "POWER8";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power8;
pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
dc->fw_name = "PowerPC,POWER9";
dc->desc = "POWER9";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power9;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
dc->fw_name = "PowerPC,POWER10";
dc->desc = "POWER10";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power10;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
PCR_COMPAT_3_00;
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
- dc->props = ppc_cpu_properties;
+ device_class_set_props(dc, ppc_cpu_properties);
cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset);
#endif
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
- dc->props = riscv_cpu_properties;
+ device_class_set_props(dc, riscv_cpu_properties);
}
char *riscv_isa_string(RISCVCPU *cpu)
device_class_set_parent_realize(dc, s390_cpu_realizefn,
&scc->parent_realize);
- dc->props = s390x_cpu_properties;
+ device_class_set_props(dc, s390x_cpu_properties);
dc->user_creatable = true;
cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset);
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
&scc->parent_realize);
- dc->props = sparc_cpu_properties;
+ device_class_set_props(dc, sparc_cpu_properties);
cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset);
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = NULL;
- dc->props = static_props;
+ device_class_set_props(dc, static_props);
}
static const TypeInfo static_prop_type = {
projects / thirdparty / qemu.git / commitdiff
