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Commit | Line | Data |
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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
edf79e66 HC |
11 | */ |
12 | ||
83c9f4ca | 13 | #include "hw/hw.h" |
0d09e41a PB |
14 | #include "hw/i386/pc.h" |
15 | #include "hw/isa/vt82c686.h" | |
16 | #include "hw/i2c/i2c.h" | |
17 | #include "hw/i2c/smbus.h" | |
83c9f4ca | 18 | #include "hw/pci/pci.h" |
0d09e41a | 19 | #include "hw/isa/isa.h" |
83c9f4ca | 20 | #include "hw/sysbus.h" |
0d09e41a PB |
21 | #include "hw/mips/mips.h" |
22 | #include "hw/isa/apm.h" | |
23 | #include "hw/acpi/acpi.h" | |
24 | #include "hw/i2c/pm_smbus.h" | |
9c17d615 | 25 | #include "sysemu/sysemu.h" |
1de7afc9 | 26 | #include "qemu/timer.h" |
022c62cb | 27 | #include "exec/address-spaces.h" |
edf79e66 | 28 | |
edf79e66 HC |
29 | //#define DEBUG_VT82C686B |
30 | ||
31 | #ifdef DEBUG_VT82C686B | |
32 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
33 | #else | |
34 | #define DPRINTF(fmt, ...) | |
35 | #endif | |
36 | ||
37 | typedef struct SuperIOConfig | |
38 | { | |
39 | uint8_t config[0xff]; | |
40 | uint8_t index; | |
41 | uint8_t data; | |
42 | } SuperIOConfig; | |
43 | ||
44 | typedef struct VT82C686BState { | |
45 | PCIDevice dev; | |
bcc37e24 | 46 | MemoryRegion superio; |
edf79e66 HC |
47 | SuperIOConfig superio_conf; |
48 | } VT82C686BState; | |
49 | ||
bcc37e24 JK |
50 | static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, |
51 | unsigned size) | |
edf79e66 HC |
52 | { |
53 | int can_write; | |
54 | SuperIOConfig *superio_conf = opaque; | |
55 | ||
b2bedb21 | 56 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); |
edf79e66 HC |
57 | if (addr == 0x3f0) { |
58 | superio_conf->index = data & 0xff; | |
59 | } else { | |
60 | /* 0x3f1 */ | |
61 | switch (superio_conf->index) { | |
62 | case 0x00 ... 0xdf: | |
63 | case 0xe4: | |
64 | case 0xe5: | |
65 | case 0xe9 ... 0xed: | |
66 | case 0xf3: | |
67 | case 0xf5: | |
68 | case 0xf7: | |
69 | case 0xf9 ... 0xfb: | |
70 | case 0xfd ... 0xff: | |
71 | can_write = 0; | |
72 | break; | |
73 | default: | |
74 | can_write = 1; | |
75 | ||
76 | if (can_write) { | |
77 | switch (superio_conf->index) { | |
78 | case 0xe7: | |
79 | if ((data & 0xff) != 0xfe) { | |
b2bedb21 | 80 | DPRINTF("chage uart 1 base. unsupported yet\n"); |
edf79e66 HC |
81 | } |
82 | break; | |
83 | case 0xe8: | |
84 | if ((data & 0xff) != 0xbe) { | |
b2bedb21 | 85 | DPRINTF("chage uart 2 base. unsupported yet\n"); |
edf79e66 HC |
86 | } |
87 | break; | |
88 | ||
89 | default: | |
90 | superio_conf->config[superio_conf->index] = data & 0xff; | |
91 | } | |
92 | } | |
93 | } | |
94 | superio_conf->config[superio_conf->index] = data & 0xff; | |
95 | } | |
96 | } | |
97 | ||
bcc37e24 | 98 | static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) |
edf79e66 HC |
99 | { |
100 | SuperIOConfig *superio_conf = opaque; | |
101 | ||
b2bedb21 | 102 | DPRINTF("superio_ioport_readb address 0x%x\n", addr); |
edf79e66 HC |
103 | return (superio_conf->config[superio_conf->index]); |
104 | } | |
105 | ||
bcc37e24 JK |
106 | static const MemoryRegionOps superio_ops = { |
107 | .read = superio_ioport_readb, | |
108 | .write = superio_ioport_writeb, | |
109 | .endianness = DEVICE_NATIVE_ENDIAN, | |
110 | .impl = { | |
111 | .min_access_size = 1, | |
112 | .max_access_size = 1, | |
113 | }, | |
114 | }; | |
115 | ||
edf79e66 HC |
116 | static void vt82c686b_reset(void * opaque) |
117 | { | |
118 | PCIDevice *d = opaque; | |
119 | uint8_t *pci_conf = d->config; | |
120 | VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); | |
121 | ||
122 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
123 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
124 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
125 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
126 | ||
127 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
128 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
129 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
130 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
131 | pci_conf[0x59] = 0x04; | |
132 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
133 | pci_conf[0x5f] = 0x04; | |
134 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
135 | ||
136 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
137 | vt82c->superio_conf.config[0xe2] = 0x03; | |
138 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
139 | vt82c->superio_conf.config[0xe6] = 0xde; | |
140 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
141 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
142 | } | |
143 | ||
144 | /* write config pci function0 registers. PCI-ISA bridge */ | |
145 | static void vt82c686b_write_config(PCIDevice * d, uint32_t address, | |
146 | uint32_t val, int len) | |
147 | { | |
148 | VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); | |
149 | ||
b2bedb21 | 150 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
151 | address, val, len); |
152 | ||
153 | pci_default_write_config(d, address, val, len); | |
154 | if (address == 0x85) { /* enable or disable super IO configure */ | |
bcc37e24 | 155 | memory_region_set_enabled(&vt686->superio, val & 0x2); |
edf79e66 HC |
156 | } |
157 | } | |
158 | ||
159 | #define ACPI_DBG_IO_ADDR 0xb044 | |
160 | ||
161 | typedef struct VT686PMState { | |
162 | PCIDevice dev; | |
a2902821 | 163 | MemoryRegion io; |
355bf2e5 | 164 | ACPIREGS ar; |
edf79e66 | 165 | APMState apm; |
edf79e66 HC |
166 | PMSMBus smb; |
167 | uint32_t smb_io_base; | |
168 | } VT686PMState; | |
169 | ||
170 | typedef struct VT686AC97State { | |
171 | PCIDevice dev; | |
172 | } VT686AC97State; | |
173 | ||
174 | typedef struct VT686MC97State { | |
175 | PCIDevice dev; | |
176 | } VT686MC97State; | |
177 | ||
edf79e66 HC |
178 | static void pm_update_sci(VT686PMState *s) |
179 | { | |
180 | int sci_level, pmsts; | |
edf79e66 | 181 | |
2886be1b | 182 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
355bf2e5 | 183 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
04dc308f IY |
184 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
185 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
186 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
187 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
9e64f8a3 | 188 | pci_set_irq(&s->dev, sci_level); |
edf79e66 | 189 | /* schedule a timer interruption if needed */ |
355bf2e5 | 190 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 191 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
192 | } |
193 | ||
355bf2e5 | 194 | static void pm_tmr_timer(ACPIREGS *ar) |
edf79e66 | 195 | { |
355bf2e5 | 196 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
edf79e66 HC |
197 | pm_update_sci(s); |
198 | } | |
199 | ||
edf79e66 HC |
200 | static void pm_io_space_update(VT686PMState *s) |
201 | { | |
202 | uint32_t pm_io_base; | |
203 | ||
a2902821 GH |
204 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
205 | pm_io_base &= 0xffc0; | |
edf79e66 | 206 | |
a2902821 GH |
207 | memory_region_transaction_begin(); |
208 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); | |
209 | memory_region_set_address(&s->io, pm_io_base); | |
210 | memory_region_transaction_commit(); | |
edf79e66 HC |
211 | } |
212 | ||
213 | static void pm_write_config(PCIDevice *d, | |
214 | uint32_t address, uint32_t val, int len) | |
215 | { | |
b2bedb21 | 216 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", |
edf79e66 HC |
217 | address, val, len); |
218 | pci_default_write_config(d, address, val, len); | |
219 | } | |
220 | ||
221 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
222 | { | |
223 | VT686PMState *s = opaque; | |
224 | ||
225 | pm_io_space_update(s); | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static const VMStateDescription vmstate_acpi = { | |
230 | .name = "vt82c686b_pm", | |
231 | .version_id = 1, | |
232 | .minimum_version_id = 1, | |
233 | .minimum_version_id_old = 1, | |
234 | .post_load = vmstate_acpi_post_load, | |
235 | .fields = (VMStateField []) { | |
236 | VMSTATE_PCI_DEVICE(dev, VT686PMState), | |
355bf2e5 GH |
237 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
238 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), | |
239 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), | |
edf79e66 | 240 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
355bf2e5 GH |
241 | VMSTATE_TIMER(ar.tmr.timer, VT686PMState), |
242 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), | |
edf79e66 HC |
243 | VMSTATE_END_OF_LIST() |
244 | } | |
245 | }; | |
246 | ||
247 | /* | |
248 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() | |
249 | * just register a PCI device now, functionalities will be implemented later. | |
250 | */ | |
251 | ||
252 | static int vt82c686b_ac97_initfn(PCIDevice *dev) | |
253 | { | |
254 | VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); | |
255 | uint8_t *pci_conf = s->dev.config; | |
256 | ||
edf79e66 HC |
257 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
258 | PCI_COMMAND_PARITY); | |
259 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
260 | PCI_STATUS_DEVSEL_MEDIUM); | |
261 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) | |
267 | { | |
268 | PCIDevice *dev; | |
269 | ||
270 | dev = pci_create(bus, devfn, "VT82C686B_AC97"); | |
271 | qdev_init_nofail(&dev->qdev); | |
272 | } | |
273 | ||
40021f08 AL |
274 | static void via_ac97_class_init(ObjectClass *klass, void *data) |
275 | { | |
39bffca2 | 276 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
277 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
278 | ||
279 | k->init = vt82c686b_ac97_initfn; | |
280 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
281 | k->device_id = PCI_DEVICE_ID_VIA_AC97; | |
282 | k->revision = 0x50; | |
283 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; | |
125ee0ed | 284 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); |
39bffca2 | 285 | dc->desc = "AC97"; |
40021f08 AL |
286 | } |
287 | ||
8c43a6f0 | 288 | static const TypeInfo via_ac97_info = { |
39bffca2 AL |
289 | .name = "VT82C686B_AC97", |
290 | .parent = TYPE_PCI_DEVICE, | |
291 | .instance_size = sizeof(VT686AC97State), | |
292 | .class_init = via_ac97_class_init, | |
edf79e66 HC |
293 | }; |
294 | ||
edf79e66 HC |
295 | static int vt82c686b_mc97_initfn(PCIDevice *dev) |
296 | { | |
297 | VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); | |
298 | uint8_t *pci_conf = s->dev.config; | |
299 | ||
edf79e66 HC |
300 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
301 | PCI_COMMAND_VGA_PALETTE); | |
302 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
303 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) | |
309 | { | |
310 | PCIDevice *dev; | |
311 | ||
312 | dev = pci_create(bus, devfn, "VT82C686B_MC97"); | |
313 | qdev_init_nofail(&dev->qdev); | |
314 | } | |
315 | ||
40021f08 AL |
316 | static void via_mc97_class_init(ObjectClass *klass, void *data) |
317 | { | |
39bffca2 | 318 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
319 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
320 | ||
321 | k->init = vt82c686b_mc97_initfn; | |
322 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
323 | k->device_id = PCI_DEVICE_ID_VIA_MC97; | |
324 | k->class_id = PCI_CLASS_COMMUNICATION_OTHER; | |
325 | k->revision = 0x30; | |
125ee0ed | 326 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 | 327 | dc->desc = "MC97"; |
40021f08 AL |
328 | } |
329 | ||
8c43a6f0 | 330 | static const TypeInfo via_mc97_info = { |
39bffca2 AL |
331 | .name = "VT82C686B_MC97", |
332 | .parent = TYPE_PCI_DEVICE, | |
333 | .instance_size = sizeof(VT686MC97State), | |
334 | .class_init = via_mc97_class_init, | |
edf79e66 HC |
335 | }; |
336 | ||
edf79e66 HC |
337 | /* vt82c686 pm init */ |
338 | static int vt82c686b_pm_initfn(PCIDevice *dev) | |
339 | { | |
340 | VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); | |
341 | uint8_t *pci_conf; | |
342 | ||
343 | pci_conf = s->dev.config; | |
edf79e66 HC |
344 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
345 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
346 | PCI_STATUS_DEVSEL_MEDIUM); | |
347 | ||
348 | /* 0x48-0x4B is Power Management I/O Base */ | |
349 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
350 | ||
351 | /* SMB ports:0xeee0~0xeeef */ | |
352 | s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); | |
353 | pci_conf[0x90] = s->smb_io_base | 1; | |
354 | pci_conf[0x91] = s->smb_io_base >> 8; | |
355 | pci_conf[0xd2] = 0x90; | |
798512e5 GH |
356 | pm_smbus_init(&s->dev.qdev, &s->smb); |
357 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); | |
edf79e66 | 358 | |
42d8a3cf | 359 | apm_init(dev, &s->apm, NULL, s); |
edf79e66 | 360 | |
1437c94b | 361 | memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); |
a2902821 GH |
362 | memory_region_set_enabled(&s->io, false); |
363 | memory_region_add_subregion(get_system_io(), 0, &s->io); | |
edf79e66 | 364 | |
77d58b1e | 365 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
b5a7c024 | 366 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
560e6396 | 367 | acpi_pm1_cnt_init(&s->ar, &s->io, 2); |
edf79e66 HC |
368 | |
369 | return 0; | |
370 | } | |
371 | ||
a5c82852 AF |
372 | I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
373 | qemu_irq sci_irq) | |
edf79e66 HC |
374 | { |
375 | PCIDevice *dev; | |
376 | VT686PMState *s; | |
377 | ||
378 | dev = pci_create(bus, devfn, "VT82C686B_PM"); | |
379 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
380 | ||
381 | s = DO_UPCAST(VT686PMState, dev, dev); | |
382 | ||
383 | qdev_init_nofail(&dev->qdev); | |
384 | ||
385 | return s->smb.smbus; | |
386 | } | |
387 | ||
40021f08 AL |
388 | static Property via_pm_properties[] = { |
389 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
390 | DEFINE_PROP_END_OF_LIST(), | |
391 | }; | |
392 | ||
393 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
394 | { | |
39bffca2 | 395 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
396 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
397 | ||
398 | k->init = vt82c686b_pm_initfn; | |
399 | k->config_write = pm_write_config; | |
400 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
401 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; | |
402 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
403 | k->revision = 0x40; | |
39bffca2 AL |
404 | dc->desc = "PM"; |
405 | dc->vmsd = &vmstate_acpi; | |
125ee0ed | 406 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
39bffca2 | 407 | dc->props = via_pm_properties; |
40021f08 AL |
408 | } |
409 | ||
8c43a6f0 | 410 | static const TypeInfo via_pm_info = { |
39bffca2 AL |
411 | .name = "VT82C686B_PM", |
412 | .parent = TYPE_PCI_DEVICE, | |
413 | .instance_size = sizeof(VT686PMState), | |
414 | .class_init = via_pm_class_init, | |
edf79e66 HC |
415 | }; |
416 | ||
edf79e66 HC |
417 | static const VMStateDescription vmstate_via = { |
418 | .name = "vt82c686b", | |
419 | .version_id = 1, | |
420 | .minimum_version_id = 1, | |
421 | .minimum_version_id_old = 1, | |
422 | .fields = (VMStateField []) { | |
423 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), | |
424 | VMSTATE_END_OF_LIST() | |
425 | } | |
426 | }; | |
427 | ||
428 | /* init the PCI-to-ISA bridge */ | |
429 | static int vt82c686b_initfn(PCIDevice *d) | |
430 | { | |
bcc37e24 | 431 | VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); |
edf79e66 | 432 | uint8_t *pci_conf; |
bcc37e24 | 433 | ISABus *isa_bus; |
edf79e66 HC |
434 | uint8_t *wmask; |
435 | int i; | |
436 | ||
bcc37e24 | 437 | isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d)); |
edf79e66 HC |
438 | |
439 | pci_conf = d->config; | |
edf79e66 | 440 | pci_config_set_prog_interface(pci_conf, 0x0); |
edf79e66 HC |
441 | |
442 | wmask = d->wmask; | |
443 | for (i = 0x00; i < 0xff; i++) { | |
444 | if (i<=0x03 || (i>=0x08 && i<=0x3f)) { | |
445 | wmask[i] = 0x00; | |
446 | } | |
447 | } | |
448 | ||
db10ca90 | 449 | memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, |
2c9b15ca | 450 | &vt82c->superio_conf, "superio", 2); |
bcc37e24 JK |
451 | memory_region_set_enabled(&vt82c->superio, false); |
452 | /* The floppy also uses 0x3f0 and 0x3f1. | |
453 | * But we do not emulate a floppy, so just set it here. */ | |
454 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, | |
455 | &vt82c->superio); | |
456 | ||
edf79e66 HC |
457 | qemu_register_reset(vt82c686b_reset, d); |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
c9940edb | 462 | ISABus *vt82c686b_init(PCIBus *bus, int devfn) |
edf79e66 HC |
463 | { |
464 | PCIDevice *d; | |
465 | ||
aa5fb7b3 | 466 | d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); |
edf79e66 | 467 | |
2ae0e48d | 468 | return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); |
edf79e66 HC |
469 | } |
470 | ||
40021f08 AL |
471 | static void via_class_init(ObjectClass *klass, void *data) |
472 | { | |
39bffca2 | 473 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
474 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
475 | ||
476 | k->init = vt82c686b_initfn; | |
477 | k->config_write = vt82c686b_write_config; | |
478 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
479 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; | |
480 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
481 | k->revision = 0x40; | |
39bffca2 | 482 | dc->desc = "ISA bridge"; |
39bffca2 | 483 | dc->vmsd = &vmstate_via; |
04916ee9 MA |
484 | /* |
485 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, | |
486 | * e.g. by mips_fulong2e_init() | |
487 | */ | |
488 | dc->cannot_instantiate_with_device_add_yet = true; | |
40021f08 AL |
489 | } |
490 | ||
8c43a6f0 | 491 | static const TypeInfo via_info = { |
39bffca2 AL |
492 | .name = "VT82C686B", |
493 | .parent = TYPE_PCI_DEVICE, | |
494 | .instance_size = sizeof(VT82C686BState), | |
495 | .class_init = via_class_init, | |
edf79e66 HC |
496 | }; |
497 | ||
83f7d43a | 498 | static void vt82c686b_register_types(void) |
edf79e66 | 499 | { |
83f7d43a AF |
500 | type_register_static(&via_ac97_info); |
501 | type_register_static(&via_mc97_info); | |
502 | type_register_static(&via_pm_info); | |
39bffca2 | 503 | type_register_static(&via_info); |
edf79e66 | 504 | } |
83f7d43a AF |
505 | |
506 | type_init(vt82c686b_register_types) |