[thirdparty/qemu.git] / hw / timer / grlib_gptimer.c

/*
 * QEMU GRLIB GPTimer Emulator
 *
 * Copyright (c) 2010-2019 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sparc/grlib.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "qemu/module.h"

#include "trace.h"

#define UNIT_REG_SIZE    16     /* Size of memory mapped regs for the unit */
#define GPTIMER_REG_SIZE 16     /* Size of memory mapped regs for a GPTimer */

#define GPTIMER_MAX_TIMERS 8

/* GPTimer Config register fields */
#define GPTIMER_ENABLE      (1 << 0)
#define GPTIMER_RESTART     (1 << 1)
#define GPTIMER_LOAD        (1 << 2)
#define GPTIMER_INT_ENABLE  (1 << 3)
#define GPTIMER_INT_PENDING (1 << 4)
#define GPTIMER_CHAIN       (1 << 5) /* Not supported */
#define GPTIMER_DEBUG_HALT  (1 << 6) /* Not supported */

/* Memory mapped register offsets */
#define SCALER_OFFSET         0x00
#define SCALER_RELOAD_OFFSET  0x04
#define CONFIG_OFFSET         0x08
#define COUNTER_OFFSET        0x00
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE            0x10

#define GRLIB_GPTIMER(obj) \
    OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)

typedef struct GPTimer     GPTimer;
typedef struct GPTimerUnit GPTimerUnit;

struct GPTimer {
    struct ptimer_state *ptimer;

    qemu_irq     irq;
    int          id;
    GPTimerUnit *unit;

    /* registers */
    uint32_t counter;
    uint32_t reload;
    uint32_t config;
};

struct GPTimerUnit {
    SysBusDevice  parent_obj;

    MemoryRegion iomem;

    uint32_t nr_timers;         /* Number of timers available */
    uint32_t freq_hz;           /* System frequency */
    uint32_t irq_line;          /* Base irq line */

    GPTimer *timers;

    /* registers */
    uint32_t scaler;
    uint32_t reload;
    uint32_t config;
};

static void grlib_gptimer_tx_begin(GPTimer *timer)
{
    ptimer_transaction_begin(timer->ptimer);
}

static void grlib_gptimer_tx_commit(GPTimer *timer)
{
    ptimer_transaction_commit(timer->ptimer);
}

/* Must be called within grlib_gptimer_tx_begin/commit block */
static void grlib_gptimer_enable(GPTimer *timer)
{
    assert(timer != NULL);


    ptimer_stop(timer->ptimer);

    if (!(timer->config & GPTIMER_ENABLE)) {
        /* Timer disabled */
        trace_grlib_gptimer_disabled(timer->id, timer->config);
        return;
    }

    /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
       underflow. Set count + 1 to simulate the GPTimer behavior. */

    trace_grlib_gptimer_enable(timer->id, timer->counter);

    ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
    ptimer_run(timer->ptimer, 1);
}

/* Must be called within grlib_gptimer_tx_begin/commit block */
static void grlib_gptimer_restart(GPTimer *timer)
{
    assert(timer != NULL);

    trace_grlib_gptimer_restart(timer->id, timer->reload);

    timer->counter = timer->reload;
    grlib_gptimer_enable(timer);
}

static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
{
    int i = 0;
    uint32_t value = 0;

    assert(unit != NULL);

    if (scaler > 0) {
        value = unit->freq_hz / (scaler + 1);
    } else {
        value = unit->freq_hz;
    }

    trace_grlib_gptimer_set_scaler(scaler, value);

    for (i = 0; i < unit->nr_timers; i++) {
        ptimer_transaction_begin(unit->timers[i].ptimer);
        ptimer_set_freq(unit->timers[i].ptimer, value);
        ptimer_transaction_commit(unit->timers[i].ptimer);
    }
}

static void grlib_gptimer_hit(void *opaque)
{
    GPTimer *timer = opaque;
    assert(timer != NULL);

    trace_grlib_gptimer_hit(timer->id);

    /* Timer expired */

    if (timer->config & GPTIMER_INT_ENABLE) {
        /* Set the pending bit (only unset by write in the config register) */
        timer->config |= GPTIMER_INT_PENDING;
        qemu_irq_pulse(timer->irq);
    }

    if (timer->config & GPTIMER_RESTART) {
        grlib_gptimer_restart(timer);
    }
}

static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
                                   unsigned size)
{
    GPTimerUnit        *unit  = opaque;
    hwaddr  timer_addr;
    int                 id;
    uint32_t            value = 0;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->scaler);
        return unit->scaler;

    case SCALER_RELOAD_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->reload);
        return unit->reload;

    case CONFIG_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->config);
        return unit->config;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            value = ptimer_get_count(unit->timers[id].ptimer);
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case COUNTER_RELOAD_OFFSET:
            value = unit->timers[id].reload;
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
            return unit->timers[id].config;

        default:
            break;
        }

    }

    trace_grlib_gptimer_readl(-1, addr, 0);
    return 0;
}

static void grlib_gptimer_write(void *opaque, hwaddr addr,
                                uint64_t value, unsigned size)
{
    GPTimerUnit        *unit = opaque;
    hwaddr  timer_addr;
    int                 id;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->scaler = value;
        trace_grlib_gptimer_writel(-1, addr, unit->scaler);
        return;

    case SCALER_RELOAD_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->reload = value;
        trace_grlib_gptimer_writel(-1, addr, unit->reload);
        grlib_gptimer_set_scaler(unit, value);
        return;

    case CONFIG_OFFSET:
        /* Read Only (disable timer freeze not supported) */
        trace_grlib_gptimer_writel(-1, addr, 0);
        return;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            grlib_gptimer_tx_begin(&unit->timers[id]);
            unit->timers[id].counter = value;
            grlib_gptimer_enable(&unit->timers[id]);
            grlib_gptimer_tx_commit(&unit->timers[id]);
            return;

        case COUNTER_RELOAD_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            unit->timers[id].reload = value;
            return;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);

            if (value & GPTIMER_INT_PENDING) {
                /* clear pending bit */
                value &= ~GPTIMER_INT_PENDING;
            } else {
                /* keep pending bit */
                value |= unit->timers[id].config & GPTIMER_INT_PENDING;
            }

            unit->timers[id].config = value;

            /* gptimer_restart calls gptimer_enable, so if "enable" and "load"
               bits are present, we just have to call restart. */

            grlib_gptimer_tx_begin(&unit->timers[id]);
            if (value & GPTIMER_LOAD) {
                grlib_gptimer_restart(&unit->timers[id]);
            } else if (value & GPTIMER_ENABLE) {
                grlib_gptimer_enable(&unit->timers[id]);
            }

            /* These fields must always be read as 0 */
            value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);

            unit->timers[id].config = value;
            grlib_gptimer_tx_commit(&unit->timers[id]);
            return;

        default:
            break;
        }

    }

    trace_grlib_gptimer_writel(-1, addr, value);
}

static const MemoryRegionOps grlib_gptimer_ops = {
    .read = grlib_gptimer_read,
    .write = grlib_gptimer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_gptimer_reset(DeviceState *d)
{
    GPTimerUnit *unit = GRLIB_GPTIMER(d);
    int          i    = 0;

    assert(unit != NULL);

    unit->scaler = 0;
    unit->reload = 0;

    unit->config  = unit->nr_timers;
    unit->config |= unit->irq_line << 3;
    unit->config |= 1 << 8;     /* separate interrupt */
    unit->config |= 1 << 9;     /* Disable timer freeze */


    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->counter = 0;
        timer->reload = 0;
        timer->config = 0;
        ptimer_transaction_begin(timer->ptimer);
        ptimer_stop(timer->ptimer);
        ptimer_set_count(timer->ptimer, 0);
        ptimer_set_freq(timer->ptimer, unit->freq_hz);
        ptimer_transaction_commit(timer->ptimer);
    }
}

static void grlib_gptimer_realize(DeviceState *dev, Error **errp)
{
    GPTimerUnit  *unit = GRLIB_GPTIMER(dev);
    unsigned int  i;
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    assert(unit->nr_timers > 0);
    assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);

    unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);

    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->unit   = unit;
        timer->ptimer = ptimer_init(grlib_gptimer_hit, timer,
                                    PTIMER_POLICY_DEFAULT);
        timer->id     = i;

        /* One IRQ line for each timer */
        sysbus_init_irq(sbd, &timer->irq);

        ptimer_transaction_begin(timer->ptimer);
        ptimer_set_freq(timer->ptimer, unit->freq_hz);
        ptimer_transaction_commit(timer->ptimer);
    }

    memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
                          unit, "gptimer",
                          UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);

    sysbus_init_mmio(sbd, &unit->iomem);
}

static Property grlib_gptimer_properties[] = {
    DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz,   40000000),
    DEFINE_PROP_UINT32("irq-line",  GPTimerUnit, irq_line,  8),
    DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = grlib_gptimer_realize;
    dc->reset = grlib_gptimer_reset;
    device_class_set_props(dc, grlib_gptimer_properties);
}

static const TypeInfo grlib_gptimer_info = {
    .name          = TYPE_GRLIB_GPTIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(GPTimerUnit),
    .class_init    = grlib_gptimer_class_init,
};

static void grlib_gptimer_register_types(void)
{
    type_register_static(&grlib_gptimer_info);
}

type_init(grlib_gptimer_register_types)
Commit	Line	Data
0f3a4a01 FC	1	/*
	2	* QEMU GRLIB GPTimer Emulator
	3	*
948caec8	4	* Copyright (c) 2010-2019 AdaCore
0f3a4a01 FC	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
db5ebe5f	25	#include "qemu/osdep.h"
948caec8	26	#include "hw/sparc/grlib.h"
83c9f4ca	27	#include "hw/sysbus.h"
1de7afc9	28	#include "qemu/timer.h"
64552b6b	29	#include "hw/irq.h"
83c9f4ca	30	#include "hw/ptimer.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
0b8fa32f	32	#include "qemu/module.h"
0f3a4a01 FC	33
	34	#include "trace.h"
	35
	36	#define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */
	37	#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */
	38
	39	#define GPTIMER_MAX_TIMERS 8
	40
	41	/* GPTimer Config register fields */
	42	#define GPTIMER_ENABLE (1 << 0)
	43	#define GPTIMER_RESTART (1 << 1)
	44	#define GPTIMER_LOAD (1 << 2)
	45	#define GPTIMER_INT_ENABLE (1 << 3)
	46	#define GPTIMER_INT_PENDING (1 << 4)
	47	#define GPTIMER_CHAIN (1 << 5) /* Not supported */
	48	#define GPTIMER_DEBUG_HALT (1 << 6) /* Not supported */
	49
	50	/* Memory mapped register offsets */
	51	#define SCALER_OFFSET 0x00
	52	#define SCALER_RELOAD_OFFSET 0x04
	53	#define CONFIG_OFFSET 0x08
	54	#define COUNTER_OFFSET 0x00
	55	#define COUNTER_RELOAD_OFFSET 0x04
	56	#define TIMER_BASE 0x10
	57
541ab55f AF	58	#define GRLIB_GPTIMER(obj) \
	59	OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)
	60
0f3a4a01 FC	61	typedef struct GPTimer GPTimer;
	62	typedef struct GPTimerUnit GPTimerUnit;
	63
	64	struct GPTimer {
0f3a4a01 FC	65	struct ptimer_state *ptimer;
	66
	67	qemu_irq irq;
	68	int id;
	69	GPTimerUnit *unit;
	70
	71	/* registers */
	72	uint32_t counter;
	73	uint32_t reload;
	74	uint32_t config;
	75	};
	76
	77	struct GPTimerUnit {
541ab55f AF	78	SysBusDevice parent_obj;
541ab55f AF	79
cde844fa	80	MemoryRegion iomem;
0f3a4a01 FC	81
	82	uint32_t nr_timers; /* Number of timers available */
	83	uint32_t freq_hz; /* System frequency */
	84	uint32_t irq_line; /* Base irq line */
	85
	86	GPTimer *timers;
	87
	88	/* registers */
	89	uint32_t scaler;
	90	uint32_t reload;
	91	uint32_t config;
	92	};
	93
663e475f PM	94	static void grlib_gptimer_tx_begin(GPTimer *timer)
	95	{
	96	ptimer_transaction_begin(timer->ptimer);
	97	}
	98
	99	static void grlib_gptimer_tx_commit(GPTimer *timer)
	100	{
	101	ptimer_transaction_commit(timer->ptimer);
	102	}
	103
	104	/* Must be called within grlib_gptimer_tx_begin/commit block */
0f3a4a01 FC	105	static void grlib_gptimer_enable(GPTimer *timer)
	106	{
	107	assert(timer != NULL);
	108
	109
	110	ptimer_stop(timer->ptimer);
	111
	112	if (!(timer->config & GPTIMER_ENABLE)) {
	113	/* Timer disabled */
	114	trace_grlib_gptimer_disabled(timer->id, timer->config);
	115	return;
	116	}
	117
	118	/* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
	119	underflow. Set count + 1 to simulate the GPTimer behavior. */
	120
9d5614d5	121	trace_grlib_gptimer_enable(timer->id, timer->counter);
0f3a4a01	122
9d5614d5	123	ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
0f3a4a01 FC	124	ptimer_run(timer->ptimer, 1);
	125	}
	126
663e475f	127	/* Must be called within grlib_gptimer_tx_begin/commit block */
0f3a4a01 FC	128	static void grlib_gptimer_restart(GPTimer *timer)
	129	{
	130	assert(timer != NULL);
	131
	132	trace_grlib_gptimer_restart(timer->id, timer->reload);
	133
	134	timer->counter = timer->reload;
	135	grlib_gptimer_enable(timer);
	136	}
	137
	138	static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
	139	{
	140	int i = 0;
	141	uint32_t value = 0;
	142
	143	assert(unit != NULL);
	144
	145	if (scaler > 0) {
	146	value = unit->freq_hz / (scaler + 1);
	147	} else {
	148	value = unit->freq_hz;
	149	}
	150
	151	trace_grlib_gptimer_set_scaler(scaler, value);
	152
	153	for (i = 0; i < unit->nr_timers; i++) {
663e475f	154	ptimer_transaction_begin(unit->timers[i].ptimer);
0f3a4a01	155	ptimer_set_freq(unit->timers[i].ptimer, value);
663e475f	156	ptimer_transaction_commit(unit->timers[i].ptimer);
0f3a4a01 FC	157	}
	158	}
	159
	160	static void grlib_gptimer_hit(void *opaque)
	161	{
	162	GPTimer *timer = opaque;
	163	assert(timer != NULL);
	164
	165	trace_grlib_gptimer_hit(timer->id);
	166
	167	/* Timer expired */
	168
	169	if (timer->config & GPTIMER_INT_ENABLE) {
	170	/* Set the pending bit (only unset by write in the config register) */
	171	timer->config \|= GPTIMER_INT_PENDING;
	172	qemu_irq_pulse(timer->irq);
	173	}
	174
	175	if (timer->config & GPTIMER_RESTART) {
	176	grlib_gptimer_restart(timer);
	177	}
	178	}
	179
a8170e5e	180	static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
cde844fa	181	unsigned size)
0f3a4a01 FC	182	{
0f3a4a01 FC	183	GPTimerUnit *unit = opaque;
a8170e5e	184	hwaddr timer_addr;
0f3a4a01 FC	185	int id;
	186	uint32_t value = 0;
	187
	188	addr &= 0xff;
	189
	190	/* Unit registers */
	191	switch (addr) {
	192	case SCALER_OFFSET:
b4548fcc	193	trace_grlib_gptimer_readl(-1, addr, unit->scaler);
0f3a4a01 FC	194	return unit->scaler;
	195
	196	case SCALER_RELOAD_OFFSET:
b4548fcc	197	trace_grlib_gptimer_readl(-1, addr, unit->reload);
0f3a4a01 FC	198	return unit->reload;
	199
	200	case CONFIG_OFFSET:
b4548fcc	201	trace_grlib_gptimer_readl(-1, addr, unit->config);
0f3a4a01 FC	202	return unit->config;
	203
	204	default:
	205	break;
	206	}
	207
	208	timer_addr = (addr % TIMER_BASE);
	209	id = (addr - TIMER_BASE) / TIMER_BASE;
	210
	211	if (id >= 0 && id < unit->nr_timers) {
	212
	213	/* GPTimer registers */
	214	switch (timer_addr) {
	215	case COUNTER_OFFSET:
	216	value = ptimer_get_count(unit->timers[id].ptimer);
b4548fcc	217	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	218	return value;
	219
	220	case COUNTER_RELOAD_OFFSET:
	221	value = unit->timers[id].reload;
b4548fcc	222	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	223	return value;
	224
	225	case CONFIG_OFFSET:
b4548fcc	226	trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
0f3a4a01 FC	227	return unit->timers[id].config;
	228
	229	default:
	230	break;
	231	}
	232
	233	}
	234
b4548fcc	235	trace_grlib_gptimer_readl(-1, addr, 0);
0f3a4a01 FC	236	return 0;
	237	}
	238
a8170e5e	239	static void grlib_gptimer_write(void *opaque, hwaddr addr,
cde844fa	240	uint64_t value, unsigned size)
0f3a4a01 FC	241	{
0f3a4a01 FC	242	GPTimerUnit *unit = opaque;
a8170e5e	243	hwaddr timer_addr;
0f3a4a01 FC	244	int id;
	245
	246	addr &= 0xff;
	247
	248	/* Unit registers */
	249	switch (addr) {
	250	case SCALER_OFFSET:
	251	value &= 0xFFFF; /* clean up the value */
	252	unit->scaler = value;
b4548fcc	253	trace_grlib_gptimer_writel(-1, addr, unit->scaler);
0f3a4a01 FC	254	return;
	255
	256	case SCALER_RELOAD_OFFSET:
	257	value &= 0xFFFF; /* clean up the value */
	258	unit->reload = value;
b4548fcc	259	trace_grlib_gptimer_writel(-1, addr, unit->reload);
0f3a4a01 FC	260	grlib_gptimer_set_scaler(unit, value);
	261	return;
	262
	263	case CONFIG_OFFSET:
	264	/* Read Only (disable timer freeze not supported) */
b4548fcc	265	trace_grlib_gptimer_writel(-1, addr, 0);
0f3a4a01 FC	266	return;
	267
	268	default:
	269	break;
	270	}
	271
	272	timer_addr = (addr % TIMER_BASE);
	273	id = (addr - TIMER_BASE) / TIMER_BASE;
	274
	275	if (id >= 0 && id < unit->nr_timers) {
	276
	277	/* GPTimer registers */
	278	switch (timer_addr) {
	279	case COUNTER_OFFSET:
b4548fcc	280	trace_grlib_gptimer_writel(id, addr, value);
663e475f	281	grlib_gptimer_tx_begin(&unit->timers[id]);
0f3a4a01 FC	282	unit->timers[id].counter = value;
0f3a4a01 FC	283	grlib_gptimer_enable(&unit->timers[id]);
663e475f	284	grlib_gptimer_tx_commit(&unit->timers[id]);
0f3a4a01 FC	285	return;
	286
	287	case COUNTER_RELOAD_OFFSET:
b4548fcc	288	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	289	unit->timers[id].reload = value;
	290	return;
	291
	292	case CONFIG_OFFSET:
b4548fcc	293	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	294
	295	if (value & GPTIMER_INT_PENDING) {
	296	/* clear pending bit */
	297	value &= ~GPTIMER_INT_PENDING;
	298	} else {
	299	/* keep pending bit */
	300	value \|= unit->timers[id].config & GPTIMER_INT_PENDING;
	301	}
	302
	303	unit->timers[id].config = value;
	304
	305	/* gptimer_restart calls gptimer_enable, so if "enable" and "load"
	306	bits are present, we just have to call restart. */
	307
663e475f	308	grlib_gptimer_tx_begin(&unit->timers[id]);
0f3a4a01 FC	309	if (value & GPTIMER_LOAD) {
	310	grlib_gptimer_restart(&unit->timers[id]);
	311	} else if (value & GPTIMER_ENABLE) {
	312	grlib_gptimer_enable(&unit->timers[id]);
	313	}
	314
	315	/* These fields must always be read as 0 */
	316	value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);
	317
	318	unit->timers[id].config = value;
663e475f	319	grlib_gptimer_tx_commit(&unit->timers[id]);
0f3a4a01 FC	320	return;
	321
	322	default:
	323	break;
	324	}
	325
	326	}
	327
b4548fcc	328	trace_grlib_gptimer_writel(-1, addr, value);
0f3a4a01 FC	329	}
0f3a4a01 FC	330
cde844fa AK	331	static const MemoryRegionOps grlib_gptimer_ops = {
	332	.read = grlib_gptimer_read,
	333	.write = grlib_gptimer_write,
	334	.endianness = DEVICE_NATIVE_ENDIAN,
	335	.valid = {
	336	.min_access_size = 4,
	337	.max_access_size = 4,
	338	},
0f3a4a01 FC	339	};
	340
	341	static void grlib_gptimer_reset(DeviceState *d)
	342	{
541ab55f	343	GPTimerUnit *unit = GRLIB_GPTIMER(d);
0f3a4a01 FC	344	int i = 0;
	345
	346	assert(unit != NULL);
	347
	348	unit->scaler = 0;
	349	unit->reload = 0;
0f3a4a01 FC	350
	351	unit->config = unit->nr_timers;
	352	unit->config \|= unit->irq_line << 3;
	353	unit->config \|= 1 << 8; /* separate interrupt */
	354	unit->config \|= 1 << 9; /* Disable timer freeze */
	355
	356
	357	for (i = 0; i < unit->nr_timers; i++) {
	358	GPTimer *timer = &unit->timers[i];
	359
	360	timer->counter = 0;
	361	timer->reload = 0;
	362	timer->config = 0;
663e475f	363	ptimer_transaction_begin(timer->ptimer);
0f3a4a01 FC	364	ptimer_stop(timer->ptimer);
	365	ptimer_set_count(timer->ptimer, 0);
	366	ptimer_set_freq(timer->ptimer, unit->freq_hz);
663e475f	367	ptimer_transaction_commit(timer->ptimer);
0f3a4a01 FC	368	}
	369	}
	370
23251fb8	371	static void grlib_gptimer_realize(DeviceState dev, Error *errp)
0f3a4a01	372	{
541ab55f	373	GPTimerUnit *unit = GRLIB_GPTIMER(dev);
0f3a4a01	374	unsigned int i;
23251fb8	375	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
0f3a4a01 FC	376
	377	assert(unit->nr_timers > 0);
	378	assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
	379
7267c094	380	unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
0f3a4a01 FC	381
	382	for (i = 0; i < unit->nr_timers; i++) {
	383	GPTimer *timer = &unit->timers[i];
	384
	385	timer->unit = unit;
663e475f PM	386	timer->ptimer = ptimer_init(grlib_gptimer_hit, timer,
663e475f PM	387	PTIMER_POLICY_DEFAULT);
0f3a4a01 FC	388	timer->id = i;
	389
	390	/* One IRQ line for each timer */
23251fb8	391	sysbus_init_irq(sbd, &timer->irq);
0f3a4a01	392
663e475f	393	ptimer_transaction_begin(timer->ptimer);
0f3a4a01	394	ptimer_set_freq(timer->ptimer, unit->freq_hz);
663e475f	395	ptimer_transaction_commit(timer->ptimer);
0f3a4a01 FC	396	}
0f3a4a01 FC	397
853dca12 PB	398	memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
853dca12 PB	399	unit, "gptimer",
cde844fa	400	UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
0f3a4a01	401
23251fb8	402	sysbus_init_mmio(sbd, &unit->iomem);
0f3a4a01 FC	403	}
0f3a4a01 FC	404
999e12bb AL	405	static Property grlib_gptimer_properties[] = {
	406	DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000),
	407	DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8),
	408	DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
	409	DEFINE_PROP_END_OF_LIST(),
	410	};
	411
	412	static void grlib_gptimer_class_init(ObjectClass klass, void data)
	413	{
39bffca2	414	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	415
23251fb8	416	dc->realize = grlib_gptimer_realize;
39bffca2	417	dc->reset = grlib_gptimer_reset;
4f67d30b	418	device_class_set_props(dc, grlib_gptimer_properties);
999e12bb AL	419	}
999e12bb AL	420
8c43a6f0	421	static const TypeInfo grlib_gptimer_info = {
541ab55f	422	.name = TYPE_GRLIB_GPTIMER,
39bffca2 AL	423	.parent = TYPE_SYS_BUS_DEVICE,
	424	.instance_size = sizeof(GPTimerUnit),
	425	.class_init = grlib_gptimer_class_init,
0f3a4a01 FC	426	};
0f3a4a01 FC	427
83f7d43a	428	static void grlib_gptimer_register_types(void)
0f3a4a01	429	{
39bffca2	430	type_register_static(&grlib_gptimer_info);
0f3a4a01 FC	431	}
0f3a4a01 FC	432
83f7d43a	433	type_init(grlib_gptimer_register_types)