[people/ms/u-boot.git] / include / configs / C29XPCIE.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * C29XPCIE board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifdef CONFIG_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_NAND_INIT
#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE		(128 << 10)
#define CONFIG_SPL_TEXT_BASE		0xf8f81000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE		0xff800000
#define CONFIG_SPL_MAX_SIZE		8192
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
#endif
#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_TPL_PAD_TO		0x20000
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SYS_TEXT_BASE		0x11001000
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0xeff40000
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

/* High Level Configuration Options */
#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */

#ifdef CONFIG_PCI
#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

/*
 * PCI Windows
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif

#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

#define CONFIG_DDR_CLK_FREQ	100000000
#define CONFIG_SYS_CLK_FREQ	66666666

#define CONFIG_HWCONFIG

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */


#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_ADDR_MAP			1
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */

#define CONFIG_SYS_MEMTEST_START	0x00200000
#define CONFIG_SYS_MEMTEST_END		0x00400000

/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM		0
#define SPD_EEPROM_ADDRESS		0x50
#define CONFIG_SYS_DDR_RAW_TIMING

/* DDR ECC Setup*/
#define CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER

#define CONFIG_SYS_SDRAM_SIZE		512
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_CCSRBAR		0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* Platform SRAM setting  */
#define CONFIG_SYS_PLATFORM_SRAM_BASE	0xffb00000
#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
#define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)

/*
 * IFC Definitions
 */
/* NOR Flash on IFC */
#define CONFIG_SYS_FLASH_BASE		0xec000000
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */

#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* in ms */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* in ms */

/* 16Bit NOR Flash - S29GL512S10TFI01 */
#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)

#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

/* CFI for NOR Flash */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

/* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)

/* 8Bit NAND Flash - K9F1G08U0B */
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_NAND \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
				FTIM0_NAND_TWP(0x0c)   | \
				FTIM0_NAND_TWCHT(0x08) | \
				FTIM0_NAND_TWH(0x06))
#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x28) | \
				FTIM1_NAND_TWBE(0x1d)  | \
				FTIM1_NAND_TRR(0x08)   | \
				FTIM1_NAND_TRP(0x0c))
#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0c) | \
				FTIM2_NAND_TREH(0x0a) | \
				FTIM2_NAND_TWHRE(0x18))
#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x04))

#define CONFIG_SYS_NAND_DDR_LAW		11

/* Set up IFC registers for boot location NOR/NAND */
#ifdef CONFIG_NAND
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

/* CPLD on IFC, selected by CS2 */
#define CONFIG_SYS_CPLD_BASE		0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull \
					| CONFIG_SYS_CPLD_BASE)

#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2	0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
				FTIM0_GPCM_TEADC(0x0e) | \
				FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
				FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
				FTIM2_GPCM_TCH(0x8) | \
				FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3	0x0

#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#endif

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
						- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)

/*
 * Config the L2 Cache as L2 SRAM
 */
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
#endif
#endif
#endif

/* Serial Port */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C EEPROM */
/* enable read and write access to EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

/* eSPI - Enhanced SPI */
#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII			/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

/* Default mode is RGMII mode */
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		2

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define CONFIG_ETHPRIME		"eTSEC1"
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_SIZE		0x2000
#endif
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
#endif
#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
#else
#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

/*
 * Environment Configuration
 */

#ifdef CONFIG_TSEC_ENET
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */

/* default location for tftp and bootm */
#define CONFIG_LOADADDR		1000000

#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"loadaddr=1000000\0"				\
	"consoledev=ttyS0\0"				\
	"ramdiskaddr=2000000\0"				\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
	"fdtaddr=1e00000\0"				\
	"fdtfile=name/of/device-tree.dtb\0"			\
	"othbootargs=ramdisk_size=600000\0"		\

#define CONFIG_RAMBOOTCOMMAND			\
	"setenv bootargs root=/dev/ram rw "	\
	"console=$consoledev,$baudrate $othbootargs; "	\
	"tftp $ramdiskaddr $ramdiskfile;"	\
	"tftp $loadaddr $bootfile;"		\
	"tftp $fdtaddr $fdtfile;"		\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
a8d9758d MH	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
3aab0cd8	4	* SPDX-License-Identifier: GPL-2.0+
a8d9758d MH	5	*/
	6
	7	/*
	8	* C29XPCIE board configuration file
	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
a8d9758d MH	14	#ifdef CONFIG_SPIFLASH
	15	#define CONFIG_RAMBOOT_SPIFLASH
	16	#define CONFIG_SYS_TEXT_BASE 0x11000000
e222b1f3	17	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
a8d9758d MH	18	#endif
a8d9758d MH	19
eb6b458c	20	#ifdef CONFIG_NAND
eb6b458c PL	21	#ifdef CONFIG_TPL_BUILD
	22	#define CONFIG_SPL_NAND_BOOT
	23	#define CONFIG_SPL_FLUSH_IMAGE
eb6b458c	24	#define CONFIG_SPL_NAND_INIT
76f1f388	25	#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
eb6b458c PL	26	#define CONFIG_SPL_COMMON_INIT_DDR
	27	#define CONFIG_SPL_MAX_SIZE (128 << 10)
	28	#define CONFIG_SPL_TEXT_BASE 0xf8f81000
	29	#define CONFIG_SYS_MPC85XX_NO_RESETVEC
e222b1f3	30	#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
eb6b458c PL	31	#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
	32	#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
	33	#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
	34	#elif defined(CONFIG_SPL_BUILD)
	35	#define CONFIG_SPL_INIT_MINIMAL
eb6b458c PL	36	#define CONFIG_SPL_NAND_MINIMAL
	37	#define CONFIG_SPL_FLUSH_IMAGE
	38	#define CONFIG_SPL_TEXT_BASE 0xff800000
	39	#define CONFIG_SPL_MAX_SIZE 8192
	40	#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
	41	#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
	42	#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
	43	#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
	44	#endif
	45	#define CONFIG_SPL_PAD_TO 0x20000
	46	#define CONFIG_TPL_PAD_TO 0x20000
	47	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	48	#define CONFIG_SYS_TEXT_BASE 0x11001000
	49	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	50	#endif
	51
a8d9758d	52	#ifndef CONFIG_SYS_TEXT_BASE
e222b1f3	53	#define CONFIG_SYS_TEXT_BASE 0xeff40000
a8d9758d MH	54	#endif
	55
	56	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	57	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	58	#endif
	59
eb6b458c PL	60	#ifdef CONFIG_SPL_BUILD
	61	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	62	#else
	63	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	64	#endif
	65
	66	#ifdef CONFIG_SPL_BUILD
	67	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
a8d9758d MH	68	#endif
	69
	70	/* High Level Configuration Options */
a8d9758d MH	71	#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
a8d9758d MH	72
a8d9758d	73	#ifdef CONFIG_PCI
b38eaec5	74	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
a8d9758d MH	75	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	76	#define CONFIG_PCI_INDIRECT_BRIDGE
	77	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	78	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	79
a8d9758d MH	80	/*
	81	* PCI Windows
	82	* Memory space is mapped 1-1, but I/O space must start from 0.
	83	*/
	84	/* controller 1, Slot 1, tgtid 1, Base address a000 */
	85	#define CONFIG_SYS_PCIE1_NAME "Slot 1"
	86	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	87	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	88	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	89	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
	90	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
	91	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	92	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	93	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
	94
a8d9758d	95	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
a8d9758d MH	96	#endif
a8d9758d MH	97
a8d9758d MH	98	#define CONFIG_TSEC_ENET
	99	#define CONFIG_ENV_OVERWRITE
	100
	101	#define CONFIG_DDR_CLK_FREQ 100000000
	102	#define CONFIG_SYS_CLK_FREQ 66666666
	103
	104	#define CONFIG_HWCONFIG
	105
	106	/*
	107	* These can be toggled for performance analysis, otherwise use default.
	108	*/
	109	#define CONFIG_L2_CACHE /* toggle L2 cache */
	110	#define CONFIG_BTB /* toggle branch predition */
	111
a8d9758d MH	112
	113	#define CONFIG_ENABLE_36BIT_PHYS
	114
	115	#define CONFIG_ADDR_MAP 1
	116	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	117
	118	#define CONFIG_SYS_MEMTEST_START 0x00200000
	119	#define CONFIG_SYS_MEMTEST_END 0x00400000
a8d9758d MH	120
a8d9758d MH	121	/* DDR Setup */
a8d9758d MH	122	#define CONFIG_DDR_SPD
	123	#define CONFIG_SYS_SPD_BUS_NUM 0
	124	#define SPD_EEPROM_ADDRESS 0x50
	125	#define CONFIG_SYS_DDR_RAW_TIMING
	126
	127	/* DDR ECC Setup*/
	128	#define CONFIG_DDR_ECC
	129	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	130	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	131
	132	#define CONFIG_SYS_SDRAM_SIZE 512
	133	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	134	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	135
	136	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	137	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	138
	139	#define CONFIG_SYS_CCSRBAR 0xffe00000
	140	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	141
	142	/* Platform SRAM setting */
	143	#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
	144	#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
	145	(0xf00000000ull \| CONFIG_SYS_PLATFORM_SRAM_BASE)
	146	#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
	147
	148	/*
	149	* IFC Definitions
	150	*/
	151	/* NOR Flash on IFC */
	152	#define CONFIG_SYS_FLASH_BASE 0xec000000
	153	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
	154
	155	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	156
	157	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
	158	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	159
	160	#define CONFIG_SYS_FLASH_QUIET_TEST
	161	#define CONFIG_FLASH_SHOW_PROGRESS 45
	162	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
	163	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
	164
	165	/* 16Bit NOR Flash - S29GL512S10TFI01 */
	166	#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	167	CSPR_PORT_SIZE_16 \| \
	168	CSPR_MSEL_NOR \| \
	169	CSPR_V)
	170	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(6410241024)
	171	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
ac2785c6	172
a8d9758d MH	173	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	174	FTIM0_NOR_TEADC(0x5) \| \
	175	FTIM0_NOR_TEAHC(0x5))
ac2785c6 PL	176	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	177	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	178	FTIM1_NOR_TSEQRAD_NOR(0x13))
a8d9758d MH	179	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
a8d9758d MH	180	FTIM2_NOR_TCH(0x4) \| \
ac2785c6	181	FTIM2_NOR_TWPH(0x0E) \| \
a8d9758d MH	182	FTIM2_NOR_TWP(0x1c))
	183	#define CONFIG_SYS_NOR_FTIM3 0x0
	184
	185	/* CFI for NOR Flash */
	186	#define CONFIG_FLASH_CFI_DRIVER
	187	#define CONFIG_SYS_FLASH_CFI
	188	#define CONFIG_SYS_FLASH_EMPTY_INFO
	189	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	190
	191	/* NAND Flash on IFC */
	192	#define CONFIG_NAND_FSL_IFC
	193	#define CONFIG_SYS_NAND_BASE 0xff800000
	194	#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
	195
	196	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	197
	198	#define CONFIG_SYS_MAX_NAND_DEVICE 1
eb6b458c	199	#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
a8d9758d MH	200
	201	/* 8Bit NAND Flash - K9F1G08U0B */
	202	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	203	\| CSPR_PORT_SIZE_8 \
	204	\| CSPR_MSEL_NAND \
	205	\| CSPR_V)
	206	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
affd520f	207	#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
a8d9758d MH	208	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	209	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	210	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
affd520f PK	211	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	212	\| CSOR_NAND_PGS_8K /* Page Size = 8K */ \
	213	\| CSOR_NAND_SPRZ_CSOR_EXT /oob in csor_ext/\
	214	\| CSOR_NAND_PB(128)) /128 Pages Per Block/
a8d9758d MH	215	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) \| \
	216	FTIM0_NAND_TWP(0x0c) \| \
	217	FTIM0_NAND_TWCHT(0x08) \| \
	218	FTIM0_NAND_TWH(0x06))
	219	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) \| \
	220	FTIM1_NAND_TWBE(0x1d) \| \
	221	FTIM1_NAND_TRR(0x08) \| \
	222	FTIM1_NAND_TRP(0x0c))
	223	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) \| \
	224	FTIM2_NAND_TREH(0x0a) \| \
	225	FTIM2_NAND_TWHRE(0x18))
	226	#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
	227
	228	#define CONFIG_SYS_NAND_DDR_LAW 11
	229
	230	/* Set up IFC registers for boot location NOR/NAND */
eb6b458c PL	231	#ifdef CONFIG_NAND
	232	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	233	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	234	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	235	#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
	236	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	237	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	238	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	239	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	240	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
	241	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	242	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	243	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	244	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	245	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	246	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	247	#else
a8d9758d MH	248	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
	249	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	250	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	251	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	252	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	253	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	254	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	255	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	256	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	257	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
affd520f	258	#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
a8d9758d MH	259	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	260	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	261	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	262	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
eb6b458c	263	#endif
a8d9758d MH	264
	265	/* CPLD on IFC, selected by CS2 */
	266	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	267	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
	268	\| CONFIG_SYS_CPLD_BASE)
	269
	270	#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
	271	\| CSPR_PORT_SIZE_8 \
	272	\| CSPR_MSEL_GPCM \
	273	\| CSPR_V)
	274	#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
	275	#define CONFIG_SYS_CSOR2 0x0
	276	/* CPLD Timing parameters for IFC CS2 */
	277	#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	278	FTIM0_GPCM_TEADC(0x0e) \| \
	279	FTIM0_GPCM_TEAHC(0x0e))
	280	#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	281	FTIM1_GPCM_TRAD(0x1f))
	282	#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
de519163	283	FTIM2_GPCM_TCH(0x8) \| \
a8d9758d MH	284	FTIM2_GPCM_TWP(0x1f))
	285	#define CONFIG_SYS_CS2_FTIM3 0x0
	286
	287	#if defined(CONFIG_RAMBOOT_SPIFLASH)
	288	#define CONFIG_SYS_RAMBOOT
	289	#define CONFIG_SYS_EXTRA_ENV_RELOC
	290	#endif
	291
	292	#define CONFIG_BOARD_EARLY_INIT_R
	293
	294	#define CONFIG_SYS_INIT_RAM_LOCK
	295	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
b39d1213	296	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
a8d9758d	297
b39d1213	298	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
a8d9758d MH	299	- GENERATED_GBL_DATA_SIZE)
	300	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	301
9307cbab	302	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
eb6b458c PL	303	#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
	304
	305	/*
	306	* Config the L2 Cache as L2 SRAM
	307	*/
	308	#if defined(CONFIG_SPL_BUILD)
	309	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	310	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	311	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	312	#define CONFIG_SYS_L2_SIZE (256 << 10)
	313	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	314	#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	315	#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
	316	#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
	317	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
	318	#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
	319	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
	320	#elif defined(CONFIG_NAND)
	321	#ifdef CONFIG_TPL_BUILD
	322	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	323	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	324	#define CONFIG_SYS_L2_SIZE (256 << 10)
	325	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	326	#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
	327	#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
	328	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
	329	#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
	330	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
	331	#else
	332	#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
	333	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	334	#define CONFIG_SYS_L2_SIZE (256 << 10)
	335	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	336	#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
	337	#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
	338	#endif
	339	#endif
	340	#endif
a8d9758d MH	341
	342	/* Serial Port */
	343	#define CONFIG_CONS_INDEX 1
a8d9758d MH	344	#define CONFIG_SYS_NS16550_SERIAL
	345	#define CONFIG_SYS_NS16550_REG_SIZE 1
	346	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	347
eb6b458c PL	348	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
	349	#define CONFIG_NS16550_MIN_FUNCTIONS
	350	#endif
	351
a8d9758d MH	352	#define CONFIG_SYS_BAUDRATE_TABLE \
	353	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	354
	355	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	356	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	357
a8d9758d MH	358	#define CONFIG_SYS_I2C
	359	#define CONFIG_SYS_I2C_FSL
	360	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	361	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	362	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	363	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	364	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	365	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	366
	367	/* I2C EEPROM */
	368	/* enable read and write access to EEPROM */
a8d9758d MH	369	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	370	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	371	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	372
a8d9758d	373	/* eSPI - Enhanced SPI */
a8d9758d MH	374	#define CONFIG_SF_DEFAULT_SPEED 10000000
	375	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	376
	377	#ifdef CONFIG_TSEC_ENET
a8d9758d MH	378	#define CONFIG_MII /* MII PHY management */
	379	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	380	#define CONFIG_TSEC1 1
	381	#define CONFIG_TSEC1_NAME "eTSEC1"
	382	#define CONFIG_TSEC2 1
	383	#define CONFIG_TSEC2_NAME "eTSEC2"
	384
	385	/* Default mode is RGMII mode */
	386	#define TSEC1_PHY_ADDR 0
	387	#define TSEC2_PHY_ADDR 2
	388
	389	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	390	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	391
	392	#define CONFIG_ETHPRIME "eTSEC1"
a8d9758d MH	393	#endif /* CONFIG_TSEC_ENET */
	394
	395	/*
	396	* Environment
	397	*/
	398	#if defined(CONFIG_SYS_RAMBOOT)
	399	#if defined(CONFIG_RAMBOOT_SPIFLASH)
a8d9758d MH	400	#define CONFIG_ENV_SPI_BUS 0
	401	#define CONFIG_ENV_SPI_CS 0
	402	#define CONFIG_ENV_SPI_MAX_HZ 10000000
	403	#define CONFIG_ENV_SPI_MODE 0
	404	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	405	#define CONFIG_ENV_SECT_SIZE 0x10000
	406	#define CONFIG_ENV_SIZE 0x2000
	407	#endif
eb6b458c	408	#elif defined(CONFIG_NAND)
eb6b458c PL	409	#ifdef CONFIG_TPL_BUILD
	410	#define CONFIG_ENV_SIZE 0x2000
	411	#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
	412	#else
	413	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	414	#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
	415	#endif
	416	#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
a8d9758d	417	#else
a8d9758d	418	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
a8d9758d MH	419	#define CONFIG_ENV_SIZE 0x2000
	420	#define CONFIG_ENV_SECT_SIZE 0x20000
	421	#endif
	422
	423	#define CONFIG_LOADS_ECHO
	424	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	425
a8d9758d MH	426	/*
	427	* Miscellaneous configurable options
	428	*/
	429	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	430	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	431	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	432	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
a8d9758d	433
a8d9758d MH	434	/*
	435	* For booting Linux, the board info and command line data
	436	* have to be in the first 64 MB of memory, since this is
	437	* the maximum mapped by the Linux kernel during initialization.
	438	*/
	439	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
	440	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	441
	442	/*
	443	* Environment Configuration
	444	*/
	445
	446	#ifdef CONFIG_TSEC_ENET
	447	#define CONFIG_HAS_ETH0
	448	#define CONFIG_HAS_ETH1
	449	#endif
	450
	451	#define CONFIG_ROOTPATH "/opt/nfsroot"
	452	#define CONFIG_BOOTFILE "uImage"
	453	#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
	454
	455	/* default location for tftp and bootm */
	456	#define CONFIG_LOADADDR 1000000
	457
9c25ee6d PL	458	#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
9c25ee6d PL	459
a8d9758d MH	460	#define CONFIG_EXTRA_ENV_SETTINGS \
	461	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
	462	"netdev=eth0\0" \
	463	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	464	"loadaddr=1000000\0" \
	465	"consoledev=ttyS0\0" \
	466	"ramdiskaddr=2000000\0" \
	467	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	468	"fdtaddr=1e00000\0" \
a8d9758d MH	469	"fdtfile=name/of/device-tree.dtb\0" \
	470	"othbootargs=ramdisk_size=600000\0" \
	471
	472	#define CONFIG_RAMBOOTCOMMAND \
	473	"setenv bootargs root=/dev/ram rw " \
	474	"console=$consoledev,$baudrate $othbootargs; " \
	475	"tftp $ramdiskaddr $ramdiskfile;" \
	476	"tftp $loadaddr $bootfile;" \
	477	"tftp $fdtaddr $fdtfile;" \
	478	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	479
	480	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	481
3ca49c42 PL	482	#include <asm/fsl_secure_boot.h>
3ca49c42 PL	483
a8d9758d	484	#endif /* __CONFIG_H */