]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
objdump: Add configure time option to enable colored disassembly output by default.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3b8e069a
YS		 12022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
2
3 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
4 Rm_BANK,Rn is always 1.
5
c07ec968
PB		 62022-07-21 Peter Bergner <bergner@linux.ibm.com>
7
8 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
9 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
10 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
11 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
12 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
13 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
14 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
15
bbcab336
CZ		 162022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
17
18 * disassemble.c (disassemble_init_for_target): Set
19 created_styled_output for ARC based targets.
20 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
21 instead of fprintf_ftype throughout.
22 (find_format): Likewise.
23 (print_flags): Likewise.
24 (print_insn_arc): Likewise.
25
0bd09323
NC		 262022-07-08 Nick Clifton <nickc@redhat.com>
27
28 * 2.39 branch created.
29
a0f3a4c6
MN		 302022-07-04 Marcus Nilsson <brainbomb@gmail.com>
31
32 * disassemble.c: (disassemble_init_for_target): Set
33 created_styled_output for AVR based targets.
34 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
35 instead of fprintf_ftype throughout.
36 (avr_operand): Pass in and fill disassembler_style when
37 parsing operands.
38
69341966
AK		 392022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
40
41 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
42 table.
43
e3161106
SM		 442022-03-16 Simon Marchi <simon.marchi@efficios.com>
45
46 * configure.ac: Handle bfd_amdgcn_arch.
47 * configure: Re-generate.
48
d17e797f
MR		 492022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
50 Maciej W. Rozycki <macro@orcam.me.uk>
51
52 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
53 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
54 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
55 "bnez" instructions.
56
36d285b9
NC		 572022-02-17 Nick Clifton <nickc@redhat.com>
58
59 * po/sr.po: Updated Serbian translation.
60
a532eb72
ST		 612022-02-14 Sergei Trofimovich <siarheit@google.com>
62
63 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
64 * microblaze-opc.h: Follow 'fsqrt' rename.
65
5fe73d46
NC		 662022-01-24 Nick Clifton <nickc@redhat.com>
67
68 * po/ro.po: Updated Romanian translation.
69 * po/uk.po: Updated Ukranian translation.
70
f908e960
NC		 712022-01-22 Nick Clifton <nickc@redhat.com>
72
73 * configure: Regenerate.
74 * po/opcodes.pot: Regenerate.
75
a74e1cb3
NC		 762022-01-22 Nick Clifton <nickc@redhat.com>
77
78 * 2.38 release branch created.
79
6c037fdb
NC		 802022-01-17 Nick Clifton <nickc@redhat.com>
81
82 * Makefile.in: Regenerate.
83 * po/opcodes.pot: Regenerate.
84
96c7115a
MN		 852021-12-02 Marcus Nilsson <brainbomb@gmail.com>
86
87 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
88 in insn_type on branching instructions.
89
3a337a86
AB		 902021-11-25 Andrew Burgess <aburgess@redhat.com>
91 Simon Cook <simon.cook@embecosm.com>
92
93 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
94 (riscv_options): New static global.
95 (disassembler_options_riscv): New function.
96 (print_riscv_disassembler_options): Rewrite to use
97 disassembler_options_riscv.
98
7060c28e
NC		 992021-11-25 Nick Clifton <nickc@redhat.com>
100
101 PR 28614
102 * aarch64-asm.c: Replace assert(0) with real code.
103 * aarch64-dis.c: Likewise.
104 * aarch64-opc.c: Likewise.
105
79abb939
NC		 1062021-11-25 Nick Clifton <nickc@redhat.com>
107
108 * po/fr.po; Updated French translation.
109
2b677209
MR		 1102021-10-27 Maciej W. Rozycki <macro@embecosm.com>
111
112 * Makefile.am: Remove obsolete comment.
113 * configure.ac: Refer `libbfd.la' to link shared BFD library
114 except for Cygwin.
115 * Makefile.in: Regenerate.
116 * configure: Regenerate.
117
b9004024
NA		 1182021-09-27 Nick Alcock <nick.alcock@oracle.com>
119
120 * configure: Regenerate.
121
4d5d5d46
PB		 1222021-09-25 Peter Bergner <bergner@linux.ibm.com>
123
124 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
125 on POWER5 and later.
126
6a7f5766
AB		 1272021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
128
129 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
130 before an unknown instruction, '%d' is replaced with the
131 instruction length.
132
718aefcf
NC		 1332021-09-02 Nick Clifton <nickc@redhat.com>
134
135 PR 28292
136 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
137 of BFD_RELOC_16.
138
5d9cff51
SV		 1392021-08-17 Shahab Vahedi <shahab@synopsys.com>
140
141 * arc-regs.h (DEF): Fix the register numbers.
142
3ee0cd9e
NC		 1432021-08-10 Nick Clifton <nickc@redhat.com>
144
145 * po/sr.po: Updated Serbian translation.
146
8d56b9fc
CX		 1472021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
148
149 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
150
b180e829
AK		 1512021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
152
153 * s390-opc.txt: Add qpaci.
154
346d80ef
NC		 1552021-07-03 Nick Clifton <nickc@redhat.com>
156
157 * configure: Regenerate.
158 * po/opcodes.pot: Regenerate.
159
51419248
NC		 1602021-07-03 Nick Clifton <nickc@redhat.com>
161
162 * 2.37 release branch created.
163
62194b63
AM		 1642021-07-02 Alan Modra <amodra@gmail.com>
165
166 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
167 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
168 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
169 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
170 (nds32_keyword_gpr): Move declarations to..
171 * nds32-asm.h: ..here, constifying to match definitions.
172
2fe36d31
MF		 1732021-07-01 Mike Frysinger <vapier@gentoo.org>
174
175 * Makefile.am (GUILE): New variable.
176 (CGEN): Use $(GUILE).
177 * Makefile.in: Regenerate.
178
f375d32b
MF		 1792021-07-01 Mike Frysinger <vapier@gentoo.org>
180
181 * mep-asm.c (macros): Mark static & const.
182 (lookup_macro): Change return & m to const.
183 (expand_macro): Change mac to const.
184 (expand_string): Change pmacro to const.
185
9b2beaf7
MF		 1862021-07-01 Mike Frysinger <vapier@gentoo.org>
187
188 * nds32-asm.c (operand_fields): Rename to ...
189 (nds32_operand_fields): ... this.
190 (keyword_gpr): Rename to ...
191 (nds32_keyword_gpr): ... this.
192 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
193 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
194 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
195 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
196 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
197 Mark static.
198 (keywords): Rename to ...
199 (nds32_keywords): ... this.
200 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
201 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
202
ac8ef696
MF		 2032021-07-01 Mike Frysinger <vapier@gentoo.org>
204
205 * z80-dis.c (opc_ed): Make const.
206 (pref_ed): Make p const.
207
52b83874
MF		 2082021-07-01 Mike Frysinger <vapier@gentoo.org>
209
210 * microblaze-dis.c (get_field_special): Make op const.
211 (read_insn_microblaze): Make opr & op const. Rename opcodes to
212 microblaze_opcodes.
213 (print_insn_microblaze): Make op & pop const.
214 (get_insn_microblaze): Make op const. Rename opcodes to
215 microblaze_opcodes.
216 (microblaze_get_target_address): Likewise.
217 * microblaze-opc.h (struct op_code_struct): Make const.
218 Rename opcodes to microblaze_opcodes.
219
6c2ede01
MF		 2202021-07-01 Mike Frysinger <vapier@gentoo.org>
221
222 * aarch64-gen.c (aarch64_opcode_table): Add const.
223 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
224
46b8b3d6
AB		 2252021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
226
227 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
228 available.
229
ded5cb94
AM		 2302021-06-22 Alan Modra <amodra@gmail.com>
231
232 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
233 print separator for pcrel insns.
234
47399e9c
AM		 2352021-06-19 Alan Modra <amodra@gmail.com>
236
237 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
238
d984392e
AM		 2392021-06-19 Alan Modra <amodra@gmail.com>
240
241 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
242 entire buffer.
243
7993124e
AM		 2442021-06-17 Alan Modra <amodra@gmail.com>
245
246 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
247 in table.
248
a38d1396
AM		 2492021-06-03 Alan Modra <amodra@gmail.com>
250
251 PR 1202
252 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
253 Use unsigned int for inst.
254
8f467114
SV		 2552021-06-02 Shahab Vahedi <shahab@synopsys.com>
256
257 * arc-dis.c (arc_option_arg_t): New enumeration.
258 (arc_options): New variable.
259 (disassembler_options_arc): New function.
260 (print_arc_disassembler_options): Reimplement in terms of
261 "disassembler_options_arc".
262
1ff6a3b8
AM		 2632021-05-29 Alan Modra <amodra@gmail.com>
264
265 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
266 Don't special case PPC_OPCODE_RAW.
267 (lookup_prefix): Likewise.
268 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
269 (print_insn_powerpc): ..update caller.
270 * ppc-opc.c (EXT): Define.
271 (powerpc_opcodes): Mark extended mnemonics with EXT.
272 (prefix_opcodes, vle_opcodes): Likewise.
273 (XISEL, XISEL_MASK): Add cr field and simplify.
274 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
275 all isel variants to where the base mnemonic belongs. Sort dstt,
276 dststt and dssall.
277
49149d59
MR		 2782021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
279
280 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
281 COP3 opcode instructions.
282
9573a461
MR		 2832021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
284
285 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
286 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
287 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
288 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
289 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
290 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
291 "cop2", and "cop3" entries.
292
fa495743
MR		 2932021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
294
295 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
296 entries and associated comments.
297
b930964c
MR		 2982021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
299
300 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
301 of "c0".
302
dd844468
MR		 3032021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
304
305 * mips-dis.c (mips_cp1_names_mips): New variable.
306 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
307 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
308 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
309 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
310 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
311 "loongson2f".
312
9204ccd4
MR		 3132021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
314
315 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
316 handling code over to...
317 <OP_REG_CONTROL>: ... this new case.
318 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
319 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
320 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
321 replacing the `G' operand code with `g'. Update "cftc1" and
322 "cftc2" entries replacing the `E' operand code with `y'.
323 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
324 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
325 entries replacing the `G' operand code with `g'.
326
a3fb396f
MR		 3272021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
328
329 * mips-dis.c (mips_cp0_names_r3900): New variable.
330 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
331 for "r3900".
332
cccc84fa
MR		 3332021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
334
335 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
336 and "mtthc2" to using the `G' rather than `g' operand code for
337 the coprocessor control register referred.
338
c9de3168
MR		 3392021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
340
341 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
342 entries with each other.
343
ebcab741
PB		 3442021-05-27 Peter Bergner <bergner@linux.ibm.com>
345
346 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
347
bc30a119
AM		 3482021-05-25 Alan Modra <amodra@gmail.com>
349
350 * cris-desc.c: Regenerate.
351 * cris-desc.h: Regenerate.
352 * cris-opc.h: Regenerate.
353 * po/POTFILES.in: Regenerate.
354
54711280
MF		 3552021-05-24 Mike Frysinger <vapier@gentoo.org>
356
357 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
358 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
359 (CGEN_CPUS): Add cris.
360 (CRIS_DEPS): Define.
361 (stamp-cris): New rule.
362 * cgen.sh: Handle desc action.
363 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
364 * Makefile.in, configure: Regenerate.
365
113bb761
JN		 3662021-05-18 Job Noorman <mtvec@pm.me>
367
368 PR 27814
369 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
370 the elf objects.
371
e683cb41
AC		 3722021-05-17 Alex Coplan <alex.coplan@arm.com>
373
374 * arm-dis.c (mve_opcodes): Fix disassembly of
375 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
376 (is_mve_encoding_conflict): MVE vector loads should not match
377 when P = W = 0.
378 (is_mve_unpredictable): It's not unpredictable to use the same
379 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
380
a680affc
NC		 3812021-05-11 Nick Clifton <nickc@redhat.com>
382
383 PR 27840
384 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
385 the end of the code buffer.
386
0b3e14c9
SH		 3872021-05-06 Stafford Horne <shorne@gmail.com>
388
389 PR 21464
390 * or1k-asm.c: Regenerate.
391
6aee2cb2
MF		 3922021-05-01 Max Filippov <jcmvbkbc@gmail.com>
393
394 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
395 info->insn_info_valid.
396
fe134c65
JB		 3972021-04-26 Jan Beulich <jbeulich@suse.com>
398
399 * i386-opc.tbl (lea): Add Optimize.
400 * opcodes/i386-tbl.h: Re-generate.
401
b3ea7639
MF		 4022020-04-23 Max Filippov <jcmvbkbc@gmail.com>
403
404 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
405 of l32r fetch and display referenced literal value.
406
c1cbb7d8
MF		 4072021-04-23 Max Filippov <jcmvbkbc@gmail.com>
408
409 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
410 to 4 for literal disassembly.
411
02202574
PW		 4122021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
413
414 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
415 for TLBI instruction.
416
cd6608e4
PW		 4172021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
418
419 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
420 DC instruction.
421
fe1640ff
JB		 4222021-04-19 Jan Beulich <jbeulich@suse.com>
423
424 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
425 "qualifier".
426 (convert_mov_to_movewide): Add initializer for "value".
427
100e914d
PW		 4282021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
429
430 * aarch64-opc.c: Add RME system registers.
431
a21b96dd
NC		 4322021-04-16 Lifang Xia <lifang_xia@c-sky.com>
433
434 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
435 "addi d,CV,z" to "c.mv d,CV".
436
43e05cd4
AM		 4372021-04-12 Alan Modra <amodra@gmail.com>
438
439 * configure.ac (--enable-checking): Add support.
440 * config.in: Regenerate.
441 * configure: Regenerate.
442
52efda82
TB		 4432021-04-09 Tejas Belagod <tejas.belagod@arm.com>
444
445 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
446 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
447
c3f72de4
AM		 4482021-04-09 Alan Modra <amodra@gmail.com>
449
450 * ppc-dis.c (struct dis_private): Add "special".
451 (POWERPC_DIALECT): Delete. Replace uses with..
452 (private_data): ..this. New inline function.
453 (disassemble_init_powerpc): Init "special" names.
454 (skip_optional_operands): Add is_pcrel arg, set when detecting R
455 field of prefix instructions.
456 (bsearch_reloc, print_got_plt): New functions.
457 (print_insn_powerpc): For pcrel instructions, print target address
458 and symbol if known, and decode plt and got loads too.
459
ce7d813a
AM		 4602021-04-08 Alan Modra <amodra@gmail.com>
461
462 PR 27684
463 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
464
97bf40d8
AM		 4652021-04-08 Alan Modra <amodra@gmail.com>
466
467 PR 27676
468 * ppc-opc.c (DCBT_EO): Move earlier.
469 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
470 (powerpc_operands): Add THCT and THDS entries.
471 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
472
a2e66773
AM		 4732021-04-06 Alan Modra <amodra@gmail.com>
474
475 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
476 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
477 symbol_at_address_func.
478
ab2af25e
AM		 4792021-04-05 Alan Modra <amodra@gmail.com>
480
481 * configure.ac: Don't check for limits.h, string.h, strings.h or
482 stdlib.h.
483 (AC_ISC_POSIX): Don't invoke.
484 * sysdep.h: Include stdlib.h and string.h unconditionally.
485 * i386-opc.h: Include limits.h unconditionally.
486 * wasm32-dis.c: Likewise.
487 * cgen-opc.c: Don't include alloca-conf.h.
488 * config.in: Regenerate.
489 * configure: Regenerate.
490
e9b095a5
ML		 4912021-04-01 Martin Liska <mliska@suse.cz>
492
493 * arm-dis.c (strneq): Remove strneq and use startswith.
494 * cr16-dis.c (print_insn_cr16): Likewise.
495 * score-dis.c (streq): Likewise.
496 (strneq): Likewise.
497 * score7-dis.c (strneq): Likewise.
498
1cb108e4
AM		 4992021-04-01 Alan Modra <amodra@gmail.com>
500
501 PR 27675
502 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
503
78933a4a
AM		 5042021-03-31 Alan Modra <amodra@gmail.com>
505
506 * sysdep.h (POISON_BFD_BOOLEAN): Define.
507 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
508 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
509 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
510 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
511 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
512 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
513 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
514 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
515 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
516 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
517 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
518 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
519 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
520 and TRUE with true throughout.
521
3dfb1b6d
AM		 5222021-03-31 Alan Modra <amodra@gmail.com>
523
524 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
525 * aarch64-dis.h: Likewise.
526 * aarch64-opc.c: Likewise.
527 * avr-dis.c: Likewise.
528 * csky-dis.c: Likewise.
529 * nds32-asm.c: Likewise.
530 * nds32-dis.c: Likewise.
531 * nfp-dis.c: Likewise.
532 * riscv-dis.c: Likewise.
533 * s12z-dis.c: Likewise.
534 * wasm32-dis.c: Likewise.
535
5e042380
JB		 5362021-03-30 Jan Beulich <jbeulich@suse.com>
537
538 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
539 (i386_seg_prefixes): New.
540 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
541 (i386_seg_prefixes): Declare.
542
34684862
JB		 5432021-03-30 Jan Beulich <jbeulich@suse.com>
544
545 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
546
6288d05f
JB		 5472021-03-30 Jan Beulich <jbeulich@suse.com>
548
549 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
550 * i386-reg.tbl (st): Move down.
551 (st(0)): Delete. Extend comment.
552 * i386-tbl.h: Re-generate.
553
bbe1eca6
JB		 5542021-03-29 Jan Beulich <jbeulich@suse.com>
555
556 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
557 (cmpsd): Move next to cmps.
558 (movsd): Move next to movs.
559 (cmpxchg16b): Move to separate section.
560 (fisttp, fisttpll): Likewise.
561 (monitor, mwait): Likewise.
562 * i386-tbl.h: Re-generate.
563
c8cad9d3
JB		 5642021-03-29 Jan Beulich <jbeulich@suse.com>
565
566 * i386-opc.tbl (psadbw): Add <sse2:comm>.
567 (vpsadbw): Add C.
568 * i386-tbl.h: Re-generate.
569
5cdaf100
JB		 5702021-03-29 Jan Beulich <jbeulich@suse.com>
571
572 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
573 pclmul, gfni): New templates. Use them wherever possible. Move
574 SSE4.1 pextrw into respective section.
575 * i386-tbl.h: Re-generate.
576
73e45eb2
JB		 5772021-03-29 Jan Beulich <jbeulich@suse.com>
578
579 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
580 strtoull(). Bump upper loop bound. Widen masks. Sanity check
581 "length".
582 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
583 Convert all of their uses to representation in opcode.
584
9df6f676
JB		 5852021-03-29 Jan Beulich <jbeulich@suse.com>
586
587 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
588 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
589 value of None. Shrink operands to 3 bits.
590
389d00a5
JB		 5912021-03-29 Jan Beulich <jbeulich@suse.com>
592
593 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 594 "space".
389d00a5
JB		 595 (output_i386_opcode): New local variable "space". Adjust
596 process_i386_opcode_modifier() invocation.
597 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
598 invocation.
599 * i386-tbl.h: Re-generate.
600
63b4cc53
AM		 6012021-03-29 Alan Modra <amodra@gmail.com>
602
603 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
604 (fp_qualifier_p, get_data_pattern): Likewise.
605 (aarch64_get_operand_modifier_from_value): Likewise.
606 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
607 (operand_variant_qualifier_p): Likewise.
608 (qualifier_value_in_range_constraint_p): Likewise.
609 (aarch64_get_qualifier_esize): Likewise.
610 (aarch64_get_qualifier_nelem): Likewise.
611 (aarch64_get_qualifier_standard_value): Likewise.
612 (get_lower_bound, get_upper_bound): Likewise.
613 (aarch64_find_best_match, match_operands_qualifier): Likewise.
614 (aarch64_print_operand): Likewise.
615 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
616 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
617 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
618 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
619 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
620 (print_insn_tic6x): Likewise.
621
3d7d6c1b
AM		 6222021-03-29 Alan Modra <amodra@gmail.com>
623
624 * arc-dis.c (extract_operand_value): Correct NULL cast.
625 * frv-opc.h: Regenerate.
626
c3344b62
JB		 6272021-03-26 Jan Beulich <jbeulich@suse.com>
628
629 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
630 MMX form.
631 * i386-tbl.h: Re-generate.
632
efa30ac3
HAQ		 6332021-03-25 Abid Qadeer <abidh@codesourcery.com>
634
635 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
636 immediate in br.n instruction.
637
596a02ff
JB		 6382021-03-25 Jan Beulich <jbeulich@suse.com>
639
640 * i386-dis.c (XMGatherD, VexGatherD): New.
641 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
642 (print_insn): Check masking for S/G insns.
643 (OP_E_memory): New local variable check_gather. Extend mandatory
644 SIB check. Check register conflicts for (EVEX-encoded) gathers.
645 Extend check for disallowed 16-bit addressing.
646 (OP_VEX): New local variables modrm_reg and sib_index. Convert
647 if()s to switch(). Check register conflicts for (VEX-encoded)
648 gathers. Drop no longer reachable cases.
649 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
650 vgatherdp*.
651
53642852
JB		 6522021-03-25 Jan Beulich <jbeulich@suse.com>
653
654 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
655 zeroing-masking without masking.
656
c0e54661
JB		 6572021-03-25 Jan Beulich <jbeulich@suse.com>
658
659 * i386-opc.tbl (invlpgb): Fix multi-operand form.
660 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
661 single-operand forms as deprecated.
662 * i386-tbl.h: Re-generate.
663
5a403766
AM		 6642021-03-25 Alan Modra <amodra@gmail.com>
665
666 PR 27647
667 * ppc-opc.c (XLOCB_MASK): Delete.
668 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
669 XLBH_MASK.
670 (powerpc_opcodes): Accept a BH field on all extended forms of
671 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
672
9a182d04
JB		 6732021-03-24 Jan Beulich <jbeulich@suse.com>
674
675 * i386-gen.c (output_i386_opcode): Drop processing of
676 opcode_length. Calculate length from base_opcode. Adjust prefix
677 encoding determination.
678 (process_i386_opcodes): Drop output of fake opcode_length.
679 * i386-opc.h (struct insn_template): Drop opcode_length field.
680 * i386-opc.tbl: Drop opcode length field from all templates.
681 * i386-tbl.h: Re-generate.
682
35648716
JB		 6832021-03-24 Jan Beulich <jbeulich@suse.com>
684
685 * i386-gen.c (process_i386_opcode_modifier): Return void. New
686 parameter "prefix". Drop local variable "regular_encoding".
687 Record prefix setting / check for consistency.
688 (output_i386_opcode): Parse opcode_length and base_opcode
689 earlier. Derive prefix encoding. Drop no longer applicable
690 consistency checking. Adjust process_i386_opcode_modifier()
691 invocation.
692 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
693 invocation.
694 * i386-tbl.h: Re-generate.
695
31184569
JB		 6962021-03-24 Jan Beulich <jbeulich@suse.com>
697
698 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
699 check.
700 * i386-opc.h (Prefix_*): Move #define-s.
701 * i386-opc.tbl: Move pseudo prefix enumerator values to
702 extension opcode field. Introduce pseudopfx template.
703 * i386-tbl.h: Re-generate.
704
b933fa4b
JB		 7052021-03-23 Jan Beulich <jbeulich@suse.com>
706
707 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
708 comment.
709 * i386-tbl.h: Re-generate.
710
dac10fb0
JB		 7112021-03-23 Jan Beulich <jbeulich@suse.com>
712
713 * i386-opc.h (struct insn_template): Move cpu_flags field past
714 opcode_modifier one.
715 * i386-tbl.h: Re-generate.
716
441f6aca
JB		 7172021-03-23 Jan Beulich <jbeulich@suse.com>
718
719 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
720 * i386-opc.h (OpcodeSpace): New enumerator.
721 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
722 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
723 SPACE_XOP09, SPACE_XOP0A): ... respectively.
724 (struct i386_opcode_modifier): New field opcodespace. Shrink
725 opcodeprefix field.
726 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
727 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
728 OpcodePrefix uses.
729 * i386-tbl.h: Re-generate.
730
08dedd66
ML		 7312021-03-22 Martin Liska <mliska@suse.cz>
732
733 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
734 * arc-dis.c (parse_option): Likewise.
735 * arm-dis.c (parse_arm_disassembler_options): Likewise.
736 * cris-dis.c (print_with_operands): Likewise.
737 * h8300-dis.c (bfd_h8_disassemble): Likewise.
738 * i386-dis.c (print_insn): Likewise.
739 * ia64-gen.c (fetch_insn_class): Likewise.
740 (parse_resource_users): Likewise.
741 (in_iclass): Likewise.
742 (lookup_specifier): Likewise.
743 (insert_opcode_dependencies): Likewise.
744 * mips-dis.c (parse_mips_ase_option): Likewise.
745 (parse_mips_dis_option): Likewise.
746 * s390-dis.c (disassemble_init_s390): Likewise.
747 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
748
80d49d6a
KLC		 7492021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
750
751 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
752
7fce7ea9
PW		 7532021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
754
755 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
756 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
757
78c84bf9
AM		 7582021-03-12 Alan Modra <amodra@gmail.com>
759
760 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
761
fd1fd061
JB		 7622021-03-11 Jan Beulich <jbeulich@suse.com>
763
764 * i386-dis.c (OP_XMM): Re-order checks.
765
ac7a2311
JB		 7662021-03-11 Jan Beulich <jbeulich@suse.com>
767
768 * i386-dis.c (putop): Drop need_vex check when also checking
769 vex.evex.
770 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
771 checking vex.b.
772
da944c8a
JB		 7732021-03-11 Jan Beulich <jbeulich@suse.com>
774
775 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
776 checks. Move case label past broadcast check.
777
b763d508
JB		 7782021-03-10 Jan Beulich <jbeulich@suse.com>
779
780 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
781 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
782 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
783 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
784 EVEX_W_0F38C7_M_0_L_2): Delete.
785 (REG_EVEX_0F38C7_M_0_L_2): New.
786 (intel_operand_size): Handle VEX and EVEX the same for
787 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
788 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
789 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
790 vex_vsib_q_w_d_mode uses.
791 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
792 0F38A1, and 0F38A3 entries.
793 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
794 entry.
795 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
796 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
797 0F38A3 entries.
798
32e31ad7
JB		 7992021-03-10 Jan Beulich <jbeulich@suse.com>
800
801 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
802 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
803 MOD_VEX_0FXOP_09_12): Rename to ...
804 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
805 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
806 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
807 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
808 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
809 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
810 (reg_table): Adjust comments.
811 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
812 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
813 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
814 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
815 (vex_len_table): Adjust opcode 0A_12 entry.
816 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
817 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
818 (rm_table): Move hreset entry.
819
85ba7507
JB		 8202021-03-10 Jan Beulich <jbeulich@suse.com>
821
822 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
823 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
824 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
825 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
826 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
827 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
828 (get_valid_dis386): Also handle 512-bit vector length when
829 vectoring into vex_len_table[].
830 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
831 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
832 entries.
833 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
834 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
835 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
836 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
837 entries.
838
066f82b9
JB		 8392021-03-10 Jan Beulich <jbeulich@suse.com>
840
841 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
842 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
843 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
844 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
845 entries.
846 * i386-dis-evex-len.h (evex_len_table): Likewise.
847 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
848
fc681dd6
JB		 8492021-03-10 Jan Beulich <jbeulich@suse.com>
850
851 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
852 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
853 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
854 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
855 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
856 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
857 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
858 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
859 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
860 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
861 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
862 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
863 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
864 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
865 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
866 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
867 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
868 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
869 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
870 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
871 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
872 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
873 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
874 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
875 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
876 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
877 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
878 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
879 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
880 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
881 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
882 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
883 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
884 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
885 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
886 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
887 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
888 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
889 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
890 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
891 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
892 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
893 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
894 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
895 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
896 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
897 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
898 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
899 EVEX_W_0F3A43_L_n): New.
900 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
901 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
902 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
903 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
904 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
905 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
906 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
907 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
908 0F385B, 0F38C6, and 0F38C7 entries.
909 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
910 0F38C6 and 0F38C7.
911 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
912 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
913 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
914 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
915
13954a31
JB		 9162021-03-10 Jan Beulich <jbeulich@suse.com>
917
918 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
919 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
920 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
921 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
922 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
923 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
924 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
925 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
926 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
927 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
928 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
929 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
930 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
931 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
932 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
933 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
934 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
935 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
936 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
937 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
938 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
939 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
940 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
941 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
942 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
943 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
944 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
945 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
946 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
947 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
948 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
949 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
950 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
951 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
952 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
953 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
954 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
955 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
956 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
957 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
958 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
959 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
960 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
961 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
962 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
963 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
964 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
965 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
966 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
967 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
968 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
969 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
970 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
971 VEX_W_0F99_P_2_LEN_0): Delete.
972 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
973 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
974 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
975 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
976 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
977 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
978 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
979 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
980 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
981 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
982 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
983 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
984 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
985 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
986 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
987 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
988 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
989 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
990 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
991 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
992 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
993 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
994 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
995 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
996 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
997 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
998 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
999 (prefix_table): No longer link to vex_len_table[] for opcodes
1000 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1001 0F92, 0F93, 0F98, and 0F99.
1002 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1003 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1004 0F98, and 0F99.
1005 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1006 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1007 0F98, and 0F99.
1008 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1009 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1010 0F98, and 0F99.
1011 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1012 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1013 0F98, and 0F99.
1014
14d10c6c
JB		 10152021-03-10 Jan Beulich <jbeulich@suse.com>
1016
1017 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1018 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1019 REG_VEX_0F73_M_0 respectively.
1020 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1021 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1022 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1023 MOD_VEX_0F73_REG_7): Delete.
1024 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1025 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1026 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1027 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1028 PREFIX_VEX_0F3AF0_L_0 respectively.
1029 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1030 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1031 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1032 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1033 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1034 VEX_LEN_0F38F7): New.
1035 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1036 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1037 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1038 0F38F3.
1039 (prefix_table): No longer link to vex_len_table[] for opcodes
1040 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1041 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1042 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1043 0F38F6, 0F38F7, and 0F3AF0.
1044 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1045 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1046 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1047 0F73.
1048
00ec1875
JB		 10492021-03-10 Jan Beulich <jbeulich@suse.com>
1050
1051 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1052 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1053 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1054 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1055 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1056 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1057 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1058 73.
1059 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1060 0F72, and 0F73.
1061 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1062 0F73.
1063
31941983
JB		 10642021-03-10 Jan Beulich <jbeulich@suse.com>
1065
1066 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1067 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1068 (reg_table): Don't link to mod_table[] where not needed. Add
1069 PREFIX_IGNORED to nop entries.
1070 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1071 (mod_table): Add nop entries next to prefetch ones. Drop
1072 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1073 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1074 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1075 PREFIX_OPCODE from endbr* entries.
1076 (get_valid_dis386): Also consider entry's name when zapping
1077 vindex.
1078 (print_insn): Handle PREFIX_IGNORED.
1079
742732c7
JB		 10802021-03-09 Jan Beulich <jbeulich@suse.com>
1081
1082 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1083 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1084 element.
1085 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1086 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1087 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1088 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1089 (struct i386_opcode_modifier): Delete notrackprefixok,
1090 islockable, hleprefixok, and repprefixok fields. Add prefixok
1091 field.
1092 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1093 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1094 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1095 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1096 Replace HLEPrefixOk.
1097 * opcodes/i386-tbl.h: Re-generate.
1098
e93a3b27
JB		 10992021-03-09 Jan Beulich <jbeulich@suse.com>
1100
1101 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1102 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1103 64-bit form.
1104 * opcodes/i386-tbl.h: Re-generate.
1105
75363b6d
JB		 11062021-03-03 Jan Beulich <jbeulich@suse.com>
1107
1108 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1109 for {} instead of {0}. Don't look for '0'.
1110 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1111 size specifiers.
1112
5a9f5403
NC		 11132021-02-19 Nelson Chu <nelson.chu@sifive.com>
1114
1115 PR 27158
1116 * riscv-dis.c (print_insn_args): Updated encoding macros.
1117 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1118 (match_c_addi16sp): Updated encoding macros.
1119 (match_c_lui): Likewise.
1120 (match_c_lui_with_hint): Likewise.
1121 (match_c_addi4spn): Likewise.
1122 (match_c_slli): Likewise.
1123 (match_slli_as_c_slli): Likewise.
1124 (match_c_slli64): Likewise.
1125 (match_srxi_as_c_srxi): Likewise.
1126 (riscv_insn_types): Added .insn css/cl/cs.
1127
3d73d29e
NC		 11282021-02-18 Nelson Chu <nelson.chu@sifive.com>
1129
1130 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1131 (default_priv_spec): Updated type to riscv_spec_class.
1132 (parse_riscv_dis_option): Updated.
1133 * riscv-opc.c: Moved stuff and make the file tidy.
1134
b9b204b3
AM		 11352021-02-17 Alan Modra <amodra@gmail.com>
1136
1137 * wasm32-dis.c: Include limits.h.
1138 (CHAR_BIT): Provide backup define.
1139 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1140 Correct signed overflow checking.
1141
394ae71f
JB		 11422021-02-16 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1145 * i386-tbl.h: Re-generate.
1146
b818b220
JB		 11472021-02-16 Jan Beulich <jbeulich@suse.com>
1148
1149 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1150 Oword.
1151 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1152
ba2b480f
AK		 11532021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1154
1155 * s390-mkopc.c (main): Accept arch14 as cpu string.
1156 * s390-opc.txt: Add new arch14 instructions.
1157
95148614
NA		 11582021-02-04 Nick Alcock <nick.alcock@oracle.com>
1159
1160 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1161 favour of LIBINTL.
1162 * configure: Regenerated.
1163
bfd428bc
MF		 11642021-02-08 Mike Frysinger <vapier@gentoo.org>
1165
1166 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1167 * tic54x-opc.c (regs): Rename to ...
1168 (tic54x_regs): ... this.
1169 (mmregs): Rename to ...
1170 (tic54x_mmregs): ... this.
1171 (condition_codes): Rename to ...
1172 (tic54x_condition_codes): ... this.
1173 (cc2_codes): Rename to ...
1174 (tic54x_cc2_codes): ... this.
1175 (cc3_codes): Rename to ...
1176 (tic54x_cc3_codes): ... this.
1177 (status_bits): Rename to ...
1178 (tic54x_status_bits): ... this.
1179 (misc_symbols): Rename to ...
1180 (tic54x_misc_symbols): ... this.
1181
24075dcc
NC		 11822021-02-04 Nelson Chu <nelson.chu@sifive.com>
1183
1184 * riscv-opc.c (MASK_RVB_IMM): Removed.
1185 (riscv_opcodes): Removed zb* instructions.
1186 (riscv_ext_version_table): Removed versions for zb*.
1187
c3ffb8f3
AM		 11882021-01-26 Alan Modra <amodra@gmail.com>
1189
1190 * i386-gen.c (parse_template): Ensure entire template_instance
1191 is initialised.
1192
1942a048
NC		 11932021-01-15 Nelson Chu <nelson.chu@sifive.com>
1194
1195 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1196 (riscv_fpr_names_abi): Likewise.
1197 (riscv_opcodes): Likewise.
1198 (riscv_insn_types): Likewise.
1199
b800637e
NC		 12002021-01-15 Nelson Chu <nelson.chu@sifive.com>
1201
1202 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1203
dcd709e0
NC		 12042021-01-15 Nelson Chu <nelson.chu@sifive.com>
1205
1206 * riscv-dis.c: Comments tidy and improvement.
1207 * riscv-opc.c: Likewise.
1208
5347ed60
AM		 12092021-01-13 Alan Modra <amodra@gmail.com>
1210
1211 * Makefile.in: Regenerate.
1212
d546b610
L		 12132021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1214
1215 PR binutils/26792
1216 * configure.ac: Use GNU_MAKE_JOBSERVER.
1217 * aclocal.m4: Regenerated.
1218 * configure: Likewise.
1219
6d104cac
NC		 12202021-01-12 Nick Clifton <nickc@redhat.com>
1221
1222 * po/sr.po: Updated Serbian translation.
1223
83b33c6c
L		 12242021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1225
1226 PR ld/27173
1227 * configure: Regenerated.
1228
82c70b08
KT		 12292021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1230
1231 * aarch64-asm-2.c: Regenerate.
1232 * aarch64-dis-2.c: Likewise.
1233 * aarch64-opc-2.c: Likewise.
1234 * aarch64-opc.c (aarch64_print_operand):
1235 Delete handling of AARCH64_OPND_CSRE_CSR.
1236 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1237 (CSRE): Likewise.
1238 (_CSRE_INSN): Likewise.
1239 (aarch64_opcode_table): Delete csr.
1240
a8aa72b9
NC		 12412021-01-11 Nick Clifton <nickc@redhat.com>
1242
1243 * po/de.po: Updated German translation.
1244 * po/fr.po: Updated French translation.
1245 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1246 * po/sv.po: Updated Swedish translation.
1247 * po/uk.po: Updated Ukranian translation.
1248
a4966cd9
L		 12492021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1250
1251 * configure: Regenerated.
1252
573fe3fb
NC		 12532021-01-09 Nick Clifton <nickc@redhat.com>
1254
1255 * configure: Regenerate.
1256 * po/opcodes.pot: Regenerate.
1257
055bc77a
NC		 12582021-01-09 Nick Clifton <nickc@redhat.com>
1259
1260 * 2.36 release branch crated.
1261
aae7fcb8
PB		 12622021-01-08 Peter Bergner <bergner@linux.ibm.com>
1263
1264 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1265 (DW, (XRC_MASK): Define.
1266 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1267
64307045
AM		 12682021-01-09 Alan Modra <amodra@gmail.com>
1269
1270 * configure: Regenerate.
1271
ed205222
NC		 12722021-01-08 Nick Clifton <nickc@redhat.com>
1273
1274 * po/sv.po: Updated Swedish translation.
1275
fb932b57
NC		 12762021-01-08 Nick Clifton <nickc@redhat.com>
1277
e84c8716
NC		 1278 PR 27129
1279 * aarch64-dis.c (determine_disassembling_preference): Move call to
1280 aarch64_match_operands_constraint outside of the assertion.
1281 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1282 Replace with a return of FALSE.
1283
fb932b57
NC		 1284 PR 27139
1285 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1286 core system register.
1287
f4782128
ST		 12882021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1289
1290 * configure: Regenerate.
1291
1b0927db
NC		 12922021-01-07 Nick Clifton <nickc@redhat.com>
1293
1294 * po/fr.po: Updated French translation.
1295
3b288c8e
FN		 12962021-01-07 Fredrik Noring <noring@nocrew.org>
1297
1298 * m68k-opc.c (chkl): Change minimum architecture requirement to
1299 m68020.
1300
aa881ecd
PT		 13012021-01-07 Philipp Tomsich <prt@gnu.org>
1302
1303 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1304
2652cfad
CXW		 13052021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1306 Jim Wilson <jimw@sifive.com>
1307 Andrew Waterman <andrew@sifive.com>
1308 Maxim Blinov <maxim.blinov@embecosm.com>
1309 Kito Cheng <kito.cheng@sifive.com>
1310 Nelson Chu <nelson.chu@sifive.com>
1311
1312 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1313 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1314
250d07de
AM		 13152021-01-01 Alan Modra <amodra@gmail.com>
1316
1317 Update year range in copyright notice of all files.
1318
c2795844 1319For older changes see ChangeLog-2020
3499769a 1320\f
a2c58332 1321Copyright (C) 2021-2022 Free Software Foundation, Inc.
3499769a
AM		 1322
1323Copying and distribution of this file, with or without modification,
1324are permitted in any medium without royalty provided the copyright
1325notice and this notice are preserved.
1326
1327Local Variables:
1328mode: change-log
1329left-margin: 8
1330fill-column: 74
1331version-control: never
1332End:
A mirror of the official binutils-gdb repository