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sim: unify hardware settings
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
47399e9c
AM		 12021-06-19 Alan Modra <amodra@gmail.com>
2
3 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
4
d984392e
AM		 52021-06-19 Alan Modra <amodra@gmail.com>
6
7 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
8 entire buffer.
9
7993124e
AM		 102021-06-17 Alan Modra <amodra@gmail.com>
11
12 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
13 in table.
14
a38d1396
AM		 152021-06-03 Alan Modra <amodra@gmail.com>
16
17 PR 1202
18 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
19 Use unsigned int for inst.
20
8f467114
SV		 212021-06-02 Shahab Vahedi <shahab@synopsys.com>
22
23 * arc-dis.c (arc_option_arg_t): New enumeration.
24 (arc_options): New variable.
25 (disassembler_options_arc): New function.
26 (print_arc_disassembler_options): Reimplement in terms of
27 "disassembler_options_arc".
28
1ff6a3b8
AM		 292021-05-29 Alan Modra <amodra@gmail.com>
30
31 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
32 Don't special case PPC_OPCODE_RAW.
33 (lookup_prefix): Likewise.
34 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
35 (print_insn_powerpc): ..update caller.
36 * ppc-opc.c (EXT): Define.
37 (powerpc_opcodes): Mark extended mnemonics with EXT.
38 (prefix_opcodes, vle_opcodes): Likewise.
39 (XISEL, XISEL_MASK): Add cr field and simplify.
40 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
41 all isel variants to where the base mnemonic belongs. Sort dstt,
42 dststt and dssall.
43
49149d59
MR		 442021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
45
46 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
47 COP3 opcode instructions.
48
9573a461
MR		 492021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
50
51 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
52 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
53 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
54 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
55 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
56 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
57 "cop2", and "cop3" entries.
58
fa495743
MR		 592021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
60
61 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
62 entries and associated comments.
63
b930964c
MR		 642021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
65
66 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
67 of "c0".
68
dd844468
MR		 692021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
70
71 * mips-dis.c (mips_cp1_names_mips): New variable.
72 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
73 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
74 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
75 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
76 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
77 "loongson2f".
78
9204ccd4
MR		 792021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
80
81 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
82 handling code over to...
83 <OP_REG_CONTROL>: ... this new case.
84 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
85 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
86 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
87 replacing the `G' operand code with `g'. Update "cftc1" and
88 "cftc2" entries replacing the `E' operand code with `y'.
89 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
90 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
91 entries replacing the `G' operand code with `g'.
92
a3fb396f
MR		 932021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
94
95 * mips-dis.c (mips_cp0_names_r3900): New variable.
96 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
97 for "r3900".
98
cccc84fa
MR		 992021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
100
101 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
102 and "mtthc2" to using the `G' rather than `g' operand code for
103 the coprocessor control register referred.
104
c9de3168
MR		 1052021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
106
107 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
108 entries with each other.
109
ebcab741
PB		 1102021-05-27 Peter Bergner <bergner@linux.ibm.com>
111
112 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
113
bc30a119
AM		 1142021-05-25 Alan Modra <amodra@gmail.com>
115
116 * cris-desc.c: Regenerate.
117 * cris-desc.h: Regenerate.
118 * cris-opc.h: Regenerate.
119 * po/POTFILES.in: Regenerate.
120
54711280
MF		 1212021-05-24 Mike Frysinger <vapier@gentoo.org>
122
123 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
124 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
125 (CGEN_CPUS): Add cris.
126 (CRIS_DEPS): Define.
127 (stamp-cris): New rule.
128 * cgen.sh: Handle desc action.
129 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
130 * Makefile.in, configure: Regenerate.
131
113bb761
JN		 1322021-05-18 Job Noorman <mtvec@pm.me>
133
134 PR 27814
135 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
136 the elf objects.
137
e683cb41
AC		 1382021-05-17 Alex Coplan <alex.coplan@arm.com>
139
140 * arm-dis.c (mve_opcodes): Fix disassembly of
141 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
142 (is_mve_encoding_conflict): MVE vector loads should not match
143 when P = W = 0.
144 (is_mve_unpredictable): It's not unpredictable to use the same
145 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
146
a680affc
NC		 1472021-05-11 Nick Clifton <nickc@redhat.com>
148
149 PR 27840
150 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
151 the end of the code buffer.
152
0b3e14c9
SH		 1532021-05-06 Stafford Horne <shorne@gmail.com>
154
155 PR 21464
156 * or1k-asm.c: Regenerate.
157
6aee2cb2
MF		 1582021-05-01 Max Filippov <jcmvbkbc@gmail.com>
159
160 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
161 info->insn_info_valid.
162
fe134c65
JB		 1632021-04-26 Jan Beulich <jbeulich@suse.com>
164
165 * i386-opc.tbl (lea): Add Optimize.
166 * opcodes/i386-tbl.h: Re-generate.
167
b3ea7639
MF		 1682020-04-23 Max Filippov <jcmvbkbc@gmail.com>
169
170 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
171 of l32r fetch and display referenced literal value.
172
c1cbb7d8
MF		 1732021-04-23 Max Filippov <jcmvbkbc@gmail.com>
174
175 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
176 to 4 for literal disassembly.
177
02202574
PW		 1782021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
179
180 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
181 for TLBI instruction.
182
cd6608e4
PW		 1832021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
184
185 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
186 DC instruction.
187
fe1640ff
JB		 1882021-04-19 Jan Beulich <jbeulich@suse.com>
189
190 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
191 "qualifier".
192 (convert_mov_to_movewide): Add initializer for "value".
193
100e914d
PW		 1942021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
195
196 * aarch64-opc.c: Add RME system registers.
197
a21b96dd
NC		 1982021-04-16 Lifang Xia <lifang_xia@c-sky.com>
199
200 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
201 "addi d,CV,z" to "c.mv d,CV".
202
43e05cd4
AM		 2032021-04-12 Alan Modra <amodra@gmail.com>
204
205 * configure.ac (--enable-checking): Add support.
206 * config.in: Regenerate.
207 * configure: Regenerate.
208
52efda82
TB		 2092021-04-09 Tejas Belagod <tejas.belagod@arm.com>
210
211 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
212 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
213
c3f72de4
AM		 2142021-04-09 Alan Modra <amodra@gmail.com>
215
216 * ppc-dis.c (struct dis_private): Add "special".
217 (POWERPC_DIALECT): Delete. Replace uses with..
218 (private_data): ..this. New inline function.
219 (disassemble_init_powerpc): Init "special" names.
220 (skip_optional_operands): Add is_pcrel arg, set when detecting R
221 field of prefix instructions.
222 (bsearch_reloc, print_got_plt): New functions.
223 (print_insn_powerpc): For pcrel instructions, print target address
224 and symbol if known, and decode plt and got loads too.
225
ce7d813a
AM		 2262021-04-08 Alan Modra <amodra@gmail.com>
227
228 PR 27684
229 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
230
97bf40d8
AM		 2312021-04-08 Alan Modra <amodra@gmail.com>
232
233 PR 27676
234 * ppc-opc.c (DCBT_EO): Move earlier.
235 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
236 (powerpc_operands): Add THCT and THDS entries.
237 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
238
a2e66773
AM		 2392021-04-06 Alan Modra <amodra@gmail.com>
240
241 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
242 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
243 symbol_at_address_func.
244
ab2af25e
AM		 2452021-04-05 Alan Modra <amodra@gmail.com>
246
247 * configure.ac: Don't check for limits.h, string.h, strings.h or
248 stdlib.h.
249 (AC_ISC_POSIX): Don't invoke.
250 * sysdep.h: Include stdlib.h and string.h unconditionally.
251 * i386-opc.h: Include limits.h unconditionally.
252 * wasm32-dis.c: Likewise.
253 * cgen-opc.c: Don't include alloca-conf.h.
254 * config.in: Regenerate.
255 * configure: Regenerate.
256
e9b095a5
ML		 2572021-04-01 Martin Liska <mliska@suse.cz>
258
259 * arm-dis.c (strneq): Remove strneq and use startswith.
260 * cr16-dis.c (print_insn_cr16): Likewise.
261 * score-dis.c (streq): Likewise.
262 (strneq): Likewise.
263 * score7-dis.c (strneq): Likewise.
264
1cb108e4
AM		 2652021-04-01 Alan Modra <amodra@gmail.com>
266
267 PR 27675
268 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
269
78933a4a
AM		 2702021-03-31 Alan Modra <amodra@gmail.com>
271
272 * sysdep.h (POISON_BFD_BOOLEAN): Define.
273 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
274 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
275 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
276 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
277 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
278 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
279 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
280 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
281 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
282 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
283 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
284 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
285 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
286 and TRUE with true throughout.
287
3dfb1b6d
AM		 2882021-03-31 Alan Modra <amodra@gmail.com>
289
290 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
291 * aarch64-dis.h: Likewise.
292 * aarch64-opc.c: Likewise.
293 * avr-dis.c: Likewise.
294 * csky-dis.c: Likewise.
295 * nds32-asm.c: Likewise.
296 * nds32-dis.c: Likewise.
297 * nfp-dis.c: Likewise.
298 * riscv-dis.c: Likewise.
299 * s12z-dis.c: Likewise.
300 * wasm32-dis.c: Likewise.
301
5e042380
JB		 3022021-03-30 Jan Beulich <jbeulich@suse.com>
303
304 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
305 (i386_seg_prefixes): New.
306 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
307 (i386_seg_prefixes): Declare.
308
34684862
JB		 3092021-03-30 Jan Beulich <jbeulich@suse.com>
310
311 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
312
6288d05f
JB		 3132021-03-30 Jan Beulich <jbeulich@suse.com>
314
315 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
316 * i386-reg.tbl (st): Move down.
317 (st(0)): Delete. Extend comment.
318 * i386-tbl.h: Re-generate.
319
bbe1eca6
JB		 3202021-03-29 Jan Beulich <jbeulich@suse.com>
321
322 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
323 (cmpsd): Move next to cmps.
324 (movsd): Move next to movs.
325 (cmpxchg16b): Move to separate section.
326 (fisttp, fisttpll): Likewise.
327 (monitor, mwait): Likewise.
328 * i386-tbl.h: Re-generate.
329
c8cad9d3
JB		 3302021-03-29 Jan Beulich <jbeulich@suse.com>
331
332 * i386-opc.tbl (psadbw): Add <sse2:comm>.
333 (vpsadbw): Add C.
334 * i386-tbl.h: Re-generate.
335
5cdaf100
JB		 3362021-03-29 Jan Beulich <jbeulich@suse.com>
337
338 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
339 pclmul, gfni): New templates. Use them wherever possible. Move
340 SSE4.1 pextrw into respective section.
341 * i386-tbl.h: Re-generate.
342
73e45eb2
JB		 3432021-03-29 Jan Beulich <jbeulich@suse.com>
344
345 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
346 strtoull(). Bump upper loop bound. Widen masks. Sanity check
347 "length".
348 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
349 Convert all of their uses to representation in opcode.
350
9df6f676
JB		 3512021-03-29 Jan Beulich <jbeulich@suse.com>
352
353 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
354 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
355 value of None. Shrink operands to 3 bits.
356
389d00a5
JB		 3572021-03-29 Jan Beulich <jbeulich@suse.com>
358
359 * i386-gen.c (process_i386_opcode_modifier): New parameter
360 "space".
361 (output_i386_opcode): New local variable "space". Adjust
362 process_i386_opcode_modifier() invocation.
363 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
364 invocation.
365 * i386-tbl.h: Re-generate.
366
63b4cc53
AM		 3672021-03-29 Alan Modra <amodra@gmail.com>
368
369 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
370 (fp_qualifier_p, get_data_pattern): Likewise.
371 (aarch64_get_operand_modifier_from_value): Likewise.
372 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
373 (operand_variant_qualifier_p): Likewise.
374 (qualifier_value_in_range_constraint_p): Likewise.
375 (aarch64_get_qualifier_esize): Likewise.
376 (aarch64_get_qualifier_nelem): Likewise.
377 (aarch64_get_qualifier_standard_value): Likewise.
378 (get_lower_bound, get_upper_bound): Likewise.
379 (aarch64_find_best_match, match_operands_qualifier): Likewise.
380 (aarch64_print_operand): Likewise.
381 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
382 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
383 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
384 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
385 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
386 (print_insn_tic6x): Likewise.
387
3d7d6c1b
AM		 3882021-03-29 Alan Modra <amodra@gmail.com>
389
390 * arc-dis.c (extract_operand_value): Correct NULL cast.
391 * frv-opc.h: Regenerate.
392
c3344b62
JB		 3932021-03-26 Jan Beulich <jbeulich@suse.com>
394
395 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
396 MMX form.
397 * i386-tbl.h: Re-generate.
398
efa30ac3
HAQ		 3992021-03-25 Abid Qadeer <abidh@codesourcery.com>
400
401 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
402 immediate in br.n instruction.
403
596a02ff
JB		 4042021-03-25 Jan Beulich <jbeulich@suse.com>
405
406 * i386-dis.c (XMGatherD, VexGatherD): New.
407 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
408 (print_insn): Check masking for S/G insns.
409 (OP_E_memory): New local variable check_gather. Extend mandatory
410 SIB check. Check register conflicts for (EVEX-encoded) gathers.
411 Extend check for disallowed 16-bit addressing.
412 (OP_VEX): New local variables modrm_reg and sib_index. Convert
413 if()s to switch(). Check register conflicts for (VEX-encoded)
414 gathers. Drop no longer reachable cases.
415 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
416 vgatherdp*.
417
53642852
JB		 4182021-03-25 Jan Beulich <jbeulich@suse.com>
419
420 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
421 zeroing-masking without masking.
422
c0e54661
JB		 4232021-03-25 Jan Beulich <jbeulich@suse.com>
424
425 * i386-opc.tbl (invlpgb): Fix multi-operand form.
426 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
427 single-operand forms as deprecated.
428 * i386-tbl.h: Re-generate.
429
5a403766
AM		 4302021-03-25 Alan Modra <amodra@gmail.com>
431
432 PR 27647
433 * ppc-opc.c (XLOCB_MASK): Delete.
434 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
435 XLBH_MASK.
436 (powerpc_opcodes): Accept a BH field on all extended forms of
437 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
438
9a182d04
JB		 4392021-03-24 Jan Beulich <jbeulich@suse.com>
440
441 * i386-gen.c (output_i386_opcode): Drop processing of
442 opcode_length. Calculate length from base_opcode. Adjust prefix
443 encoding determination.
444 (process_i386_opcodes): Drop output of fake opcode_length.
445 * i386-opc.h (struct insn_template): Drop opcode_length field.
446 * i386-opc.tbl: Drop opcode length field from all templates.
447 * i386-tbl.h: Re-generate.
448
35648716
JB		 4492021-03-24 Jan Beulich <jbeulich@suse.com>
450
451 * i386-gen.c (process_i386_opcode_modifier): Return void. New
452 parameter "prefix". Drop local variable "regular_encoding".
453 Record prefix setting / check for consistency.
454 (output_i386_opcode): Parse opcode_length and base_opcode
455 earlier. Derive prefix encoding. Drop no longer applicable
456 consistency checking. Adjust process_i386_opcode_modifier()
457 invocation.
458 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
459 invocation.
460 * i386-tbl.h: Re-generate.
461
31184569
JB		 4622021-03-24 Jan Beulich <jbeulich@suse.com>
463
464 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
465 check.
466 * i386-opc.h (Prefix_*): Move #define-s.
467 * i386-opc.tbl: Move pseudo prefix enumerator values to
468 extension opcode field. Introduce pseudopfx template.
469 * i386-tbl.h: Re-generate.
470
b933fa4b
JB		 4712021-03-23 Jan Beulich <jbeulich@suse.com>
472
473 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
474 comment.
475 * i386-tbl.h: Re-generate.
476
dac10fb0
JB		 4772021-03-23 Jan Beulich <jbeulich@suse.com>
478
479 * i386-opc.h (struct insn_template): Move cpu_flags field past
480 opcode_modifier one.
481 * i386-tbl.h: Re-generate.
482
441f6aca
JB		 4832021-03-23 Jan Beulich <jbeulich@suse.com>
484
485 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
486 * i386-opc.h (OpcodeSpace): New enumerator.
487 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
488 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
489 SPACE_XOP09, SPACE_XOP0A): ... respectively.
490 (struct i386_opcode_modifier): New field opcodespace. Shrink
491 opcodeprefix field.
492 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
493 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
494 OpcodePrefix uses.
495 * i386-tbl.h: Re-generate.
496
08dedd66
ML		 4972021-03-22 Martin Liska <mliska@suse.cz>
498
499 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
500 * arc-dis.c (parse_option): Likewise.
501 * arm-dis.c (parse_arm_disassembler_options): Likewise.
502 * cris-dis.c (print_with_operands): Likewise.
503 * h8300-dis.c (bfd_h8_disassemble): Likewise.
504 * i386-dis.c (print_insn): Likewise.
505 * ia64-gen.c (fetch_insn_class): Likewise.
506 (parse_resource_users): Likewise.
507 (in_iclass): Likewise.
508 (lookup_specifier): Likewise.
509 (insert_opcode_dependencies): Likewise.
510 * mips-dis.c (parse_mips_ase_option): Likewise.
511 (parse_mips_dis_option): Likewise.
512 * s390-dis.c (disassemble_init_s390): Likewise.
513 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
514
80d49d6a
KLC		 5152021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
516
517 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
518
7fce7ea9
PW		 5192021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
520
521 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
522 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
523
78c84bf9
AM		 5242021-03-12 Alan Modra <amodra@gmail.com>
525
526 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
527
fd1fd061
JB		 5282021-03-11 Jan Beulich <jbeulich@suse.com>
529
530 * i386-dis.c (OP_XMM): Re-order checks.
531
ac7a2311
JB		 5322021-03-11 Jan Beulich <jbeulich@suse.com>
533
534 * i386-dis.c (putop): Drop need_vex check when also checking
535 vex.evex.
536 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
537 checking vex.b.
538
da944c8a
JB		 5392021-03-11 Jan Beulich <jbeulich@suse.com>
540
541 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
542 checks. Move case label past broadcast check.
543
b763d508
JB		 5442021-03-10 Jan Beulich <jbeulich@suse.com>
545
546 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
547 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
548 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
549 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
550 EVEX_W_0F38C7_M_0_L_2): Delete.
551 (REG_EVEX_0F38C7_M_0_L_2): New.
552 (intel_operand_size): Handle VEX and EVEX the same for
553 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
554 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
555 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
556 vex_vsib_q_w_d_mode uses.
557 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
558 0F38A1, and 0F38A3 entries.
559 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
560 entry.
561 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
562 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
563 0F38A3 entries.
564
32e31ad7
JB		 5652021-03-10 Jan Beulich <jbeulich@suse.com>
566
567 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
568 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
569 MOD_VEX_0FXOP_09_12): Rename to ...
570 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
571 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
572 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
573 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
574 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
575 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
576 (reg_table): Adjust comments.
577 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
578 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
579 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
580 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
581 (vex_len_table): Adjust opcode 0A_12 entry.
582 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
583 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
584 (rm_table): Move hreset entry.
585
85ba7507
JB		 5862021-03-10 Jan Beulich <jbeulich@suse.com>
587
588 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
589 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
590 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
591 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
592 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
593 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
594 (get_valid_dis386): Also handle 512-bit vector length when
595 vectoring into vex_len_table[].
596 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
597 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
598 entries.
599 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
600 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
601 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
602 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
603 entries.
604
066f82b9
JB		 6052021-03-10 Jan Beulich <jbeulich@suse.com>
606
607 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
608 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
609 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
610 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
611 entries.
612 * i386-dis-evex-len.h (evex_len_table): Likewise.
613 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
614
fc681dd6
JB		 6152021-03-10 Jan Beulich <jbeulich@suse.com>
616
617 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
618 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
619 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
620 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
621 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
622 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
623 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
624 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
625 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
626 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
627 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
628 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
629 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
630 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
631 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
632 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
633 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
634 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
635 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
636 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
637 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
638 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
639 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
640 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
641 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
642 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
643 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
644 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
645 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
646 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
647 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
648 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
649 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
650 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
651 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
652 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
653 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
654 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
655 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
656 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
657 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
658 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
659 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
660 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
661 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
662 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
663 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
664 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
665 EVEX_W_0F3A43_L_n): New.
666 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
667 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
668 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
669 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
670 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
671 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
672 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
673 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
674 0F385B, 0F38C6, and 0F38C7 entries.
675 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
676 0F38C6 and 0F38C7.
677 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
678 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
679 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
680 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
681
13954a31
JB		 6822021-03-10 Jan Beulich <jbeulich@suse.com>
683
684 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
685 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
686 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
687 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
688 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
689 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
690 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
691 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
692 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
693 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
694 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
695 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
696 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
697 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
698 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
699 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
700 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
701 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
702 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
703 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
704 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
705 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
706 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
707 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
708 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
709 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
710 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
711 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
712 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
713 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
714 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
715 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
716 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
717 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
718 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
719 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
720 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
721 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
722 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
723 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
724 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
725 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
726 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
727 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
728 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
729 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
730 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
731 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
732 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
733 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
734 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
735 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
736 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
737 VEX_W_0F99_P_2_LEN_0): Delete.
738 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
739 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
740 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
741 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
742 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
743 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
744 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
745 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
746 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
747 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
748 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
749 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
750 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
751 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
752 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
753 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
754 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
755 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
756 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
757 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
758 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
759 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
760 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
761 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
762 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
763 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
764 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
765 (prefix_table): No longer link to vex_len_table[] for opcodes
766 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
767 0F92, 0F93, 0F98, and 0F99.
768 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
769 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
770 0F98, and 0F99.
771 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
772 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
773 0F98, and 0F99.
774 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
775 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
776 0F98, and 0F99.
777 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
778 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
779 0F98, and 0F99.
780
14d10c6c
JB		 7812021-03-10 Jan Beulich <jbeulich@suse.com>
782
783 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
784 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
785 REG_VEX_0F73_M_0 respectively.
786 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
787 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
788 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
789 MOD_VEX_0F73_REG_7): Delete.
790 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
791 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
792 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
793 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
794 PREFIX_VEX_0F3AF0_L_0 respectively.
795 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
796 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
797 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
798 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
799 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
800 VEX_LEN_0F38F7): New.
801 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
802 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
803 0F72, and 0F73. No longer link to vex_len_table[] for opcode
804 0F38F3.
805 (prefix_table): No longer link to vex_len_table[] for opcodes
806 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
807 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
808 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
809 0F38F6, 0F38F7, and 0F3AF0.
810 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
811 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
812 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
813 0F73.
814
00ec1875
JB		 8152021-03-10 Jan Beulich <jbeulich@suse.com>
816
817 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
818 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
819 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
820 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
821 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
822 (MOD_0F71, MOD_0F72, MOD_0F73): New.
823 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
824 73.
825 (reg_table): No longer link to mod_table[] for opcodes 0F71,
826 0F72, and 0F73.
827 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
828 0F73.
829
31941983
JB		 8302021-03-10 Jan Beulich <jbeulich@suse.com>
831
832 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
833 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
834 (reg_table): Don't link to mod_table[] where not needed. Add
835 PREFIX_IGNORED to nop entries.
836 (prefix_table): Replace PREFIX_OPCODE in nop entries.
837 (mod_table): Add nop entries next to prefetch ones. Drop
838 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
839 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
840 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
841 PREFIX_OPCODE from endbr* entries.
842 (get_valid_dis386): Also consider entry's name when zapping
843 vindex.
844 (print_insn): Handle PREFIX_IGNORED.
845
742732c7
JB		 8462021-03-09 Jan Beulich <jbeulich@suse.com>
847
848 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
849 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
850 element.
851 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
852 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
853 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
854 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
855 (struct i386_opcode_modifier): Delete notrackprefixok,
856 islockable, hleprefixok, and repprefixok fields. Add prefixok
857 field.
858 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
859 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
860 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
861 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
862 Replace HLEPrefixOk.
863 * opcodes/i386-tbl.h: Re-generate.
864
e93a3b27
JB		 8652021-03-09 Jan Beulich <jbeulich@suse.com>
866
867 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
868 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
869 64-bit form.
870 * opcodes/i386-tbl.h: Re-generate.
871
75363b6d
JB		 8722021-03-03 Jan Beulich <jbeulich@suse.com>
873
874 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
875 for {} instead of {0}. Don't look for '0'.
876 * i386-opc.tbl: Drop operand count field. Drop redundant operand
877 size specifiers.
878
5a9f5403
NC		 8792021-02-19 Nelson Chu <nelson.chu@sifive.com>
880
881 PR 27158
882 * riscv-dis.c (print_insn_args): Updated encoding macros.
883 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
884 (match_c_addi16sp): Updated encoding macros.
885 (match_c_lui): Likewise.
886 (match_c_lui_with_hint): Likewise.
887 (match_c_addi4spn): Likewise.
888 (match_c_slli): Likewise.
889 (match_slli_as_c_slli): Likewise.
890 (match_c_slli64): Likewise.
891 (match_srxi_as_c_srxi): Likewise.
892 (riscv_insn_types): Added .insn css/cl/cs.
893
3d73d29e
NC		 8942021-02-18 Nelson Chu <nelson.chu@sifive.com>
895
896 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
897 (default_priv_spec): Updated type to riscv_spec_class.
898 (parse_riscv_dis_option): Updated.
899 * riscv-opc.c: Moved stuff and make the file tidy.
900
b9b204b3
AM		 9012021-02-17 Alan Modra <amodra@gmail.com>
902
903 * wasm32-dis.c: Include limits.h.
904 (CHAR_BIT): Provide backup define.
905 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
906 Correct signed overflow checking.
907
394ae71f
JB		 9082021-02-16 Jan Beulich <jbeulich@suse.com>
909
910 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
911 * i386-tbl.h: Re-generate.
912
b818b220
JB		 9132021-02-16 Jan Beulich <jbeulich@suse.com>
914
915 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
916 Oword.
917 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
918
ba2b480f
AK		 9192021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
920
921 * s390-mkopc.c (main): Accept arch14 as cpu string.
922 * s390-opc.txt: Add new arch14 instructions.
923
95148614
NA		 9242021-02-04 Nick Alcock <nick.alcock@oracle.com>
925
926 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
927 favour of LIBINTL.
928 * configure: Regenerated.
929
bfd428bc
MF		 9302021-02-08 Mike Frysinger <vapier@gentoo.org>
931
932 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
933 * tic54x-opc.c (regs): Rename to ...
934 (tic54x_regs): ... this.
935 (mmregs): Rename to ...
936 (tic54x_mmregs): ... this.
937 (condition_codes): Rename to ...
938 (tic54x_condition_codes): ... this.
939 (cc2_codes): Rename to ...
940 (tic54x_cc2_codes): ... this.
941 (cc3_codes): Rename to ...
942 (tic54x_cc3_codes): ... this.
943 (status_bits): Rename to ...
944 (tic54x_status_bits): ... this.
945 (misc_symbols): Rename to ...
946 (tic54x_misc_symbols): ... this.
947
24075dcc
NC		 9482021-02-04 Nelson Chu <nelson.chu@sifive.com>
949
950 * riscv-opc.c (MASK_RVB_IMM): Removed.
951 (riscv_opcodes): Removed zb* instructions.
952 (riscv_ext_version_table): Removed versions for zb*.
953
c3ffb8f3
AM		 9542021-01-26 Alan Modra <amodra@gmail.com>
955
956 * i386-gen.c (parse_template): Ensure entire template_instance
957 is initialised.
958
1942a048
NC		 9592021-01-15 Nelson Chu <nelson.chu@sifive.com>
960
961 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
962 (riscv_fpr_names_abi): Likewise.
963 (riscv_opcodes): Likewise.
964 (riscv_insn_types): Likewise.
965
b800637e
NC		 9662021-01-15 Nelson Chu <nelson.chu@sifive.com>
967
968 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
969
dcd709e0
NC		 9702021-01-15 Nelson Chu <nelson.chu@sifive.com>
971
972 * riscv-dis.c: Comments tidy and improvement.
973 * riscv-opc.c: Likewise.
974
5347ed60
AM		 9752021-01-13 Alan Modra <amodra@gmail.com>
976
977 * Makefile.in: Regenerate.
978
d546b610
L		 9792021-01-12 H.J. Lu <hongjiu.lu@intel.com>
980
981 PR binutils/26792
982 * configure.ac: Use GNU_MAKE_JOBSERVER.
983 * aclocal.m4: Regenerated.
984 * configure: Likewise.
985
6d104cac
NC		 9862021-01-12 Nick Clifton <nickc@redhat.com>
987
988 * po/sr.po: Updated Serbian translation.
989
83b33c6c
L		 9902021-01-11 H.J. Lu <hongjiu.lu@intel.com>
991
992 PR ld/27173
993 * configure: Regenerated.
994
82c70b08
KT		 9952021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
996
997 * aarch64-asm-2.c: Regenerate.
998 * aarch64-dis-2.c: Likewise.
999 * aarch64-opc-2.c: Likewise.
1000 * aarch64-opc.c (aarch64_print_operand):
1001 Delete handling of AARCH64_OPND_CSRE_CSR.
1002 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1003 (CSRE): Likewise.
1004 (_CSRE_INSN): Likewise.
1005 (aarch64_opcode_table): Delete csr.
1006
a8aa72b9
NC		 10072021-01-11 Nick Clifton <nickc@redhat.com>
1008
1009 * po/de.po: Updated German translation.
1010 * po/fr.po: Updated French translation.
1011 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1012 * po/sv.po: Updated Swedish translation.
1013 * po/uk.po: Updated Ukranian translation.
1014
a4966cd9
L		 10152021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * configure: Regenerated.
1018
573fe3fb
NC		 10192021-01-09 Nick Clifton <nickc@redhat.com>
1020
1021 * configure: Regenerate.
1022 * po/opcodes.pot: Regenerate.
1023
055bc77a
NC		 10242021-01-09 Nick Clifton <nickc@redhat.com>
1025
1026 * 2.36 release branch crated.
1027
aae7fcb8
PB		 10282021-01-08 Peter Bergner <bergner@linux.ibm.com>
1029
1030 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1031 (DW, (XRC_MASK): Define.
1032 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1033
64307045
AM		 10342021-01-09 Alan Modra <amodra@gmail.com>
1035
1036 * configure: Regenerate.
1037
ed205222
NC		 10382021-01-08 Nick Clifton <nickc@redhat.com>
1039
1040 * po/sv.po: Updated Swedish translation.
1041
fb932b57
NC		 10422021-01-08 Nick Clifton <nickc@redhat.com>
1043
e84c8716
NC		 1044 PR 27129
1045 * aarch64-dis.c (determine_disassembling_preference): Move call to
1046 aarch64_match_operands_constraint outside of the assertion.
1047 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1048 Replace with a return of FALSE.
1049
fb932b57
NC		 1050 PR 27139
1051 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1052 core system register.
1053
f4782128
ST		 10542021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1055
1056 * configure: Regenerate.
1057
1b0927db
NC		 10582021-01-07 Nick Clifton <nickc@redhat.com>
1059
1060 * po/fr.po: Updated French translation.
1061
3b288c8e
FN		 10622021-01-07 Fredrik Noring <noring@nocrew.org>
1063
1064 * m68k-opc.c (chkl): Change minimum architecture requirement to
1065 m68020.
1066
aa881ecd
PT		 10672021-01-07 Philipp Tomsich <prt@gnu.org>
1068
1069 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1070
2652cfad
CXW		 10712021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1072 Jim Wilson <jimw@sifive.com>
1073 Andrew Waterman <andrew@sifive.com>
1074 Maxim Blinov <maxim.blinov@embecosm.com>
1075 Kito Cheng <kito.cheng@sifive.com>
1076 Nelson Chu <nelson.chu@sifive.com>
1077
1078 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1079 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1080
250d07de
AM		 10812021-01-01 Alan Modra <amodra@gmail.com>
1082
1083 Update year range in copyright notice of all files.
1084
c2795844 1085For older changes see ChangeLog-2020
3499769a 1086\f
c2795844 1087Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1088
1089Copying and distribution of this file, with or without modification,
1090are permitted in any medium without royalty provided the copyright
1091notice and this notice are preserved.
1092
1093Local Variables:
1094mode: change-log
1095left-margin: 8
1096fill-column: 74
1097version-control: never
1098End:
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