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opcodes: constify aarch64_opcode_tables
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6c2ede01
MF		 12021-07-01 Mike Frysinger <vapier@gentoo.org>
2
3 * aarch64-gen.c (aarch64_opcode_table): Add const.
4 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
5
46b8b3d6
AB		 62021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
7
8 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
9 available.
10
ded5cb94
AM		 112021-06-22 Alan Modra <amodra@gmail.com>
12
13 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
14 print separator for pcrel insns.
15
47399e9c
AM		 162021-06-19 Alan Modra <amodra@gmail.com>
17
18 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
19
d984392e
AM		 202021-06-19 Alan Modra <amodra@gmail.com>
21
22 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
23 entire buffer.
24
7993124e
AM		 252021-06-17 Alan Modra <amodra@gmail.com>
26
27 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
28 in table.
29
a38d1396
AM		 302021-06-03 Alan Modra <amodra@gmail.com>
31
32 PR 1202
33 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
34 Use unsigned int for inst.
35
8f467114
SV		 362021-06-02 Shahab Vahedi <shahab@synopsys.com>
37
38 * arc-dis.c (arc_option_arg_t): New enumeration.
39 (arc_options): New variable.
40 (disassembler_options_arc): New function.
41 (print_arc_disassembler_options): Reimplement in terms of
42 "disassembler_options_arc".
43
1ff6a3b8
AM		 442021-05-29 Alan Modra <amodra@gmail.com>
45
46 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
47 Don't special case PPC_OPCODE_RAW.
48 (lookup_prefix): Likewise.
49 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
50 (print_insn_powerpc): ..update caller.
51 * ppc-opc.c (EXT): Define.
52 (powerpc_opcodes): Mark extended mnemonics with EXT.
53 (prefix_opcodes, vle_opcodes): Likewise.
54 (XISEL, XISEL_MASK): Add cr field and simplify.
55 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
56 all isel variants to where the base mnemonic belongs. Sort dstt,
57 dststt and dssall.
58
49149d59
MR		 592021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
60
61 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
62 COP3 opcode instructions.
63
9573a461
MR		 642021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
65
66 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
67 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
68 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
69 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
70 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
71 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
72 "cop2", and "cop3" entries.
73
fa495743
MR		 742021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
75
76 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
77 entries and associated comments.
78
b930964c
MR		 792021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
80
81 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
82 of "c0".
83
dd844468
MR		 842021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
85
86 * mips-dis.c (mips_cp1_names_mips): New variable.
87 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
88 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
89 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
90 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
91 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
92 "loongson2f".
93
9204ccd4
MR		 942021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
95
96 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
97 handling code over to...
98 <OP_REG_CONTROL>: ... this new case.
99 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
100 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
101 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
102 replacing the `G' operand code with `g'. Update "cftc1" and
103 "cftc2" entries replacing the `E' operand code with `y'.
104 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
105 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
106 entries replacing the `G' operand code with `g'.
107
a3fb396f
MR		 1082021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
109
110 * mips-dis.c (mips_cp0_names_r3900): New variable.
111 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
112 for "r3900".
113
cccc84fa
MR		 1142021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
115
116 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
117 and "mtthc2" to using the `G' rather than `g' operand code for
118 the coprocessor control register referred.
119
c9de3168
MR		 1202021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
121
122 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
123 entries with each other.
124
ebcab741
PB		 1252021-05-27 Peter Bergner <bergner@linux.ibm.com>
126
127 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
128
bc30a119
AM		 1292021-05-25 Alan Modra <amodra@gmail.com>
130
131 * cris-desc.c: Regenerate.
132 * cris-desc.h: Regenerate.
133 * cris-opc.h: Regenerate.
134 * po/POTFILES.in: Regenerate.
135
54711280
MF		 1362021-05-24 Mike Frysinger <vapier@gentoo.org>
137
138 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
139 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
140 (CGEN_CPUS): Add cris.
141 (CRIS_DEPS): Define.
142 (stamp-cris): New rule.
143 * cgen.sh: Handle desc action.
144 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
145 * Makefile.in, configure: Regenerate.
146
113bb761
JN		 1472021-05-18 Job Noorman <mtvec@pm.me>
148
149 PR 27814
150 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
151 the elf objects.
152
e683cb41
AC		 1532021-05-17 Alex Coplan <alex.coplan@arm.com>
154
155 * arm-dis.c (mve_opcodes): Fix disassembly of
156 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
157 (is_mve_encoding_conflict): MVE vector loads should not match
158 when P = W = 0.
159 (is_mve_unpredictable): It's not unpredictable to use the same
160 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
161
a680affc
NC		 1622021-05-11 Nick Clifton <nickc@redhat.com>
163
164 PR 27840
165 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
166 the end of the code buffer.
167
0b3e14c9
SH		 1682021-05-06 Stafford Horne <shorne@gmail.com>
169
170 PR 21464
171 * or1k-asm.c: Regenerate.
172
6aee2cb2
MF		 1732021-05-01 Max Filippov <jcmvbkbc@gmail.com>
174
175 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
176 info->insn_info_valid.
177
fe134c65
JB		 1782021-04-26 Jan Beulich <jbeulich@suse.com>
179
180 * i386-opc.tbl (lea): Add Optimize.
181 * opcodes/i386-tbl.h: Re-generate.
182
b3ea7639
MF		 1832020-04-23 Max Filippov <jcmvbkbc@gmail.com>
184
185 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
186 of l32r fetch and display referenced literal value.
187
c1cbb7d8
MF		 1882021-04-23 Max Filippov <jcmvbkbc@gmail.com>
189
190 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
191 to 4 for literal disassembly.
192
02202574
PW		 1932021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
194
195 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
196 for TLBI instruction.
197
cd6608e4
PW		 1982021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
199
200 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
201 DC instruction.
202
fe1640ff
JB		 2032021-04-19 Jan Beulich <jbeulich@suse.com>
204
205 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
206 "qualifier".
207 (convert_mov_to_movewide): Add initializer for "value".
208
100e914d
PW		 2092021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
210
211 * aarch64-opc.c: Add RME system registers.
212
a21b96dd
NC		 2132021-04-16 Lifang Xia <lifang_xia@c-sky.com>
214
215 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
216 "addi d,CV,z" to "c.mv d,CV".
217
43e05cd4
AM		 2182021-04-12 Alan Modra <amodra@gmail.com>
219
220 * configure.ac (--enable-checking): Add support.
221 * config.in: Regenerate.
222 * configure: Regenerate.
223
52efda82
TB		 2242021-04-09 Tejas Belagod <tejas.belagod@arm.com>
225
226 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
227 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
228
c3f72de4
AM		 2292021-04-09 Alan Modra <amodra@gmail.com>
230
231 * ppc-dis.c (struct dis_private): Add "special".
232 (POWERPC_DIALECT): Delete. Replace uses with..
233 (private_data): ..this. New inline function.
234 (disassemble_init_powerpc): Init "special" names.
235 (skip_optional_operands): Add is_pcrel arg, set when detecting R
236 field of prefix instructions.
237 (bsearch_reloc, print_got_plt): New functions.
238 (print_insn_powerpc): For pcrel instructions, print target address
239 and symbol if known, and decode plt and got loads too.
240
ce7d813a
AM		 2412021-04-08 Alan Modra <amodra@gmail.com>
242
243 PR 27684
244 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
245
97bf40d8
AM		 2462021-04-08 Alan Modra <amodra@gmail.com>
247
248 PR 27676
249 * ppc-opc.c (DCBT_EO): Move earlier.
250 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
251 (powerpc_operands): Add THCT and THDS entries.
252 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
253
a2e66773
AM		 2542021-04-06 Alan Modra <amodra@gmail.com>
255
256 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
257 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
258 symbol_at_address_func.
259
ab2af25e
AM		 2602021-04-05 Alan Modra <amodra@gmail.com>
261
262 * configure.ac: Don't check for limits.h, string.h, strings.h or
263 stdlib.h.
264 (AC_ISC_POSIX): Don't invoke.
265 * sysdep.h: Include stdlib.h and string.h unconditionally.
266 * i386-opc.h: Include limits.h unconditionally.
267 * wasm32-dis.c: Likewise.
268 * cgen-opc.c: Don't include alloca-conf.h.
269 * config.in: Regenerate.
270 * configure: Regenerate.
271
e9b095a5
ML		 2722021-04-01 Martin Liska <mliska@suse.cz>
273
274 * arm-dis.c (strneq): Remove strneq and use startswith.
275 * cr16-dis.c (print_insn_cr16): Likewise.
276 * score-dis.c (streq): Likewise.
277 (strneq): Likewise.
278 * score7-dis.c (strneq): Likewise.
279
1cb108e4
AM		 2802021-04-01 Alan Modra <amodra@gmail.com>
281
282 PR 27675
283 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
284
78933a4a
AM		 2852021-03-31 Alan Modra <amodra@gmail.com>
286
287 * sysdep.h (POISON_BFD_BOOLEAN): Define.
288 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
289 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
290 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
291 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
292 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
293 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
294 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
295 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
296 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
297 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
298 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
299 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
300 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
301 and TRUE with true throughout.
302
3dfb1b6d
AM		 3032021-03-31 Alan Modra <amodra@gmail.com>
304
305 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
306 * aarch64-dis.h: Likewise.
307 * aarch64-opc.c: Likewise.
308 * avr-dis.c: Likewise.
309 * csky-dis.c: Likewise.
310 * nds32-asm.c: Likewise.
311 * nds32-dis.c: Likewise.
312 * nfp-dis.c: Likewise.
313 * riscv-dis.c: Likewise.
314 * s12z-dis.c: Likewise.
315 * wasm32-dis.c: Likewise.
316
5e042380
JB		 3172021-03-30 Jan Beulich <jbeulich@suse.com>
318
319 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
320 (i386_seg_prefixes): New.
321 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
322 (i386_seg_prefixes): Declare.
323
34684862
JB		 3242021-03-30 Jan Beulich <jbeulich@suse.com>
325
326 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
327
6288d05f
JB		 3282021-03-30 Jan Beulich <jbeulich@suse.com>
329
330 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
331 * i386-reg.tbl (st): Move down.
332 (st(0)): Delete. Extend comment.
333 * i386-tbl.h: Re-generate.
334
bbe1eca6
JB		 3352021-03-29 Jan Beulich <jbeulich@suse.com>
336
337 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
338 (cmpsd): Move next to cmps.
339 (movsd): Move next to movs.
340 (cmpxchg16b): Move to separate section.
341 (fisttp, fisttpll): Likewise.
342 (monitor, mwait): Likewise.
343 * i386-tbl.h: Re-generate.
344
c8cad9d3
JB		 3452021-03-29 Jan Beulich <jbeulich@suse.com>
346
347 * i386-opc.tbl (psadbw): Add <sse2:comm>.
348 (vpsadbw): Add C.
349 * i386-tbl.h: Re-generate.
350
5cdaf100
JB		 3512021-03-29 Jan Beulich <jbeulich@suse.com>
352
353 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
354 pclmul, gfni): New templates. Use them wherever possible. Move
355 SSE4.1 pextrw into respective section.
356 * i386-tbl.h: Re-generate.
357
73e45eb2
JB		 3582021-03-29 Jan Beulich <jbeulich@suse.com>
359
360 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
361 strtoull(). Bump upper loop bound. Widen masks. Sanity check
362 "length".
363 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
364 Convert all of their uses to representation in opcode.
365
9df6f676
JB		 3662021-03-29 Jan Beulich <jbeulich@suse.com>
367
368 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
369 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
370 value of None. Shrink operands to 3 bits.
371
389d00a5
JB		 3722021-03-29 Jan Beulich <jbeulich@suse.com>
373
374 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 375 "space".
389d00a5
JB		 376 (output_i386_opcode): New local variable "space". Adjust
377 process_i386_opcode_modifier() invocation.
378 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
379 invocation.
380 * i386-tbl.h: Re-generate.
381
63b4cc53
AM		 3822021-03-29 Alan Modra <amodra@gmail.com>
383
384 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
385 (fp_qualifier_p, get_data_pattern): Likewise.
386 (aarch64_get_operand_modifier_from_value): Likewise.
387 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
388 (operand_variant_qualifier_p): Likewise.
389 (qualifier_value_in_range_constraint_p): Likewise.
390 (aarch64_get_qualifier_esize): Likewise.
391 (aarch64_get_qualifier_nelem): Likewise.
392 (aarch64_get_qualifier_standard_value): Likewise.
393 (get_lower_bound, get_upper_bound): Likewise.
394 (aarch64_find_best_match, match_operands_qualifier): Likewise.
395 (aarch64_print_operand): Likewise.
396 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
397 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
398 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
399 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
400 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
401 (print_insn_tic6x): Likewise.
402
3d7d6c1b
AM		 4032021-03-29 Alan Modra <amodra@gmail.com>
404
405 * arc-dis.c (extract_operand_value): Correct NULL cast.
406 * frv-opc.h: Regenerate.
407
c3344b62
JB		 4082021-03-26 Jan Beulich <jbeulich@suse.com>
409
410 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
411 MMX form.
412 * i386-tbl.h: Re-generate.
413
efa30ac3
HAQ		 4142021-03-25 Abid Qadeer <abidh@codesourcery.com>
415
416 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
417 immediate in br.n instruction.
418
596a02ff
JB		 4192021-03-25 Jan Beulich <jbeulich@suse.com>
420
421 * i386-dis.c (XMGatherD, VexGatherD): New.
422 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
423 (print_insn): Check masking for S/G insns.
424 (OP_E_memory): New local variable check_gather. Extend mandatory
425 SIB check. Check register conflicts for (EVEX-encoded) gathers.
426 Extend check for disallowed 16-bit addressing.
427 (OP_VEX): New local variables modrm_reg and sib_index. Convert
428 if()s to switch(). Check register conflicts for (VEX-encoded)
429 gathers. Drop no longer reachable cases.
430 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
431 vgatherdp*.
432
53642852
JB		 4332021-03-25 Jan Beulich <jbeulich@suse.com>
434
435 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
436 zeroing-masking without masking.
437
c0e54661
JB		 4382021-03-25 Jan Beulich <jbeulich@suse.com>
439
440 * i386-opc.tbl (invlpgb): Fix multi-operand form.
441 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
442 single-operand forms as deprecated.
443 * i386-tbl.h: Re-generate.
444
5a403766
AM		 4452021-03-25 Alan Modra <amodra@gmail.com>
446
447 PR 27647
448 * ppc-opc.c (XLOCB_MASK): Delete.
449 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
450 XLBH_MASK.
451 (powerpc_opcodes): Accept a BH field on all extended forms of
452 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
453
9a182d04
JB		 4542021-03-24 Jan Beulich <jbeulich@suse.com>
455
456 * i386-gen.c (output_i386_opcode): Drop processing of
457 opcode_length. Calculate length from base_opcode. Adjust prefix
458 encoding determination.
459 (process_i386_opcodes): Drop output of fake opcode_length.
460 * i386-opc.h (struct insn_template): Drop opcode_length field.
461 * i386-opc.tbl: Drop opcode length field from all templates.
462 * i386-tbl.h: Re-generate.
463
35648716
JB		 4642021-03-24 Jan Beulich <jbeulich@suse.com>
465
466 * i386-gen.c (process_i386_opcode_modifier): Return void. New
467 parameter "prefix". Drop local variable "regular_encoding".
468 Record prefix setting / check for consistency.
469 (output_i386_opcode): Parse opcode_length and base_opcode
470 earlier. Derive prefix encoding. Drop no longer applicable
471 consistency checking. Adjust process_i386_opcode_modifier()
472 invocation.
473 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
474 invocation.
475 * i386-tbl.h: Re-generate.
476
31184569
JB		 4772021-03-24 Jan Beulich <jbeulich@suse.com>
478
479 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
480 check.
481 * i386-opc.h (Prefix_*): Move #define-s.
482 * i386-opc.tbl: Move pseudo prefix enumerator values to
483 extension opcode field. Introduce pseudopfx template.
484 * i386-tbl.h: Re-generate.
485
b933fa4b
JB		 4862021-03-23 Jan Beulich <jbeulich@suse.com>
487
488 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
489 comment.
490 * i386-tbl.h: Re-generate.
491
dac10fb0
JB		 4922021-03-23 Jan Beulich <jbeulich@suse.com>
493
494 * i386-opc.h (struct insn_template): Move cpu_flags field past
495 opcode_modifier one.
496 * i386-tbl.h: Re-generate.
497
441f6aca
JB		 4982021-03-23 Jan Beulich <jbeulich@suse.com>
499
500 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
501 * i386-opc.h (OpcodeSpace): New enumerator.
502 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
503 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
504 SPACE_XOP09, SPACE_XOP0A): ... respectively.
505 (struct i386_opcode_modifier): New field opcodespace. Shrink
506 opcodeprefix field.
507 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
508 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
509 OpcodePrefix uses.
510 * i386-tbl.h: Re-generate.
511
08dedd66
ML		 5122021-03-22 Martin Liska <mliska@suse.cz>
513
514 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
515 * arc-dis.c (parse_option): Likewise.
516 * arm-dis.c (parse_arm_disassembler_options): Likewise.
517 * cris-dis.c (print_with_operands): Likewise.
518 * h8300-dis.c (bfd_h8_disassemble): Likewise.
519 * i386-dis.c (print_insn): Likewise.
520 * ia64-gen.c (fetch_insn_class): Likewise.
521 (parse_resource_users): Likewise.
522 (in_iclass): Likewise.
523 (lookup_specifier): Likewise.
524 (insert_opcode_dependencies): Likewise.
525 * mips-dis.c (parse_mips_ase_option): Likewise.
526 (parse_mips_dis_option): Likewise.
527 * s390-dis.c (disassemble_init_s390): Likewise.
528 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
529
80d49d6a
KLC		 5302021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
531
532 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
533
7fce7ea9
PW		 5342021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
535
536 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
537 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
538
78c84bf9
AM		 5392021-03-12 Alan Modra <amodra@gmail.com>
540
541 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
542
fd1fd061
JB		 5432021-03-11 Jan Beulich <jbeulich@suse.com>
544
545 * i386-dis.c (OP_XMM): Re-order checks.
546
ac7a2311
JB		 5472021-03-11 Jan Beulich <jbeulich@suse.com>
548
549 * i386-dis.c (putop): Drop need_vex check when also checking
550 vex.evex.
551 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
552 checking vex.b.
553
da944c8a
JB		 5542021-03-11 Jan Beulich <jbeulich@suse.com>
555
556 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
557 checks. Move case label past broadcast check.
558
b763d508
JB		 5592021-03-10 Jan Beulich <jbeulich@suse.com>
560
561 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
562 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
563 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
564 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
565 EVEX_W_0F38C7_M_0_L_2): Delete.
566 (REG_EVEX_0F38C7_M_0_L_2): New.
567 (intel_operand_size): Handle VEX and EVEX the same for
568 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
569 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
570 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
571 vex_vsib_q_w_d_mode uses.
572 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
573 0F38A1, and 0F38A3 entries.
574 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
575 entry.
576 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
577 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
578 0F38A3 entries.
579
32e31ad7
JB		 5802021-03-10 Jan Beulich <jbeulich@suse.com>
581
582 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
583 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
584 MOD_VEX_0FXOP_09_12): Rename to ...
585 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
586 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
587 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
588 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
589 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
590 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
591 (reg_table): Adjust comments.
592 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
593 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
594 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
595 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
596 (vex_len_table): Adjust opcode 0A_12 entry.
597 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
598 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
599 (rm_table): Move hreset entry.
600
85ba7507
JB		 6012021-03-10 Jan Beulich <jbeulich@suse.com>
602
603 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
604 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
605 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
606 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
607 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
608 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
609 (get_valid_dis386): Also handle 512-bit vector length when
610 vectoring into vex_len_table[].
611 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
612 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
613 entries.
614 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
615 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
616 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
617 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
618 entries.
619
066f82b9
JB		 6202021-03-10 Jan Beulich <jbeulich@suse.com>
621
622 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
623 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
624 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
625 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
626 entries.
627 * i386-dis-evex-len.h (evex_len_table): Likewise.
628 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
629
fc681dd6
JB		 6302021-03-10 Jan Beulich <jbeulich@suse.com>
631
632 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
633 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
634 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
635 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
636 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
637 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
638 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
639 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
640 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
641 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
642 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
643 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
644 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
645 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
646 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
647 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
648 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
649 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
650 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
651 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
652 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
653 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
654 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
655 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
656 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
657 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
658 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
659 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
660 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
661 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
662 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
663 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
664 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
665 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
666 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
667 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
668 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
669 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
670 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
671 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
672 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
673 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
674 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
675 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
676 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
677 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
678 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
679 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
680 EVEX_W_0F3A43_L_n): New.
681 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
682 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
683 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
684 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
685 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
686 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
687 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
688 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
689 0F385B, 0F38C6, and 0F38C7 entries.
690 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
691 0F38C6 and 0F38C7.
692 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
693 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
694 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
695 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
696
13954a31
JB		 6972021-03-10 Jan Beulich <jbeulich@suse.com>
698
699 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
700 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
701 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
702 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
703 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
704 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
705 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
706 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
707 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
708 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
709 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
710 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
711 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
712 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
713 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
714 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
715 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
716 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
717 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
718 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
719 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
720 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
721 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
722 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
723 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
724 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
725 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
726 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
727 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
728 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
729 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
730 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
731 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
732 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
733 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
734 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
735 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
736 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
737 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
738 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
739 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
740 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
741 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
742 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
743 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
744 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
745 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
746 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
747 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
748 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
749 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
750 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
751 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
752 VEX_W_0F99_P_2_LEN_0): Delete.
753 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
754 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
755 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
756 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
757 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
758 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
759 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
760 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
761 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
762 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
763 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
764 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
765 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
766 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
767 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
768 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
769 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
770 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
771 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
772 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
773 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
774 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
775 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
776 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
777 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
778 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
779 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
780 (prefix_table): No longer link to vex_len_table[] for opcodes
781 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
782 0F92, 0F93, 0F98, and 0F99.
783 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
784 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
785 0F98, and 0F99.
786 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
787 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
788 0F98, and 0F99.
789 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
790 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
791 0F98, and 0F99.
792 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
793 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
794 0F98, and 0F99.
795
14d10c6c
JB		 7962021-03-10 Jan Beulich <jbeulich@suse.com>
797
798 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
799 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
800 REG_VEX_0F73_M_0 respectively.
801 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
802 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
803 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
804 MOD_VEX_0F73_REG_7): Delete.
805 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
806 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
807 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
808 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
809 PREFIX_VEX_0F3AF0_L_0 respectively.
810 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
811 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
812 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
813 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
814 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
815 VEX_LEN_0F38F7): New.
816 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
817 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
818 0F72, and 0F73. No longer link to vex_len_table[] for opcode
819 0F38F3.
820 (prefix_table): No longer link to vex_len_table[] for opcodes
821 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
822 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
823 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
824 0F38F6, 0F38F7, and 0F3AF0.
825 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
826 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
827 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
828 0F73.
829
00ec1875
JB		 8302021-03-10 Jan Beulich <jbeulich@suse.com>
831
832 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
833 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
834 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
835 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
836 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
837 (MOD_0F71, MOD_0F72, MOD_0F73): New.
838 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
839 73.
840 (reg_table): No longer link to mod_table[] for opcodes 0F71,
841 0F72, and 0F73.
842 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
843 0F73.
844
31941983
JB		 8452021-03-10 Jan Beulich <jbeulich@suse.com>
846
847 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
848 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
849 (reg_table): Don't link to mod_table[] where not needed. Add
850 PREFIX_IGNORED to nop entries.
851 (prefix_table): Replace PREFIX_OPCODE in nop entries.
852 (mod_table): Add nop entries next to prefetch ones. Drop
853 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
854 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
855 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
856 PREFIX_OPCODE from endbr* entries.
857 (get_valid_dis386): Also consider entry's name when zapping
858 vindex.
859 (print_insn): Handle PREFIX_IGNORED.
860
742732c7
JB		 8612021-03-09 Jan Beulich <jbeulich@suse.com>
862
863 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
864 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
865 element.
866 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
867 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
868 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
869 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
870 (struct i386_opcode_modifier): Delete notrackprefixok,
871 islockable, hleprefixok, and repprefixok fields. Add prefixok
872 field.
873 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
874 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
875 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
876 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
877 Replace HLEPrefixOk.
878 * opcodes/i386-tbl.h: Re-generate.
879
e93a3b27
JB		 8802021-03-09 Jan Beulich <jbeulich@suse.com>
881
882 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
883 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
884 64-bit form.
885 * opcodes/i386-tbl.h: Re-generate.
886
75363b6d
JB		 8872021-03-03 Jan Beulich <jbeulich@suse.com>
888
889 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
890 for {} instead of {0}. Don't look for '0'.
891 * i386-opc.tbl: Drop operand count field. Drop redundant operand
892 size specifiers.
893
5a9f5403
NC		 8942021-02-19 Nelson Chu <nelson.chu@sifive.com>
895
896 PR 27158
897 * riscv-dis.c (print_insn_args): Updated encoding macros.
898 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
899 (match_c_addi16sp): Updated encoding macros.
900 (match_c_lui): Likewise.
901 (match_c_lui_with_hint): Likewise.
902 (match_c_addi4spn): Likewise.
903 (match_c_slli): Likewise.
904 (match_slli_as_c_slli): Likewise.
905 (match_c_slli64): Likewise.
906 (match_srxi_as_c_srxi): Likewise.
907 (riscv_insn_types): Added .insn css/cl/cs.
908
3d73d29e
NC		 9092021-02-18 Nelson Chu <nelson.chu@sifive.com>
910
911 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
912 (default_priv_spec): Updated type to riscv_spec_class.
913 (parse_riscv_dis_option): Updated.
914 * riscv-opc.c: Moved stuff and make the file tidy.
915
b9b204b3
AM		 9162021-02-17 Alan Modra <amodra@gmail.com>
917
918 * wasm32-dis.c: Include limits.h.
919 (CHAR_BIT): Provide backup define.
920 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
921 Correct signed overflow checking.
922
394ae71f
JB		 9232021-02-16 Jan Beulich <jbeulich@suse.com>
924
925 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
926 * i386-tbl.h: Re-generate.
927
b818b220
JB		 9282021-02-16 Jan Beulich <jbeulich@suse.com>
929
930 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
931 Oword.
932 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
933
ba2b480f
AK		 9342021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
935
936 * s390-mkopc.c (main): Accept arch14 as cpu string.
937 * s390-opc.txt: Add new arch14 instructions.
938
95148614
NA		 9392021-02-04 Nick Alcock <nick.alcock@oracle.com>
940
941 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
942 favour of LIBINTL.
943 * configure: Regenerated.
944
bfd428bc
MF		 9452021-02-08 Mike Frysinger <vapier@gentoo.org>
946
947 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
948 * tic54x-opc.c (regs): Rename to ...
949 (tic54x_regs): ... this.
950 (mmregs): Rename to ...
951 (tic54x_mmregs): ... this.
952 (condition_codes): Rename to ...
953 (tic54x_condition_codes): ... this.
954 (cc2_codes): Rename to ...
955 (tic54x_cc2_codes): ... this.
956 (cc3_codes): Rename to ...
957 (tic54x_cc3_codes): ... this.
958 (status_bits): Rename to ...
959 (tic54x_status_bits): ... this.
960 (misc_symbols): Rename to ...
961 (tic54x_misc_symbols): ... this.
962
24075dcc
NC		 9632021-02-04 Nelson Chu <nelson.chu@sifive.com>
964
965 * riscv-opc.c (MASK_RVB_IMM): Removed.
966 (riscv_opcodes): Removed zb* instructions.
967 (riscv_ext_version_table): Removed versions for zb*.
968
c3ffb8f3
AM		 9692021-01-26 Alan Modra <amodra@gmail.com>
970
971 * i386-gen.c (parse_template): Ensure entire template_instance
972 is initialised.
973
1942a048
NC		 9742021-01-15 Nelson Chu <nelson.chu@sifive.com>
975
976 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
977 (riscv_fpr_names_abi): Likewise.
978 (riscv_opcodes): Likewise.
979 (riscv_insn_types): Likewise.
980
b800637e
NC		 9812021-01-15 Nelson Chu <nelson.chu@sifive.com>
982
983 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
984
dcd709e0
NC		 9852021-01-15 Nelson Chu <nelson.chu@sifive.com>
986
987 * riscv-dis.c: Comments tidy and improvement.
988 * riscv-opc.c: Likewise.
989
5347ed60
AM		 9902021-01-13 Alan Modra <amodra@gmail.com>
991
992 * Makefile.in: Regenerate.
993
d546b610
L		 9942021-01-12 H.J. Lu <hongjiu.lu@intel.com>
995
996 PR binutils/26792
997 * configure.ac: Use GNU_MAKE_JOBSERVER.
998 * aclocal.m4: Regenerated.
999 * configure: Likewise.
1000
6d104cac
NC		 10012021-01-12 Nick Clifton <nickc@redhat.com>
1002
1003 * po/sr.po: Updated Serbian translation.
1004
83b33c6c
L		 10052021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1006
1007 PR ld/27173
1008 * configure: Regenerated.
1009
82c70b08
KT		 10102021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1011
1012 * aarch64-asm-2.c: Regenerate.
1013 * aarch64-dis-2.c: Likewise.
1014 * aarch64-opc-2.c: Likewise.
1015 * aarch64-opc.c (aarch64_print_operand):
1016 Delete handling of AARCH64_OPND_CSRE_CSR.
1017 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1018 (CSRE): Likewise.
1019 (_CSRE_INSN): Likewise.
1020 (aarch64_opcode_table): Delete csr.
1021
a8aa72b9
NC		 10222021-01-11 Nick Clifton <nickc@redhat.com>
1023
1024 * po/de.po: Updated German translation.
1025 * po/fr.po: Updated French translation.
1026 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1027 * po/sv.po: Updated Swedish translation.
1028 * po/uk.po: Updated Ukranian translation.
1029
a4966cd9
L		 10302021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1031
1032 * configure: Regenerated.
1033
573fe3fb
NC		 10342021-01-09 Nick Clifton <nickc@redhat.com>
1035
1036 * configure: Regenerate.
1037 * po/opcodes.pot: Regenerate.
1038
055bc77a
NC		 10392021-01-09 Nick Clifton <nickc@redhat.com>
1040
1041 * 2.36 release branch crated.
1042
aae7fcb8
PB		 10432021-01-08 Peter Bergner <bergner@linux.ibm.com>
1044
1045 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1046 (DW, (XRC_MASK): Define.
1047 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1048
64307045
AM		 10492021-01-09 Alan Modra <amodra@gmail.com>
1050
1051 * configure: Regenerate.
1052
ed205222
NC		 10532021-01-08 Nick Clifton <nickc@redhat.com>
1054
1055 * po/sv.po: Updated Swedish translation.
1056
fb932b57
NC		 10572021-01-08 Nick Clifton <nickc@redhat.com>
1058
e84c8716
NC		 1059 PR 27129
1060 * aarch64-dis.c (determine_disassembling_preference): Move call to
1061 aarch64_match_operands_constraint outside of the assertion.
1062 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1063 Replace with a return of FALSE.
1064
fb932b57
NC		 1065 PR 27139
1066 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1067 core system register.
1068
f4782128
ST		 10692021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1070
1071 * configure: Regenerate.
1072
1b0927db
NC		 10732021-01-07 Nick Clifton <nickc@redhat.com>
1074
1075 * po/fr.po: Updated French translation.
1076
3b288c8e
FN		 10772021-01-07 Fredrik Noring <noring@nocrew.org>
1078
1079 * m68k-opc.c (chkl): Change minimum architecture requirement to
1080 m68020.
1081
aa881ecd
PT		 10822021-01-07 Philipp Tomsich <prt@gnu.org>
1083
1084 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1085
2652cfad
CXW		 10862021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1087 Jim Wilson <jimw@sifive.com>
1088 Andrew Waterman <andrew@sifive.com>
1089 Maxim Blinov <maxim.blinov@embecosm.com>
1090 Kito Cheng <kito.cheng@sifive.com>
1091 Nelson Chu <nelson.chu@sifive.com>
1092
1093 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1094 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1095
250d07de
AM		 10962021-01-01 Alan Modra <amodra@gmail.com>
1097
1098 Update year range in copyright notice of all files.
1099
c2795844 1100For older changes see ChangeLog-2020
3499769a 1101\f
c2795844 1102Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1103
1104Copying and distribution of this file, with or without modification,
1105are permitted in any medium without royalty provided the copyright
1106notice and this notice are preserved.
1107
1108Local Variables:
1109mode: change-log
1110left-margin: 8
1111fill-column: 74
1112version-control: never
1113End:
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