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Add new NT_ARM_ZA and NT_ARM_SSVE register set constants.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a72b0718
NC		 12022-12-31 Nick Clifton <nickc@redhat.com>
2
3 * 2.40 branch created.
4
b2059307
SV		 52022-11-22 Shahab Vahedi <shahab@synopsys.com>
6
7 * arc-regs.h: Change isa_config address to 0xc1.
8 isa_config exists for ARC700 and ARCV2 and not ARCALL.
9
de1fbe78
YS		 102022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
11
12 * rx-decode.opc: Switch arguments of the MVTACGU insn.
13 * rx-decode.c: Regenerate.
14
3b8e069a
YS		 152022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
16
17 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
18 Rm_BANK,Rn is always 1.
19
c07ec968
PB		 202022-07-21 Peter Bergner <bergner@linux.ibm.com>
21
22 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
23 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
24 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
25 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
26 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
27 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
28 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
29
bbcab336
CZ		 302022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
31
32 * disassemble.c (disassemble_init_for_target): Set
33 created_styled_output for ARC based targets.
34 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
35 instead of fprintf_ftype throughout.
36 (find_format): Likewise.
37 (print_flags): Likewise.
38 (print_insn_arc): Likewise.
39
0bd09323
NC		 402022-07-08 Nick Clifton <nickc@redhat.com>
41
42 * 2.39 branch created.
43
a0f3a4c6
MN		 442022-07-04 Marcus Nilsson <brainbomb@gmail.com>
45
46 * disassemble.c: (disassemble_init_for_target): Set
47 created_styled_output for AVR based targets.
48 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
49 instead of fprintf_ftype throughout.
50 (avr_operand): Pass in and fill disassembler_style when
51 parsing operands.
52
69341966
AK		 532022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
54
55 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
56 table.
57
e3161106
SM		 582022-03-16 Simon Marchi <simon.marchi@efficios.com>
59
60 * configure.ac: Handle bfd_amdgcn_arch.
61 * configure: Re-generate.
62
d17e797f
MR		 632022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
64 Maciej W. Rozycki <macro@orcam.me.uk>
65
66 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
67 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
68 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
69 "bnez" instructions.
70
36d285b9
NC		 712022-02-17 Nick Clifton <nickc@redhat.com>
72
73 * po/sr.po: Updated Serbian translation.
74
a532eb72
ST		 752022-02-14 Sergei Trofimovich <siarheit@google.com>
76
77 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
78 * microblaze-opc.h: Follow 'fsqrt' rename.
79
5fe73d46
NC		 802022-01-24 Nick Clifton <nickc@redhat.com>
81
82 * po/ro.po: Updated Romanian translation.
83 * po/uk.po: Updated Ukranian translation.
84
f908e960
NC		 852022-01-22 Nick Clifton <nickc@redhat.com>
86
87 * configure: Regenerate.
88 * po/opcodes.pot: Regenerate.
89
a74e1cb3
NC		 902022-01-22 Nick Clifton <nickc@redhat.com>
91
92 * 2.38 release branch created.
93
6c037fdb
NC		 942022-01-17 Nick Clifton <nickc@redhat.com>
95
96 * Makefile.in: Regenerate.
97 * po/opcodes.pot: Regenerate.
98
96c7115a
MN		 992021-12-02 Marcus Nilsson <brainbomb@gmail.com>
100
101 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
102 in insn_type on branching instructions.
103
3a337a86
AB		 1042021-11-25 Andrew Burgess <aburgess@redhat.com>
105 Simon Cook <simon.cook@embecosm.com>
106
107 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
108 (riscv_options): New static global.
109 (disassembler_options_riscv): New function.
110 (print_riscv_disassembler_options): Rewrite to use
111 disassembler_options_riscv.
112
7060c28e
NC		 1132021-11-25 Nick Clifton <nickc@redhat.com>
114
115 PR 28614
116 * aarch64-asm.c: Replace assert(0) with real code.
117 * aarch64-dis.c: Likewise.
118 * aarch64-opc.c: Likewise.
119
79abb939
NC		 1202021-11-25 Nick Clifton <nickc@redhat.com>
121
122 * po/fr.po; Updated French translation.
123
2b677209
MR		 1242021-10-27 Maciej W. Rozycki <macro@embecosm.com>
125
126 * Makefile.am: Remove obsolete comment.
127 * configure.ac: Refer `libbfd.la' to link shared BFD library
128 except for Cygwin.
129 * Makefile.in: Regenerate.
130 * configure: Regenerate.
131
b9004024
NA		 1322021-09-27 Nick Alcock <nick.alcock@oracle.com>
133
134 * configure: Regenerate.
135
4d5d5d46
PB		 1362021-09-25 Peter Bergner <bergner@linux.ibm.com>
137
138 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
139 on POWER5 and later.
140
6a7f5766
AB		 1412021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
142
143 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
144 before an unknown instruction, '%d' is replaced with the
145 instruction length.
146
718aefcf
NC		 1472021-09-02 Nick Clifton <nickc@redhat.com>
148
149 PR 28292
150 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
151 of BFD_RELOC_16.
152
5d9cff51
SV		 1532021-08-17 Shahab Vahedi <shahab@synopsys.com>
154
155 * arc-regs.h (DEF): Fix the register numbers.
156
3ee0cd9e
NC		 1572021-08-10 Nick Clifton <nickc@redhat.com>
158
159 * po/sr.po: Updated Serbian translation.
160
8d56b9fc
CX		 1612021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
162
163 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
164
b180e829
AK		 1652021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
166
167 * s390-opc.txt: Add qpaci.
168
346d80ef
NC		 1692021-07-03 Nick Clifton <nickc@redhat.com>
170
171 * configure: Regenerate.
172 * po/opcodes.pot: Regenerate.
173
51419248
NC		 1742021-07-03 Nick Clifton <nickc@redhat.com>
175
176 * 2.37 release branch created.
177
62194b63
AM		 1782021-07-02 Alan Modra <amodra@gmail.com>
179
180 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
181 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
182 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
183 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
184 (nds32_keyword_gpr): Move declarations to..
185 * nds32-asm.h: ..here, constifying to match definitions.
186
2fe36d31
MF		 1872021-07-01 Mike Frysinger <vapier@gentoo.org>
188
189 * Makefile.am (GUILE): New variable.
190 (CGEN): Use $(GUILE).
191 * Makefile.in: Regenerate.
192
f375d32b
MF		 1932021-07-01 Mike Frysinger <vapier@gentoo.org>
194
195 * mep-asm.c (macros): Mark static & const.
196 (lookup_macro): Change return & m to const.
197 (expand_macro): Change mac to const.
198 (expand_string): Change pmacro to const.
199
9b2beaf7
MF		 2002021-07-01 Mike Frysinger <vapier@gentoo.org>
201
202 * nds32-asm.c (operand_fields): Rename to ...
203 (nds32_operand_fields): ... this.
204 (keyword_gpr): Rename to ...
205 (nds32_keyword_gpr): ... this.
206 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
207 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
208 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
209 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
210 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
211 Mark static.
212 (keywords): Rename to ...
213 (nds32_keywords): ... this.
214 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
215 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
216
ac8ef696
MF		 2172021-07-01 Mike Frysinger <vapier@gentoo.org>
218
219 * z80-dis.c (opc_ed): Make const.
220 (pref_ed): Make p const.
221
52b83874
MF		 2222021-07-01 Mike Frysinger <vapier@gentoo.org>
223
224 * microblaze-dis.c (get_field_special): Make op const.
225 (read_insn_microblaze): Make opr & op const. Rename opcodes to
226 microblaze_opcodes.
227 (print_insn_microblaze): Make op & pop const.
228 (get_insn_microblaze): Make op const. Rename opcodes to
229 microblaze_opcodes.
230 (microblaze_get_target_address): Likewise.
231 * microblaze-opc.h (struct op_code_struct): Make const.
232 Rename opcodes to microblaze_opcodes.
233
6c2ede01
MF		 2342021-07-01 Mike Frysinger <vapier@gentoo.org>
235
236 * aarch64-gen.c (aarch64_opcode_table): Add const.
237 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
238
46b8b3d6
AB		 2392021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
240
241 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
242 available.
243
ded5cb94
AM		 2442021-06-22 Alan Modra <amodra@gmail.com>
245
246 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
247 print separator for pcrel insns.
248
47399e9c
AM		 2492021-06-19 Alan Modra <amodra@gmail.com>
250
251 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
252
d984392e
AM		 2532021-06-19 Alan Modra <amodra@gmail.com>
254
255 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
256 entire buffer.
257
7993124e
AM		 2582021-06-17 Alan Modra <amodra@gmail.com>
259
260 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
261 in table.
262
a38d1396
AM		 2632021-06-03 Alan Modra <amodra@gmail.com>
264
265 PR 1202
266 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
267 Use unsigned int for inst.
268
8f467114
SV		 2692021-06-02 Shahab Vahedi <shahab@synopsys.com>
270
271 * arc-dis.c (arc_option_arg_t): New enumeration.
272 (arc_options): New variable.
273 (disassembler_options_arc): New function.
274 (print_arc_disassembler_options): Reimplement in terms of
275 "disassembler_options_arc".
276
1ff6a3b8
AM		 2772021-05-29 Alan Modra <amodra@gmail.com>
278
279 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
280 Don't special case PPC_OPCODE_RAW.
281 (lookup_prefix): Likewise.
282 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
283 (print_insn_powerpc): ..update caller.
284 * ppc-opc.c (EXT): Define.
285 (powerpc_opcodes): Mark extended mnemonics with EXT.
286 (prefix_opcodes, vle_opcodes): Likewise.
287 (XISEL, XISEL_MASK): Add cr field and simplify.
288 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
289 all isel variants to where the base mnemonic belongs. Sort dstt,
290 dststt and dssall.
291
49149d59
MR		 2922021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
293
294 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
295 COP3 opcode instructions.
296
9573a461
MR		 2972021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
298
299 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
300 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
301 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
302 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
303 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
304 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
305 "cop2", and "cop3" entries.
306
fa495743
MR		 3072021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
308
309 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
310 entries and associated comments.
311
b930964c
MR		 3122021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
313
314 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
315 of "c0".
316
dd844468
MR		 3172021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
318
319 * mips-dis.c (mips_cp1_names_mips): New variable.
320 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
321 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
322 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
323 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
324 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
325 "loongson2f".
326
9204ccd4
MR		 3272021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
328
329 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
330 handling code over to...
331 <OP_REG_CONTROL>: ... this new case.
332 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
333 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
334 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
335 replacing the `G' operand code with `g'. Update "cftc1" and
336 "cftc2" entries replacing the `E' operand code with `y'.
337 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
338 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
339 entries replacing the `G' operand code with `g'.
340
a3fb396f
MR		 3412021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
342
343 * mips-dis.c (mips_cp0_names_r3900): New variable.
344 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
345 for "r3900".
346
cccc84fa
MR		 3472021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
348
349 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
350 and "mtthc2" to using the `G' rather than `g' operand code for
351 the coprocessor control register referred.
352
c9de3168
MR		 3532021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
354
355 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
356 entries with each other.
357
ebcab741
PB		 3582021-05-27 Peter Bergner <bergner@linux.ibm.com>
359
360 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
361
bc30a119
AM		 3622021-05-25 Alan Modra <amodra@gmail.com>
363
364 * cris-desc.c: Regenerate.
365 * cris-desc.h: Regenerate.
366 * cris-opc.h: Regenerate.
367 * po/POTFILES.in: Regenerate.
368
54711280
MF		 3692021-05-24 Mike Frysinger <vapier@gentoo.org>
370
371 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
372 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
373 (CGEN_CPUS): Add cris.
374 (CRIS_DEPS): Define.
375 (stamp-cris): New rule.
376 * cgen.sh: Handle desc action.
377 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
378 * Makefile.in, configure: Regenerate.
379
113bb761
JN		 3802021-05-18 Job Noorman <mtvec@pm.me>
381
382 PR 27814
383 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
384 the elf objects.
385
e683cb41
AC		 3862021-05-17 Alex Coplan <alex.coplan@arm.com>
387
388 * arm-dis.c (mve_opcodes): Fix disassembly of
389 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
390 (is_mve_encoding_conflict): MVE vector loads should not match
391 when P = W = 0.
392 (is_mve_unpredictable): It's not unpredictable to use the same
393 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
394
a680affc
NC		 3952021-05-11 Nick Clifton <nickc@redhat.com>
396
397 PR 27840
398 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
399 the end of the code buffer.
400
0b3e14c9
SH		 4012021-05-06 Stafford Horne <shorne@gmail.com>
402
403 PR 21464
404 * or1k-asm.c: Regenerate.
405
6aee2cb2
MF		 4062021-05-01 Max Filippov <jcmvbkbc@gmail.com>
407
408 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
409 info->insn_info_valid.
410
fe134c65
JB		 4112021-04-26 Jan Beulich <jbeulich@suse.com>
412
413 * i386-opc.tbl (lea): Add Optimize.
414 * opcodes/i386-tbl.h: Re-generate.
415
b3ea7639
MF		 4162020-04-23 Max Filippov <jcmvbkbc@gmail.com>
417
418 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
419 of l32r fetch and display referenced literal value.
420
c1cbb7d8
MF		 4212021-04-23 Max Filippov <jcmvbkbc@gmail.com>
422
423 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
424 to 4 for literal disassembly.
425
02202574
PW		 4262021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
427
428 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
429 for TLBI instruction.
430
cd6608e4
PW		 4312021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
432
433 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
434 DC instruction.
435
fe1640ff
JB		 4362021-04-19 Jan Beulich <jbeulich@suse.com>
437
438 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
439 "qualifier".
440 (convert_mov_to_movewide): Add initializer for "value".
441
100e914d
PW		 4422021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
443
444 * aarch64-opc.c: Add RME system registers.
445
a21b96dd
NC		 4462021-04-16 Lifang Xia <lifang_xia@c-sky.com>
447
448 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
449 "addi d,CV,z" to "c.mv d,CV".
450
43e05cd4
AM		 4512021-04-12 Alan Modra <amodra@gmail.com>
452
453 * configure.ac (--enable-checking): Add support.
454 * config.in: Regenerate.
455 * configure: Regenerate.
456
52efda82
TB		 4572021-04-09 Tejas Belagod <tejas.belagod@arm.com>
458
459 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
460 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
461
c3f72de4
AM		 4622021-04-09 Alan Modra <amodra@gmail.com>
463
464 * ppc-dis.c (struct dis_private): Add "special".
465 (POWERPC_DIALECT): Delete. Replace uses with..
466 (private_data): ..this. New inline function.
467 (disassemble_init_powerpc): Init "special" names.
468 (skip_optional_operands): Add is_pcrel arg, set when detecting R
469 field of prefix instructions.
470 (bsearch_reloc, print_got_plt): New functions.
471 (print_insn_powerpc): For pcrel instructions, print target address
472 and symbol if known, and decode plt and got loads too.
473
ce7d813a
AM		 4742021-04-08 Alan Modra <amodra@gmail.com>
475
476 PR 27684
477 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
478
97bf40d8
AM		 4792021-04-08 Alan Modra <amodra@gmail.com>
480
481 PR 27676
482 * ppc-opc.c (DCBT_EO): Move earlier.
483 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
484 (powerpc_operands): Add THCT and THDS entries.
485 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
486
a2e66773
AM		 4872021-04-06 Alan Modra <amodra@gmail.com>
488
489 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
490 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
491 symbol_at_address_func.
492
ab2af25e
AM		 4932021-04-05 Alan Modra <amodra@gmail.com>
494
495 * configure.ac: Don't check for limits.h, string.h, strings.h or
496 stdlib.h.
497 (AC_ISC_POSIX): Don't invoke.
498 * sysdep.h: Include stdlib.h and string.h unconditionally.
499 * i386-opc.h: Include limits.h unconditionally.
500 * wasm32-dis.c: Likewise.
501 * cgen-opc.c: Don't include alloca-conf.h.
502 * config.in: Regenerate.
503 * configure: Regenerate.
504
e9b095a5
ML		 5052021-04-01 Martin Liska <mliska@suse.cz>
506
507 * arm-dis.c (strneq): Remove strneq and use startswith.
508 * cr16-dis.c (print_insn_cr16): Likewise.
509 * score-dis.c (streq): Likewise.
510 (strneq): Likewise.
511 * score7-dis.c (strneq): Likewise.
512
1cb108e4
AM		 5132021-04-01 Alan Modra <amodra@gmail.com>
514
515 PR 27675
516 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
517
78933a4a
AM		 5182021-03-31 Alan Modra <amodra@gmail.com>
519
520 * sysdep.h (POISON_BFD_BOOLEAN): Define.
521 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
522 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
523 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
524 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
525 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
526 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
527 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
528 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
529 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
530 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
531 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
532 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
533 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
534 and TRUE with true throughout.
535
3dfb1b6d
AM		 5362021-03-31 Alan Modra <amodra@gmail.com>
537
538 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
539 * aarch64-dis.h: Likewise.
540 * aarch64-opc.c: Likewise.
541 * avr-dis.c: Likewise.
542 * csky-dis.c: Likewise.
543 * nds32-asm.c: Likewise.
544 * nds32-dis.c: Likewise.
545 * nfp-dis.c: Likewise.
546 * riscv-dis.c: Likewise.
547 * s12z-dis.c: Likewise.
548 * wasm32-dis.c: Likewise.
549
5e042380
JB		 5502021-03-30 Jan Beulich <jbeulich@suse.com>
551
552 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
553 (i386_seg_prefixes): New.
554 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
555 (i386_seg_prefixes): Declare.
556
34684862
JB		 5572021-03-30 Jan Beulich <jbeulich@suse.com>
558
559 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
560
6288d05f
JB		 5612021-03-30 Jan Beulich <jbeulich@suse.com>
562
563 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
564 * i386-reg.tbl (st): Move down.
565 (st(0)): Delete. Extend comment.
566 * i386-tbl.h: Re-generate.
567
bbe1eca6
JB		 5682021-03-29 Jan Beulich <jbeulich@suse.com>
569
570 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
571 (cmpsd): Move next to cmps.
572 (movsd): Move next to movs.
573 (cmpxchg16b): Move to separate section.
574 (fisttp, fisttpll): Likewise.
575 (monitor, mwait): Likewise.
576 * i386-tbl.h: Re-generate.
577
c8cad9d3
JB		 5782021-03-29 Jan Beulich <jbeulich@suse.com>
579
580 * i386-opc.tbl (psadbw): Add <sse2:comm>.
581 (vpsadbw): Add C.
582 * i386-tbl.h: Re-generate.
583
5cdaf100
JB		 5842021-03-29 Jan Beulich <jbeulich@suse.com>
585
586 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
587 pclmul, gfni): New templates. Use them wherever possible. Move
588 SSE4.1 pextrw into respective section.
589 * i386-tbl.h: Re-generate.
590
73e45eb2
JB		 5912021-03-29 Jan Beulich <jbeulich@suse.com>
592
593 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
594 strtoull(). Bump upper loop bound. Widen masks. Sanity check
595 "length".
596 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
597 Convert all of their uses to representation in opcode.
598
9df6f676
JB		 5992021-03-29 Jan Beulich <jbeulich@suse.com>
600
601 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
602 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
603 value of None. Shrink operands to 3 bits.
604
389d00a5
JB		 6052021-03-29 Jan Beulich <jbeulich@suse.com>
606
607 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 608 "space".
389d00a5
JB		 609 (output_i386_opcode): New local variable "space". Adjust
610 process_i386_opcode_modifier() invocation.
611 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
612 invocation.
613 * i386-tbl.h: Re-generate.
614
63b4cc53
AM		 6152021-03-29 Alan Modra <amodra@gmail.com>
616
617 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
618 (fp_qualifier_p, get_data_pattern): Likewise.
619 (aarch64_get_operand_modifier_from_value): Likewise.
620 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
621 (operand_variant_qualifier_p): Likewise.
622 (qualifier_value_in_range_constraint_p): Likewise.
623 (aarch64_get_qualifier_esize): Likewise.
624 (aarch64_get_qualifier_nelem): Likewise.
625 (aarch64_get_qualifier_standard_value): Likewise.
626 (get_lower_bound, get_upper_bound): Likewise.
627 (aarch64_find_best_match, match_operands_qualifier): Likewise.
628 (aarch64_print_operand): Likewise.
629 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
630 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
631 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
632 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
633 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
634 (print_insn_tic6x): Likewise.
635
3d7d6c1b
AM		 6362021-03-29 Alan Modra <amodra@gmail.com>
637
638 * arc-dis.c (extract_operand_value): Correct NULL cast.
639 * frv-opc.h: Regenerate.
640
c3344b62
JB		 6412021-03-26 Jan Beulich <jbeulich@suse.com>
642
643 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
644 MMX form.
645 * i386-tbl.h: Re-generate.
646
efa30ac3
HAQ		 6472021-03-25 Abid Qadeer <abidh@codesourcery.com>
648
649 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
650 immediate in br.n instruction.
651
596a02ff
JB		 6522021-03-25 Jan Beulich <jbeulich@suse.com>
653
654 * i386-dis.c (XMGatherD, VexGatherD): New.
655 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
656 (print_insn): Check masking for S/G insns.
657 (OP_E_memory): New local variable check_gather. Extend mandatory
658 SIB check. Check register conflicts for (EVEX-encoded) gathers.
659 Extend check for disallowed 16-bit addressing.
660 (OP_VEX): New local variables modrm_reg and sib_index. Convert
661 if()s to switch(). Check register conflicts for (VEX-encoded)
662 gathers. Drop no longer reachable cases.
663 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
664 vgatherdp*.
665
53642852
JB		 6662021-03-25 Jan Beulich <jbeulich@suse.com>
667
668 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
669 zeroing-masking without masking.
670
c0e54661
JB		 6712021-03-25 Jan Beulich <jbeulich@suse.com>
672
673 * i386-opc.tbl (invlpgb): Fix multi-operand form.
674 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
675 single-operand forms as deprecated.
676 * i386-tbl.h: Re-generate.
677
5a403766
AM		 6782021-03-25 Alan Modra <amodra@gmail.com>
679
680 PR 27647
681 * ppc-opc.c (XLOCB_MASK): Delete.
682 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
683 XLBH_MASK.
684 (powerpc_opcodes): Accept a BH field on all extended forms of
685 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
686
9a182d04
JB		 6872021-03-24 Jan Beulich <jbeulich@suse.com>
688
689 * i386-gen.c (output_i386_opcode): Drop processing of
690 opcode_length. Calculate length from base_opcode. Adjust prefix
691 encoding determination.
692 (process_i386_opcodes): Drop output of fake opcode_length.
693 * i386-opc.h (struct insn_template): Drop opcode_length field.
694 * i386-opc.tbl: Drop opcode length field from all templates.
695 * i386-tbl.h: Re-generate.
696
35648716
JB		 6972021-03-24 Jan Beulich <jbeulich@suse.com>
698
699 * i386-gen.c (process_i386_opcode_modifier): Return void. New
700 parameter "prefix". Drop local variable "regular_encoding".
701 Record prefix setting / check for consistency.
702 (output_i386_opcode): Parse opcode_length and base_opcode
703 earlier. Derive prefix encoding. Drop no longer applicable
704 consistency checking. Adjust process_i386_opcode_modifier()
705 invocation.
706 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
707 invocation.
708 * i386-tbl.h: Re-generate.
709
31184569
JB		 7102021-03-24 Jan Beulich <jbeulich@suse.com>
711
712 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
713 check.
714 * i386-opc.h (Prefix_*): Move #define-s.
715 * i386-opc.tbl: Move pseudo prefix enumerator values to
716 extension opcode field. Introduce pseudopfx template.
717 * i386-tbl.h: Re-generate.
718
b933fa4b
JB		 7192021-03-23 Jan Beulich <jbeulich@suse.com>
720
721 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
722 comment.
723 * i386-tbl.h: Re-generate.
724
dac10fb0
JB		 7252021-03-23 Jan Beulich <jbeulich@suse.com>
726
727 * i386-opc.h (struct insn_template): Move cpu_flags field past
728 opcode_modifier one.
729 * i386-tbl.h: Re-generate.
730
441f6aca
JB		 7312021-03-23 Jan Beulich <jbeulich@suse.com>
732
733 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
734 * i386-opc.h (OpcodeSpace): New enumerator.
735 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
736 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
737 SPACE_XOP09, SPACE_XOP0A): ... respectively.
738 (struct i386_opcode_modifier): New field opcodespace. Shrink
739 opcodeprefix field.
740 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
741 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
742 OpcodePrefix uses.
743 * i386-tbl.h: Re-generate.
744
08dedd66
ML		 7452021-03-22 Martin Liska <mliska@suse.cz>
746
747 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
748 * arc-dis.c (parse_option): Likewise.
749 * arm-dis.c (parse_arm_disassembler_options): Likewise.
750 * cris-dis.c (print_with_operands): Likewise.
751 * h8300-dis.c (bfd_h8_disassemble): Likewise.
752 * i386-dis.c (print_insn): Likewise.
753 * ia64-gen.c (fetch_insn_class): Likewise.
754 (parse_resource_users): Likewise.
755 (in_iclass): Likewise.
756 (lookup_specifier): Likewise.
757 (insert_opcode_dependencies): Likewise.
758 * mips-dis.c (parse_mips_ase_option): Likewise.
759 (parse_mips_dis_option): Likewise.
760 * s390-dis.c (disassemble_init_s390): Likewise.
761 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
762
80d49d6a
KLC		 7632021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
764
765 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
766
7fce7ea9
PW		 7672021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
768
769 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
770 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
771
78c84bf9
AM		 7722021-03-12 Alan Modra <amodra@gmail.com>
773
774 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
775
fd1fd061
JB		 7762021-03-11 Jan Beulich <jbeulich@suse.com>
777
778 * i386-dis.c (OP_XMM): Re-order checks.
779
ac7a2311
JB		 7802021-03-11 Jan Beulich <jbeulich@suse.com>
781
782 * i386-dis.c (putop): Drop need_vex check when also checking
783 vex.evex.
784 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
785 checking vex.b.
786
da944c8a
JB		 7872021-03-11 Jan Beulich <jbeulich@suse.com>
788
789 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
790 checks. Move case label past broadcast check.
791
b763d508
JB		 7922021-03-10 Jan Beulich <jbeulich@suse.com>
793
794 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
795 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
796 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
797 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
798 EVEX_W_0F38C7_M_0_L_2): Delete.
799 (REG_EVEX_0F38C7_M_0_L_2): New.
800 (intel_operand_size): Handle VEX and EVEX the same for
801 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
802 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
803 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
804 vex_vsib_q_w_d_mode uses.
805 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
806 0F38A1, and 0F38A3 entries.
807 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
808 entry.
809 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
810 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
811 0F38A3 entries.
812
32e31ad7
JB		 8132021-03-10 Jan Beulich <jbeulich@suse.com>
814
815 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
816 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
817 MOD_VEX_0FXOP_09_12): Rename to ...
818 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
819 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
820 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
821 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
822 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
823 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
824 (reg_table): Adjust comments.
825 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
826 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
827 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
828 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
829 (vex_len_table): Adjust opcode 0A_12 entry.
830 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
831 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
832 (rm_table): Move hreset entry.
833
85ba7507
JB		 8342021-03-10 Jan Beulich <jbeulich@suse.com>
835
836 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
837 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
838 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
839 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
840 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
841 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
842 (get_valid_dis386): Also handle 512-bit vector length when
843 vectoring into vex_len_table[].
844 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
845 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
846 entries.
847 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
848 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
849 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
850 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
851 entries.
852
066f82b9
JB		 8532021-03-10 Jan Beulich <jbeulich@suse.com>
854
855 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
856 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
857 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
858 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
859 entries.
860 * i386-dis-evex-len.h (evex_len_table): Likewise.
861 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
862
fc681dd6
JB		 8632021-03-10 Jan Beulich <jbeulich@suse.com>
864
865 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
866 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
867 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
868 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
869 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
870 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
871 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
872 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
873 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
874 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
875 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
876 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
877 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
878 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
879 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
880 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
881 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
882 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
883 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
884 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
885 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
886 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
887 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
888 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
889 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
890 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
891 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
892 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
893 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
894 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
895 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
896 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
897 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
898 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
899 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
900 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
901 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
902 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
903 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
904 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
905 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
906 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
907 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
908 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
909 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
910 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
911 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
912 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
913 EVEX_W_0F3A43_L_n): New.
914 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
915 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
916 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
917 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
918 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
919 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
920 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
921 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
922 0F385B, 0F38C6, and 0F38C7 entries.
923 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
924 0F38C6 and 0F38C7.
925 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
926 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
927 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
928 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
929
13954a31
JB		 9302021-03-10 Jan Beulich <jbeulich@suse.com>
931
932 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
933 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
934 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
935 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
936 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
937 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
938 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
939 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
940 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
941 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
942 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
943 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
944 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
945 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
946 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
947 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
948 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
949 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
950 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
951 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
952 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
953 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
954 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
955 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
956 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
957 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
958 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
959 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
960 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
961 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
962 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
963 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
964 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
965 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
966 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
967 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
968 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
969 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
970 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
971 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
972 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
973 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
974 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
975 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
976 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
977 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
978 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
979 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
980 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
981 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
982 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
983 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
984 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
985 VEX_W_0F99_P_2_LEN_0): Delete.
986 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
987 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
988 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
989 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
990 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
991 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
992 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
993 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
994 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
995 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
996 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
997 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
998 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
999 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1000 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1001 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1002 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1003 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1004 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1005 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1006 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1007 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1008 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1009 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1010 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1011 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1012 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1013 (prefix_table): No longer link to vex_len_table[] for opcodes
1014 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1015 0F92, 0F93, 0F98, and 0F99.
1016 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1017 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1018 0F98, and 0F99.
1019 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1020 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1021 0F98, and 0F99.
1022 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1023 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1024 0F98, and 0F99.
1025 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1026 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1027 0F98, and 0F99.
1028
14d10c6c
JB		 10292021-03-10 Jan Beulich <jbeulich@suse.com>
1030
1031 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1032 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1033 REG_VEX_0F73_M_0 respectively.
1034 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1035 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1036 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1037 MOD_VEX_0F73_REG_7): Delete.
1038 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1039 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1040 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1041 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1042 PREFIX_VEX_0F3AF0_L_0 respectively.
1043 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1044 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1045 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1046 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1047 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1048 VEX_LEN_0F38F7): New.
1049 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1050 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1051 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1052 0F38F3.
1053 (prefix_table): No longer link to vex_len_table[] for opcodes
1054 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1055 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1056 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1057 0F38F6, 0F38F7, and 0F3AF0.
1058 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1059 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1060 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1061 0F73.
1062
00ec1875
JB		 10632021-03-10 Jan Beulich <jbeulich@suse.com>
1064
1065 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1066 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1067 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1068 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1069 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1070 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1071 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1072 73.
1073 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1074 0F72, and 0F73.
1075 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1076 0F73.
1077
31941983
JB		 10782021-03-10 Jan Beulich <jbeulich@suse.com>
1079
1080 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1081 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1082 (reg_table): Don't link to mod_table[] where not needed. Add
1083 PREFIX_IGNORED to nop entries.
1084 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1085 (mod_table): Add nop entries next to prefetch ones. Drop
1086 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1087 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1088 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1089 PREFIX_OPCODE from endbr* entries.
1090 (get_valid_dis386): Also consider entry's name when zapping
1091 vindex.
1092 (print_insn): Handle PREFIX_IGNORED.
1093
742732c7
JB		 10942021-03-09 Jan Beulich <jbeulich@suse.com>
1095
1096 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1097 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1098 element.
1099 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1100 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1101 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1102 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1103 (struct i386_opcode_modifier): Delete notrackprefixok,
1104 islockable, hleprefixok, and repprefixok fields. Add prefixok
1105 field.
1106 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1107 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1108 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1109 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1110 Replace HLEPrefixOk.
1111 * opcodes/i386-tbl.h: Re-generate.
1112
e93a3b27
JB		 11132021-03-09 Jan Beulich <jbeulich@suse.com>
1114
1115 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1116 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1117 64-bit form.
1118 * opcodes/i386-tbl.h: Re-generate.
1119
75363b6d
JB		 11202021-03-03 Jan Beulich <jbeulich@suse.com>
1121
1122 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1123 for {} instead of {0}. Don't look for '0'.
1124 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1125 size specifiers.
1126
5a9f5403
NC		 11272021-02-19 Nelson Chu <nelson.chu@sifive.com>
1128
1129 PR 27158
1130 * riscv-dis.c (print_insn_args): Updated encoding macros.
1131 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1132 (match_c_addi16sp): Updated encoding macros.
1133 (match_c_lui): Likewise.
1134 (match_c_lui_with_hint): Likewise.
1135 (match_c_addi4spn): Likewise.
1136 (match_c_slli): Likewise.
1137 (match_slli_as_c_slli): Likewise.
1138 (match_c_slli64): Likewise.
1139 (match_srxi_as_c_srxi): Likewise.
1140 (riscv_insn_types): Added .insn css/cl/cs.
1141
3d73d29e
NC		 11422021-02-18 Nelson Chu <nelson.chu@sifive.com>
1143
1144 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1145 (default_priv_spec): Updated type to riscv_spec_class.
1146 (parse_riscv_dis_option): Updated.
1147 * riscv-opc.c: Moved stuff and make the file tidy.
1148
b9b204b3
AM		 11492021-02-17 Alan Modra <amodra@gmail.com>
1150
1151 * wasm32-dis.c: Include limits.h.
1152 (CHAR_BIT): Provide backup define.
1153 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1154 Correct signed overflow checking.
1155
394ae71f
JB		 11562021-02-16 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1159 * i386-tbl.h: Re-generate.
1160
b818b220
JB		 11612021-02-16 Jan Beulich <jbeulich@suse.com>
1162
1163 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1164 Oword.
1165 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1166
ba2b480f
AK		 11672021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1168
1169 * s390-mkopc.c (main): Accept arch14 as cpu string.
1170 * s390-opc.txt: Add new arch14 instructions.
1171
95148614
NA		 11722021-02-04 Nick Alcock <nick.alcock@oracle.com>
1173
1174 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1175 favour of LIBINTL.
1176 * configure: Regenerated.
1177
bfd428bc
MF		 11782021-02-08 Mike Frysinger <vapier@gentoo.org>
1179
1180 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1181 * tic54x-opc.c (regs): Rename to ...
1182 (tic54x_regs): ... this.
1183 (mmregs): Rename to ...
1184 (tic54x_mmregs): ... this.
1185 (condition_codes): Rename to ...
1186 (tic54x_condition_codes): ... this.
1187 (cc2_codes): Rename to ...
1188 (tic54x_cc2_codes): ... this.
1189 (cc3_codes): Rename to ...
1190 (tic54x_cc3_codes): ... this.
1191 (status_bits): Rename to ...
1192 (tic54x_status_bits): ... this.
1193 (misc_symbols): Rename to ...
1194 (tic54x_misc_symbols): ... this.
1195
24075dcc
NC		 11962021-02-04 Nelson Chu <nelson.chu@sifive.com>
1197
1198 * riscv-opc.c (MASK_RVB_IMM): Removed.
1199 (riscv_opcodes): Removed zb* instructions.
1200 (riscv_ext_version_table): Removed versions for zb*.
1201
c3ffb8f3
AM		 12022021-01-26 Alan Modra <amodra@gmail.com>
1203
1204 * i386-gen.c (parse_template): Ensure entire template_instance
1205 is initialised.
1206
1942a048
NC		 12072021-01-15 Nelson Chu <nelson.chu@sifive.com>
1208
1209 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1210 (riscv_fpr_names_abi): Likewise.
1211 (riscv_opcodes): Likewise.
1212 (riscv_insn_types): Likewise.
1213
b800637e
NC		 12142021-01-15 Nelson Chu <nelson.chu@sifive.com>
1215
1216 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1217
dcd709e0
NC		 12182021-01-15 Nelson Chu <nelson.chu@sifive.com>
1219
1220 * riscv-dis.c: Comments tidy and improvement.
1221 * riscv-opc.c: Likewise.
1222
5347ed60
AM		 12232021-01-13 Alan Modra <amodra@gmail.com>
1224
1225 * Makefile.in: Regenerate.
1226
d546b610
L		 12272021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 PR binutils/26792
1230 * configure.ac: Use GNU_MAKE_JOBSERVER.
1231 * aclocal.m4: Regenerated.
1232 * configure: Likewise.
1233
6d104cac
NC		 12342021-01-12 Nick Clifton <nickc@redhat.com>
1235
1236 * po/sr.po: Updated Serbian translation.
1237
83b33c6c
L		 12382021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1239
1240 PR ld/27173
1241 * configure: Regenerated.
1242
82c70b08
KT		 12432021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1244
1245 * aarch64-asm-2.c: Regenerate.
1246 * aarch64-dis-2.c: Likewise.
1247 * aarch64-opc-2.c: Likewise.
1248 * aarch64-opc.c (aarch64_print_operand):
1249 Delete handling of AARCH64_OPND_CSRE_CSR.
1250 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1251 (CSRE): Likewise.
1252 (_CSRE_INSN): Likewise.
1253 (aarch64_opcode_table): Delete csr.
1254
a8aa72b9
NC		 12552021-01-11 Nick Clifton <nickc@redhat.com>
1256
1257 * po/de.po: Updated German translation.
1258 * po/fr.po: Updated French translation.
1259 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1260 * po/sv.po: Updated Swedish translation.
1261 * po/uk.po: Updated Ukranian translation.
1262
a4966cd9
L		 12632021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1264
1265 * configure: Regenerated.
1266
573fe3fb
NC		 12672021-01-09 Nick Clifton <nickc@redhat.com>
1268
1269 * configure: Regenerate.
1270 * po/opcodes.pot: Regenerate.
1271
055bc77a
NC		 12722021-01-09 Nick Clifton <nickc@redhat.com>
1273
1274 * 2.36 release branch crated.
1275
aae7fcb8
PB		 12762021-01-08 Peter Bergner <bergner@linux.ibm.com>
1277
1278 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1279 (DW, (XRC_MASK): Define.
1280 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1281
64307045
AM		 12822021-01-09 Alan Modra <amodra@gmail.com>
1283
1284 * configure: Regenerate.
1285
ed205222
NC		 12862021-01-08 Nick Clifton <nickc@redhat.com>
1287
1288 * po/sv.po: Updated Swedish translation.
1289
fb932b57
NC		 12902021-01-08 Nick Clifton <nickc@redhat.com>
1291
e84c8716
NC		 1292 PR 27129
1293 * aarch64-dis.c (determine_disassembling_preference): Move call to
1294 aarch64_match_operands_constraint outside of the assertion.
1295 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1296 Replace with a return of FALSE.
1297
fb932b57
NC		 1298 PR 27139
1299 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1300 core system register.
1301
f4782128
ST		 13022021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1303
1304 * configure: Regenerate.
1305
1b0927db
NC		 13062021-01-07 Nick Clifton <nickc@redhat.com>
1307
1308 * po/fr.po: Updated French translation.
1309
3b288c8e
FN		 13102021-01-07 Fredrik Noring <noring@nocrew.org>
1311
1312 * m68k-opc.c (chkl): Change minimum architecture requirement to
1313 m68020.
1314
aa881ecd
PT		 13152021-01-07 Philipp Tomsich <prt@gnu.org>
1316
1317 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1318
2652cfad
CXW		 13192021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1320 Jim Wilson <jimw@sifive.com>
1321 Andrew Waterman <andrew@sifive.com>
1322 Maxim Blinov <maxim.blinov@embecosm.com>
1323 Kito Cheng <kito.cheng@sifive.com>
1324 Nelson Chu <nelson.chu@sifive.com>
1325
1326 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1327 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1328
250d07de
AM		 13292021-01-01 Alan Modra <amodra@gmail.com>
1330
1331 Update year range in copyright notice of all files.
1332
c2795844 1333For older changes see ChangeLog-2020
3499769a 1334\f
d87bef3a 1335Copyright (C) 2021-2023 Free Software Foundation, Inc.
3499769a
AM		 1336
1337Copying and distribution of this file, with or without modification,
1338are permitted in any medium without royalty provided the copyright
1339notice and this notice are preserved.
1340
1341Local Variables:
1342mode: change-log
1343left-margin: 8
1344fill-column: 74
1345version-control: never
1346End:
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