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b5c37946 12023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com>
5b512234 2
b5c37946
SJ		 3 PR 30705
4 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
5 actually available before using it.
6
72023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
8
9 * bpf-dis.c: Initialize asm_bpf_version to -1.
10 (print_insn_bpf): Set BPF ISA version from the cpu version ELF
11 header flags if no explicit version set in the command line.
12 * disassemble.c (disassemble_init_for_target): Remove unused code.
13
142023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
15
16 * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
17 register.
18
192023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
20
21 * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
22 instructions.
23
242023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
25
26 * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
27 instructions.
28
292023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
30
31 * bpf-opc.c (bpf_opcodes): Add entry for jal.
32
332023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
34
35 * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
36 instructions.
37
382023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
39
40 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
41 MOVS32{8,16,32}R instructions. and MOVS32I instructions.
42
432023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
44
45 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
46 * Makefile.in: Regenerate.
386d3059 47
87485f53
NC		 482023-07-03 Nick Clifton <nickc@redhat.com>
49
50 * configure: Regenerate.
51 * po/opcodes.pot: Regenerate.
52
d501d384
NC		 532023-07-03 Nick Clifton <nickc@redhat.com>
54
55 2.41 Branch Point.
56
d595715a
NC		 572023-05-23 Nick Clifton <nickc@redhat.com>
58
59 * po/sv.po: Updated translation.
60
da9a978a
TT		 612023-04-21 Tom Tromey <tromey@adacore.com>
62
63 * i386-dis.c (OP_J): Check result of get16.
64
4bbb4dfb
CZ		 652023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
66
67 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
68 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
69 vsubs2h, and vsubs4h instructions.
70
37522c87
NC		 712023-04-11 Nick Clifton <nickc@redhat.com>
72
73 PR 30310
74 * nfp-dis.c (init_nfp6000_priv): Check that the output section
75 exists.
76
71f646f2
NC		 772023-03-15 Nick Clifton <nickc@redhat.com>
78
79 PR 30231
80 * mep-dis.c: Regenerate.
81
77186045
NC		 822023-03-15 Nick Clifton <nickc@redhat.com>
83
84 PR 30230
85 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
86
31f2faf5
RB		 872023-02-28 Richard Ball <richard.ball@arm.com>
88
89 * aarch64-opc.c: Add MEC system registers.
90
11982f9f
NC		 912023-01-03 Nick Clifton <nickc@redhat.com>
92
93 * po/de.po: Updated German translation.
94 * po/ro.po: Updated Romainian translation.
95 * po/uk.po: Updated Ukrainian translation.
96
a72b0718
NC		 972022-12-31 Nick Clifton <nickc@redhat.com>
98
99 * 2.40 branch created.
100
b2059307
SV		 1012022-11-22 Shahab Vahedi <shahab@synopsys.com>
102
103 * arc-regs.h: Change isa_config address to 0xc1.
104 isa_config exists for ARC700 and ARCV2 and not ARCALL.
105
de1fbe78
YS		 1062022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
107
108 * rx-decode.opc: Switch arguments of the MVTACGU insn.
109 * rx-decode.c: Regenerate.
110
3b8e069a
YS		 1112022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
112
113 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
114 Rm_BANK,Rn is always 1.
115
c07ec968
PB		 1162022-07-21 Peter Bergner <bergner@linux.ibm.com>
117
118 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
119 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
120 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
121 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
122 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
123 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
124 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
125
bbcab336
CZ		 1262022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
127
128 * disassemble.c (disassemble_init_for_target): Set
129 created_styled_output for ARC based targets.
130 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
131 instead of fprintf_ftype throughout.
132 (find_format): Likewise.
133 (print_flags): Likewise.
134 (print_insn_arc): Likewise.
135
0bd09323
NC		 1362022-07-08 Nick Clifton <nickc@redhat.com>
137
138 * 2.39 branch created.
139
a0f3a4c6
MN		 1402022-07-04 Marcus Nilsson <brainbomb@gmail.com>
141
142 * disassemble.c: (disassemble_init_for_target): Set
143 created_styled_output for AVR based targets.
144 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
145 instead of fprintf_ftype throughout.
146 (avr_operand): Pass in and fill disassembler_style when
147 parsing operands.
148
69341966
AK		 1492022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
150
151 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
152 table.
153
e3161106
SM		 1542022-03-16 Simon Marchi <simon.marchi@efficios.com>
155
156 * configure.ac: Handle bfd_amdgcn_arch.
157 * configure: Re-generate.
158
d17e797f
MR		 1592022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
160 Maciej W. Rozycki <macro@orcam.me.uk>
161
162 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
163 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
164 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
165 "bnez" instructions.
166
36d285b9
NC		 1672022-02-17 Nick Clifton <nickc@redhat.com>
168
169 * po/sr.po: Updated Serbian translation.
170
a532eb72
ST		 1712022-02-14 Sergei Trofimovich <siarheit@google.com>
172
173 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
174 * microblaze-opc.h: Follow 'fsqrt' rename.
175
5fe73d46
NC		 1762022-01-24 Nick Clifton <nickc@redhat.com>
177
178 * po/ro.po: Updated Romanian translation.
179 * po/uk.po: Updated Ukranian translation.
180
f908e960
NC		 1812022-01-22 Nick Clifton <nickc@redhat.com>
182
183 * configure: Regenerate.
184 * po/opcodes.pot: Regenerate.
185
a74e1cb3
NC		 1862022-01-22 Nick Clifton <nickc@redhat.com>
187
188 * 2.38 release branch created.
189
6c037fdb
NC		 1902022-01-17 Nick Clifton <nickc@redhat.com>
191
192 * Makefile.in: Regenerate.
193 * po/opcodes.pot: Regenerate.
194
96c7115a
MN		 1952021-12-02 Marcus Nilsson <brainbomb@gmail.com>
196
197 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
198 in insn_type on branching instructions.
199
3a337a86
AB		 2002021-11-25 Andrew Burgess <aburgess@redhat.com>
201 Simon Cook <simon.cook@embecosm.com>
202
203 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
204 (riscv_options): New static global.
205 (disassembler_options_riscv): New function.
206 (print_riscv_disassembler_options): Rewrite to use
207 disassembler_options_riscv.
208
7060c28e
NC		 2092021-11-25 Nick Clifton <nickc@redhat.com>
210
211 PR 28614
212 * aarch64-asm.c: Replace assert(0) with real code.
213 * aarch64-dis.c: Likewise.
214 * aarch64-opc.c: Likewise.
215
79abb939
NC		 2162021-11-25 Nick Clifton <nickc@redhat.com>
217
218 * po/fr.po; Updated French translation.
219
2b677209
MR		 2202021-10-27 Maciej W. Rozycki <macro@embecosm.com>
221
222 * Makefile.am: Remove obsolete comment.
223 * configure.ac: Refer `libbfd.la' to link shared BFD library
224 except for Cygwin.
225 * Makefile.in: Regenerate.
226 * configure: Regenerate.
227
b9004024
NA		 2282021-09-27 Nick Alcock <nick.alcock@oracle.com>
229
230 * configure: Regenerate.
231
4d5d5d46
PB		 2322021-09-25 Peter Bergner <bergner@linux.ibm.com>
233
234 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
235 on POWER5 and later.
236
6a7f5766
AB		 2372021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
238
239 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
240 before an unknown instruction, '%d' is replaced with the
241 instruction length.
242
718aefcf
NC		 2432021-09-02 Nick Clifton <nickc@redhat.com>
244
245 PR 28292
246 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
247 of BFD_RELOC_16.
248
5d9cff51
SV		 2492021-08-17 Shahab Vahedi <shahab@synopsys.com>
250
251 * arc-regs.h (DEF): Fix the register numbers.
252
3ee0cd9e
NC		 2532021-08-10 Nick Clifton <nickc@redhat.com>
254
255 * po/sr.po: Updated Serbian translation.
256
8d56b9fc
CX		 2572021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
258
259 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
260
b180e829
AK		 2612021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
262
263 * s390-opc.txt: Add qpaci.
264
346d80ef
NC		 2652021-07-03 Nick Clifton <nickc@redhat.com>
266
267 * configure: Regenerate.
268 * po/opcodes.pot: Regenerate.
269
51419248
NC		 2702021-07-03 Nick Clifton <nickc@redhat.com>
271
272 * 2.37 release branch created.
273
62194b63
AM		 2742021-07-02 Alan Modra <amodra@gmail.com>
275
276 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
277 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
278 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
279 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
280 (nds32_keyword_gpr): Move declarations to..
281 * nds32-asm.h: ..here, constifying to match definitions.
282
2fe36d31
MF		 2832021-07-01 Mike Frysinger <vapier@gentoo.org>
284
285 * Makefile.am (GUILE): New variable.
286 (CGEN): Use $(GUILE).
287 * Makefile.in: Regenerate.
288
f375d32b
MF		 2892021-07-01 Mike Frysinger <vapier@gentoo.org>
290
291 * mep-asm.c (macros): Mark static & const.
292 (lookup_macro): Change return & m to const.
293 (expand_macro): Change mac to const.
294 (expand_string): Change pmacro to const.
295
9b2beaf7
MF		 2962021-07-01 Mike Frysinger <vapier@gentoo.org>
297
298 * nds32-asm.c (operand_fields): Rename to ...
299 (nds32_operand_fields): ... this.
300 (keyword_gpr): Rename to ...
301 (nds32_keyword_gpr): ... this.
302 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
303 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
304 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
305 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
306 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
307 Mark static.
308 (keywords): Rename to ...
309 (nds32_keywords): ... this.
310 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
311 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
312
ac8ef696
MF		 3132021-07-01 Mike Frysinger <vapier@gentoo.org>
314
315 * z80-dis.c (opc_ed): Make const.
316 (pref_ed): Make p const.
317
52b83874
MF		 3182021-07-01 Mike Frysinger <vapier@gentoo.org>
319
320 * microblaze-dis.c (get_field_special): Make op const.
321 (read_insn_microblaze): Make opr & op const. Rename opcodes to
322 microblaze_opcodes.
323 (print_insn_microblaze): Make op & pop const.
324 (get_insn_microblaze): Make op const. Rename opcodes to
325 microblaze_opcodes.
326 (microblaze_get_target_address): Likewise.
327 * microblaze-opc.h (struct op_code_struct): Make const.
328 Rename opcodes to microblaze_opcodes.
329
6c2ede01
MF		 3302021-07-01 Mike Frysinger <vapier@gentoo.org>
331
332 * aarch64-gen.c (aarch64_opcode_table): Add const.
333 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
334
46b8b3d6
AB		 3352021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
336
337 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
338 available.
339
ded5cb94
AM		 3402021-06-22 Alan Modra <amodra@gmail.com>
341
342 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
343 print separator for pcrel insns.
344
47399e9c
AM		 3452021-06-19 Alan Modra <amodra@gmail.com>
346
347 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
348
d984392e
AM		 3492021-06-19 Alan Modra <amodra@gmail.com>
350
351 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
352 entire buffer.
353
7993124e
AM		 3542021-06-17 Alan Modra <amodra@gmail.com>
355
356 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
357 in table.
358
a38d1396
AM		 3592021-06-03 Alan Modra <amodra@gmail.com>
360
361 PR 1202
362 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
363 Use unsigned int for inst.
364
8f467114
SV		 3652021-06-02 Shahab Vahedi <shahab@synopsys.com>
366
367 * arc-dis.c (arc_option_arg_t): New enumeration.
368 (arc_options): New variable.
369 (disassembler_options_arc): New function.
370 (print_arc_disassembler_options): Reimplement in terms of
371 "disassembler_options_arc".
372
1ff6a3b8
AM		 3732021-05-29 Alan Modra <amodra@gmail.com>
374
375 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
376 Don't special case PPC_OPCODE_RAW.
377 (lookup_prefix): Likewise.
378 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
379 (print_insn_powerpc): ..update caller.
380 * ppc-opc.c (EXT): Define.
381 (powerpc_opcodes): Mark extended mnemonics with EXT.
382 (prefix_opcodes, vle_opcodes): Likewise.
383 (XISEL, XISEL_MASK): Add cr field and simplify.
384 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
385 all isel variants to where the base mnemonic belongs. Sort dstt,
386 dststt and dssall.
387
49149d59
MR		 3882021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
389
390 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
391 COP3 opcode instructions.
392
9573a461
MR		 3932021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
394
395 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
396 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
397 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
398 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
399 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
400 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
401 "cop2", and "cop3" entries.
402
fa495743
MR		 4032021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
404
405 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
406 entries and associated comments.
407
b930964c
MR		 4082021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
409
410 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
411 of "c0".
412
dd844468
MR		 4132021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
414
415 * mips-dis.c (mips_cp1_names_mips): New variable.
416 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
417 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
418 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
419 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
420 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
421 "loongson2f".
422
9204ccd4
MR		 4232021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
424
425 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
426 handling code over to...
427 <OP_REG_CONTROL>: ... this new case.
428 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
429 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
430 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
431 replacing the `G' operand code with `g'. Update "cftc1" and
432 "cftc2" entries replacing the `E' operand code with `y'.
433 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
434 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
435 entries replacing the `G' operand code with `g'.
436
a3fb396f
MR		 4372021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
438
439 * mips-dis.c (mips_cp0_names_r3900): New variable.
440 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
441 for "r3900".
442
cccc84fa
MR		 4432021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
444
445 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
446 and "mtthc2" to using the `G' rather than `g' operand code for
447 the coprocessor control register referred.
448
c9de3168
MR		 4492021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
450
451 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
452 entries with each other.
453
ebcab741
PB		 4542021-05-27 Peter Bergner <bergner@linux.ibm.com>
455
456 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
457
bc30a119
AM		 4582021-05-25 Alan Modra <amodra@gmail.com>
459
460 * cris-desc.c: Regenerate.
461 * cris-desc.h: Regenerate.
462 * cris-opc.h: Regenerate.
463 * po/POTFILES.in: Regenerate.
464
54711280
MF		 4652021-05-24 Mike Frysinger <vapier@gentoo.org>
466
467 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
468 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
469 (CGEN_CPUS): Add cris.
470 (CRIS_DEPS): Define.
471 (stamp-cris): New rule.
472 * cgen.sh: Handle desc action.
473 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
474 * Makefile.in, configure: Regenerate.
475
113bb761
JN		 4762021-05-18 Job Noorman <mtvec@pm.me>
477
478 PR 27814
479 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
480 the elf objects.
481
e683cb41
AC		 4822021-05-17 Alex Coplan <alex.coplan@arm.com>
483
484 * arm-dis.c (mve_opcodes): Fix disassembly of
485 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
486 (is_mve_encoding_conflict): MVE vector loads should not match
487 when P = W = 0.
488 (is_mve_unpredictable): It's not unpredictable to use the same
489 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
490
a680affc
NC		 4912021-05-11 Nick Clifton <nickc@redhat.com>
492
493 PR 27840
494 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
495 the end of the code buffer.
496
0b3e14c9
SH		 4972021-05-06 Stafford Horne <shorne@gmail.com>
498
499 PR 21464
500 * or1k-asm.c: Regenerate.
501
6aee2cb2
MF		 5022021-05-01 Max Filippov <jcmvbkbc@gmail.com>
503
504 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
505 info->insn_info_valid.
506
fe134c65
JB		 5072021-04-26 Jan Beulich <jbeulich@suse.com>
508
509 * i386-opc.tbl (lea): Add Optimize.
510 * opcodes/i386-tbl.h: Re-generate.
511
b3ea7639
MF		 5122020-04-23 Max Filippov <jcmvbkbc@gmail.com>
513
514 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
515 of l32r fetch and display referenced literal value.
516
c1cbb7d8
MF		 5172021-04-23 Max Filippov <jcmvbkbc@gmail.com>
518
519 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
520 to 4 for literal disassembly.
521
02202574
PW		 5222021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
523
524 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
525 for TLBI instruction.
526
cd6608e4
PW		 5272021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
528
529 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
530 DC instruction.
531
fe1640ff
JB		 5322021-04-19 Jan Beulich <jbeulich@suse.com>
533
534 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
535 "qualifier".
536 (convert_mov_to_movewide): Add initializer for "value".
537
100e914d
PW		 5382021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
539
540 * aarch64-opc.c: Add RME system registers.
541
a21b96dd
NC		 5422021-04-16 Lifang Xia <lifang_xia@c-sky.com>
543
544 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
545 "addi d,CV,z" to "c.mv d,CV".
546
43e05cd4
AM		 5472021-04-12 Alan Modra <amodra@gmail.com>
548
549 * configure.ac (--enable-checking): Add support.
550 * config.in: Regenerate.
551 * configure: Regenerate.
552
52efda82
TB		 5532021-04-09 Tejas Belagod <tejas.belagod@arm.com>
554
555 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
556 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
557
c3f72de4
AM		 5582021-04-09 Alan Modra <amodra@gmail.com>
559
560 * ppc-dis.c (struct dis_private): Add "special".
561 (POWERPC_DIALECT): Delete. Replace uses with..
562 (private_data): ..this. New inline function.
563 (disassemble_init_powerpc): Init "special" names.
564 (skip_optional_operands): Add is_pcrel arg, set when detecting R
565 field of prefix instructions.
566 (bsearch_reloc, print_got_plt): New functions.
567 (print_insn_powerpc): For pcrel instructions, print target address
568 and symbol if known, and decode plt and got loads too.
569
ce7d813a
AM		 5702021-04-08 Alan Modra <amodra@gmail.com>
571
572 PR 27684
573 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
574
97bf40d8
AM		 5752021-04-08 Alan Modra <amodra@gmail.com>
576
577 PR 27676
578 * ppc-opc.c (DCBT_EO): Move earlier.
579 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
580 (powerpc_operands): Add THCT and THDS entries.
581 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
582
a2e66773
AM		 5832021-04-06 Alan Modra <amodra@gmail.com>
584
585 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
586 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
587 symbol_at_address_func.
588
ab2af25e
AM		 5892021-04-05 Alan Modra <amodra@gmail.com>
590
591 * configure.ac: Don't check for limits.h, string.h, strings.h or
592 stdlib.h.
593 (AC_ISC_POSIX): Don't invoke.
594 * sysdep.h: Include stdlib.h and string.h unconditionally.
595 * i386-opc.h: Include limits.h unconditionally.
596 * wasm32-dis.c: Likewise.
597 * cgen-opc.c: Don't include alloca-conf.h.
598 * config.in: Regenerate.
599 * configure: Regenerate.
600
e9b095a5
ML		 6012021-04-01 Martin Liska <mliska@suse.cz>
602
603 * arm-dis.c (strneq): Remove strneq and use startswith.
604 * cr16-dis.c (print_insn_cr16): Likewise.
605 * score-dis.c (streq): Likewise.
606 (strneq): Likewise.
607 * score7-dis.c (strneq): Likewise.
608
1cb108e4
AM		 6092021-04-01 Alan Modra <amodra@gmail.com>
610
611 PR 27675
612 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
613
78933a4a
AM		 6142021-03-31 Alan Modra <amodra@gmail.com>
615
616 * sysdep.h (POISON_BFD_BOOLEAN): Define.
617 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
618 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
619 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
620 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
621 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
622 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
623 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
624 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
625 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
626 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
627 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
628 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
629 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
630 and TRUE with true throughout.
631
3dfb1b6d
AM		 6322021-03-31 Alan Modra <amodra@gmail.com>
633
634 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
635 * aarch64-dis.h: Likewise.
636 * aarch64-opc.c: Likewise.
637 * avr-dis.c: Likewise.
638 * csky-dis.c: Likewise.
639 * nds32-asm.c: Likewise.
640 * nds32-dis.c: Likewise.
641 * nfp-dis.c: Likewise.
642 * riscv-dis.c: Likewise.
643 * s12z-dis.c: Likewise.
644 * wasm32-dis.c: Likewise.
645
5e042380
JB		 6462021-03-30 Jan Beulich <jbeulich@suse.com>
647
648 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
649 (i386_seg_prefixes): New.
650 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
651 (i386_seg_prefixes): Declare.
652
34684862
JB		 6532021-03-30 Jan Beulich <jbeulich@suse.com>
654
655 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
656
6288d05f
JB		 6572021-03-30 Jan Beulich <jbeulich@suse.com>
658
659 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
660 * i386-reg.tbl (st): Move down.
661 (st(0)): Delete. Extend comment.
662 * i386-tbl.h: Re-generate.
663
bbe1eca6
JB		 6642021-03-29 Jan Beulich <jbeulich@suse.com>
665
666 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
667 (cmpsd): Move next to cmps.
668 (movsd): Move next to movs.
669 (cmpxchg16b): Move to separate section.
670 (fisttp, fisttpll): Likewise.
671 (monitor, mwait): Likewise.
672 * i386-tbl.h: Re-generate.
673
c8cad9d3
JB		 6742021-03-29 Jan Beulich <jbeulich@suse.com>
675
676 * i386-opc.tbl (psadbw): Add <sse2:comm>.
677 (vpsadbw): Add C.
678 * i386-tbl.h: Re-generate.
679
5cdaf100
JB		 6802021-03-29 Jan Beulich <jbeulich@suse.com>
681
682 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
683 pclmul, gfni): New templates. Use them wherever possible. Move
684 SSE4.1 pextrw into respective section.
685 * i386-tbl.h: Re-generate.
686
73e45eb2
JB		 6872021-03-29 Jan Beulich <jbeulich@suse.com>
688
689 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
690 strtoull(). Bump upper loop bound. Widen masks. Sanity check
691 "length".
692 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
693 Convert all of their uses to representation in opcode.
694
9df6f676
JB		 6952021-03-29 Jan Beulich <jbeulich@suse.com>
696
697 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
698 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
699 value of None. Shrink operands to 3 bits.
700
389d00a5
JB		 7012021-03-29 Jan Beulich <jbeulich@suse.com>
702
703 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 704 "space".
389d00a5
JB		 705 (output_i386_opcode): New local variable "space". Adjust
706 process_i386_opcode_modifier() invocation.
707 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
708 invocation.
709 * i386-tbl.h: Re-generate.
710
63b4cc53
AM		 7112021-03-29 Alan Modra <amodra@gmail.com>
712
713 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
714 (fp_qualifier_p, get_data_pattern): Likewise.
715 (aarch64_get_operand_modifier_from_value): Likewise.
716 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
717 (operand_variant_qualifier_p): Likewise.
718 (qualifier_value_in_range_constraint_p): Likewise.
719 (aarch64_get_qualifier_esize): Likewise.
720 (aarch64_get_qualifier_nelem): Likewise.
721 (aarch64_get_qualifier_standard_value): Likewise.
722 (get_lower_bound, get_upper_bound): Likewise.
723 (aarch64_find_best_match, match_operands_qualifier): Likewise.
724 (aarch64_print_operand): Likewise.
725 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
726 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
727 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
728 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
729 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
730 (print_insn_tic6x): Likewise.
731
3d7d6c1b
AM		 7322021-03-29 Alan Modra <amodra@gmail.com>
733
734 * arc-dis.c (extract_operand_value): Correct NULL cast.
735 * frv-opc.h: Regenerate.
736
c3344b62
JB		 7372021-03-26 Jan Beulich <jbeulich@suse.com>
738
739 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
740 MMX form.
741 * i386-tbl.h: Re-generate.
742
efa30ac3
HAQ		 7432021-03-25 Abid Qadeer <abidh@codesourcery.com>
744
745 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
746 immediate in br.n instruction.
747
596a02ff
JB		 7482021-03-25 Jan Beulich <jbeulich@suse.com>
749
750 * i386-dis.c (XMGatherD, VexGatherD): New.
751 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
752 (print_insn): Check masking for S/G insns.
753 (OP_E_memory): New local variable check_gather. Extend mandatory
754 SIB check. Check register conflicts for (EVEX-encoded) gathers.
755 Extend check for disallowed 16-bit addressing.
756 (OP_VEX): New local variables modrm_reg and sib_index. Convert
757 if()s to switch(). Check register conflicts for (VEX-encoded)
758 gathers. Drop no longer reachable cases.
759 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
760 vgatherdp*.
761
53642852
JB		 7622021-03-25 Jan Beulich <jbeulich@suse.com>
763
764 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
765 zeroing-masking without masking.
766
c0e54661
JB		 7672021-03-25 Jan Beulich <jbeulich@suse.com>
768
769 * i386-opc.tbl (invlpgb): Fix multi-operand form.
770 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
771 single-operand forms as deprecated.
772 * i386-tbl.h: Re-generate.
773
5a403766
AM		 7742021-03-25 Alan Modra <amodra@gmail.com>
775
776 PR 27647
777 * ppc-opc.c (XLOCB_MASK): Delete.
778 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
779 XLBH_MASK.
780 (powerpc_opcodes): Accept a BH field on all extended forms of
781 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
782
9a182d04
JB		 7832021-03-24 Jan Beulich <jbeulich@suse.com>
784
785 * i386-gen.c (output_i386_opcode): Drop processing of
786 opcode_length. Calculate length from base_opcode. Adjust prefix
787 encoding determination.
788 (process_i386_opcodes): Drop output of fake opcode_length.
789 * i386-opc.h (struct insn_template): Drop opcode_length field.
790 * i386-opc.tbl: Drop opcode length field from all templates.
791 * i386-tbl.h: Re-generate.
792
35648716
JB		 7932021-03-24 Jan Beulich <jbeulich@suse.com>
794
795 * i386-gen.c (process_i386_opcode_modifier): Return void. New
796 parameter "prefix". Drop local variable "regular_encoding".
797 Record prefix setting / check for consistency.
798 (output_i386_opcode): Parse opcode_length and base_opcode
799 earlier. Derive prefix encoding. Drop no longer applicable
800 consistency checking. Adjust process_i386_opcode_modifier()
801 invocation.
802 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
803 invocation.
804 * i386-tbl.h: Re-generate.
805
31184569
JB		 8062021-03-24 Jan Beulich <jbeulich@suse.com>
807
808 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
809 check.
810 * i386-opc.h (Prefix_*): Move #define-s.
811 * i386-opc.tbl: Move pseudo prefix enumerator values to
812 extension opcode field. Introduce pseudopfx template.
813 * i386-tbl.h: Re-generate.
814
b933fa4b
JB		 8152021-03-23 Jan Beulich <jbeulich@suse.com>
816
817 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
818 comment.
819 * i386-tbl.h: Re-generate.
820
dac10fb0
JB		 8212021-03-23 Jan Beulich <jbeulich@suse.com>
822
823 * i386-opc.h (struct insn_template): Move cpu_flags field past
824 opcode_modifier one.
825 * i386-tbl.h: Re-generate.
826
441f6aca
JB		 8272021-03-23 Jan Beulich <jbeulich@suse.com>
828
829 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
830 * i386-opc.h (OpcodeSpace): New enumerator.
831 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
832 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
833 SPACE_XOP09, SPACE_XOP0A): ... respectively.
834 (struct i386_opcode_modifier): New field opcodespace. Shrink
835 opcodeprefix field.
836 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
837 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
838 OpcodePrefix uses.
839 * i386-tbl.h: Re-generate.
840
08dedd66
ML		 8412021-03-22 Martin Liska <mliska@suse.cz>
842
843 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
844 * arc-dis.c (parse_option): Likewise.
845 * arm-dis.c (parse_arm_disassembler_options): Likewise.
846 * cris-dis.c (print_with_operands): Likewise.
847 * h8300-dis.c (bfd_h8_disassemble): Likewise.
848 * i386-dis.c (print_insn): Likewise.
849 * ia64-gen.c (fetch_insn_class): Likewise.
850 (parse_resource_users): Likewise.
851 (in_iclass): Likewise.
852 (lookup_specifier): Likewise.
853 (insert_opcode_dependencies): Likewise.
854 * mips-dis.c (parse_mips_ase_option): Likewise.
855 (parse_mips_dis_option): Likewise.
856 * s390-dis.c (disassemble_init_s390): Likewise.
857 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
858
80d49d6a
KLC		 8592021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
860
861 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
862
7fce7ea9
PW		 8632021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
864
865 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
866 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
867
78c84bf9
AM		 8682021-03-12 Alan Modra <amodra@gmail.com>
869
870 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
871
fd1fd061
JB		 8722021-03-11 Jan Beulich <jbeulich@suse.com>
873
874 * i386-dis.c (OP_XMM): Re-order checks.
875
ac7a2311
JB		 8762021-03-11 Jan Beulich <jbeulich@suse.com>
877
878 * i386-dis.c (putop): Drop need_vex check when also checking
879 vex.evex.
880 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
881 checking vex.b.
882
da944c8a
JB		 8832021-03-11 Jan Beulich <jbeulich@suse.com>
884
885 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
886 checks. Move case label past broadcast check.
887
b763d508
JB		 8882021-03-10 Jan Beulich <jbeulich@suse.com>
889
890 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
891 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
892 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
893 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
894 EVEX_W_0F38C7_M_0_L_2): Delete.
895 (REG_EVEX_0F38C7_M_0_L_2): New.
896 (intel_operand_size): Handle VEX and EVEX the same for
897 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
898 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
899 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
900 vex_vsib_q_w_d_mode uses.
901 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
902 0F38A1, and 0F38A3 entries.
903 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
904 entry.
905 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
906 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
907 0F38A3 entries.
908
32e31ad7
JB		 9092021-03-10 Jan Beulich <jbeulich@suse.com>
910
911 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
912 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
913 MOD_VEX_0FXOP_09_12): Rename to ...
914 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
915 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
916 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
917 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
918 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
919 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
920 (reg_table): Adjust comments.
921 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
922 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
923 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
924 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
925 (vex_len_table): Adjust opcode 0A_12 entry.
926 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
927 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
928 (rm_table): Move hreset entry.
929
85ba7507
JB		 9302021-03-10 Jan Beulich <jbeulich@suse.com>
931
932 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
933 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
934 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
935 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
936 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
937 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
938 (get_valid_dis386): Also handle 512-bit vector length when
939 vectoring into vex_len_table[].
940 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
941 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
942 entries.
943 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
944 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
945 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
946 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
947 entries.
948
066f82b9
JB		 9492021-03-10 Jan Beulich <jbeulich@suse.com>
950
951 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
952 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
953 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
954 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
955 entries.
956 * i386-dis-evex-len.h (evex_len_table): Likewise.
957 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
958
fc681dd6
JB		 9592021-03-10 Jan Beulich <jbeulich@suse.com>
960
961 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
962 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
963 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
964 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
965 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
966 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
967 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
968 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
969 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
970 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
971 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
972 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
973 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
974 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
975 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
976 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
977 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
978 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
979 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
980 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
981 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
982 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
983 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
984 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
985 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
986 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
987 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
988 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
989 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
990 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
991 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
992 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
993 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
994 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
995 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
996 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
997 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
998 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
999 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1000 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1001 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1002 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1003 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1004 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1005 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1006 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1007 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1008 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1009 EVEX_W_0F3A43_L_n): New.
1010 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1011 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1012 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1013 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1014 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1015 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1016 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1017 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1018 0F385B, 0F38C6, and 0F38C7 entries.
1019 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1020 0F38C6 and 0F38C7.
1021 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1022 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1023 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1024 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1025
13954a31
JB		 10262021-03-10 Jan Beulich <jbeulich@suse.com>
1027
1028 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1029 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1030 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1031 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1032 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1033 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1034 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1035 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1036 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1037 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1038 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1039 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1040 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1041 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1042 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1043 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1044 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1045 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1046 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1047 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1048 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1049 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1050 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1051 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1052 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1053 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1054 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1055 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1056 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1057 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1058 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1059 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1060 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1061 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1062 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1063 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1064 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1065 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1066 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1067 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1068 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1069 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1070 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1071 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1072 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1073 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1074 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1075 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1076 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1077 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1078 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1079 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1080 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1081 VEX_W_0F99_P_2_LEN_0): Delete.
1082 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1083 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1084 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1085 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1086 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1087 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1088 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1089 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1090 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1091 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1092 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1093 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1094 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1095 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1096 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1097 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1098 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1099 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1100 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1101 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1102 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1103 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1104 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1105 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1106 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1107 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1108 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1109 (prefix_table): No longer link to vex_len_table[] for opcodes
1110 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1111 0F92, 0F93, 0F98, and 0F99.
1112 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1113 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1114 0F98, and 0F99.
1115 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1116 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1117 0F98, and 0F99.
1118 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1119 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1120 0F98, and 0F99.
1121 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1122 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1123 0F98, and 0F99.
1124
14d10c6c
JB		 11252021-03-10 Jan Beulich <jbeulich@suse.com>
1126
1127 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1128 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1129 REG_VEX_0F73_M_0 respectively.
1130 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1131 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1132 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1133 MOD_VEX_0F73_REG_7): Delete.
1134 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1135 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1136 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1137 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1138 PREFIX_VEX_0F3AF0_L_0 respectively.
1139 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1140 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1141 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1142 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1143 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1144 VEX_LEN_0F38F7): New.
1145 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1146 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1147 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1148 0F38F3.
1149 (prefix_table): No longer link to vex_len_table[] for opcodes
1150 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1151 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1152 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1153 0F38F6, 0F38F7, and 0F3AF0.
1154 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1155 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1156 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1157 0F73.
1158
00ec1875
JB		 11592021-03-10 Jan Beulich <jbeulich@suse.com>
1160
1161 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1162 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1163 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1164 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1165 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1166 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1167 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1168 73.
1169 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1170 0F72, and 0F73.
1171 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1172 0F73.
1173
31941983
JB		 11742021-03-10 Jan Beulich <jbeulich@suse.com>
1175
1176 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1177 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1178 (reg_table): Don't link to mod_table[] where not needed. Add
1179 PREFIX_IGNORED to nop entries.
1180 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1181 (mod_table): Add nop entries next to prefetch ones. Drop
1182 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1183 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1184 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1185 PREFIX_OPCODE from endbr* entries.
1186 (get_valid_dis386): Also consider entry's name when zapping
1187 vindex.
1188 (print_insn): Handle PREFIX_IGNORED.
1189
742732c7
JB		 11902021-03-09 Jan Beulich <jbeulich@suse.com>
1191
1192 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1193 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1194 element.
1195 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1196 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1197 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1198 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1199 (struct i386_opcode_modifier): Delete notrackprefixok,
1200 islockable, hleprefixok, and repprefixok fields. Add prefixok
1201 field.
1202 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1203 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1204 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1205 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1206 Replace HLEPrefixOk.
1207 * opcodes/i386-tbl.h: Re-generate.
1208
e93a3b27
JB		 12092021-03-09 Jan Beulich <jbeulich@suse.com>
1210
1211 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1212 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1213 64-bit form.
1214 * opcodes/i386-tbl.h: Re-generate.
1215
75363b6d
JB		 12162021-03-03 Jan Beulich <jbeulich@suse.com>
1217
1218 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1219 for {} instead of {0}. Don't look for '0'.
1220 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1221 size specifiers.
1222
5a9f5403
NC		 12232021-02-19 Nelson Chu <nelson.chu@sifive.com>
1224
1225 PR 27158
1226 * riscv-dis.c (print_insn_args): Updated encoding macros.
1227 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1228 (match_c_addi16sp): Updated encoding macros.
1229 (match_c_lui): Likewise.
1230 (match_c_lui_with_hint): Likewise.
1231 (match_c_addi4spn): Likewise.
1232 (match_c_slli): Likewise.
1233 (match_slli_as_c_slli): Likewise.
1234 (match_c_slli64): Likewise.
1235 (match_srxi_as_c_srxi): Likewise.
1236 (riscv_insn_types): Added .insn css/cl/cs.
1237
3d73d29e
NC		 12382021-02-18 Nelson Chu <nelson.chu@sifive.com>
1239
1240 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1241 (default_priv_spec): Updated type to riscv_spec_class.
1242 (parse_riscv_dis_option): Updated.
1243 * riscv-opc.c: Moved stuff and make the file tidy.
1244
b9b204b3
AM		 12452021-02-17 Alan Modra <amodra@gmail.com>
1246
1247 * wasm32-dis.c: Include limits.h.
1248 (CHAR_BIT): Provide backup define.
1249 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1250 Correct signed overflow checking.
1251
394ae71f
JB		 12522021-02-16 Jan Beulich <jbeulich@suse.com>
1253
1254 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1255 * i386-tbl.h: Re-generate.
1256
b818b220
JB		 12572021-02-16 Jan Beulich <jbeulich@suse.com>
1258
1259 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1260 Oword.
1261 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1262
ba2b480f
AK		 12632021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1264
1265 * s390-mkopc.c (main): Accept arch14 as cpu string.
1266 * s390-opc.txt: Add new arch14 instructions.
1267
95148614
NA		 12682021-02-04 Nick Alcock <nick.alcock@oracle.com>
1269
1270 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1271 favour of LIBINTL.
1272 * configure: Regenerated.
1273
bfd428bc
MF		 12742021-02-08 Mike Frysinger <vapier@gentoo.org>
1275
1276 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1277 * tic54x-opc.c (regs): Rename to ...
1278 (tic54x_regs): ... this.
1279 (mmregs): Rename to ...
1280 (tic54x_mmregs): ... this.
1281 (condition_codes): Rename to ...
1282 (tic54x_condition_codes): ... this.
1283 (cc2_codes): Rename to ...
1284 (tic54x_cc2_codes): ... this.
1285 (cc3_codes): Rename to ...
1286 (tic54x_cc3_codes): ... this.
1287 (status_bits): Rename to ...
1288 (tic54x_status_bits): ... this.
1289 (misc_symbols): Rename to ...
1290 (tic54x_misc_symbols): ... this.
1291
24075dcc
NC		 12922021-02-04 Nelson Chu <nelson.chu@sifive.com>
1293
1294 * riscv-opc.c (MASK_RVB_IMM): Removed.
1295 (riscv_opcodes): Removed zb* instructions.
1296 (riscv_ext_version_table): Removed versions for zb*.
1297
c3ffb8f3
AM		 12982021-01-26 Alan Modra <amodra@gmail.com>
1299
1300 * i386-gen.c (parse_template): Ensure entire template_instance
1301 is initialised.
1302
1942a048
NC		 13032021-01-15 Nelson Chu <nelson.chu@sifive.com>
1304
1305 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1306 (riscv_fpr_names_abi): Likewise.
1307 (riscv_opcodes): Likewise.
1308 (riscv_insn_types): Likewise.
1309
b800637e
NC		 13102021-01-15 Nelson Chu <nelson.chu@sifive.com>
1311
1312 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1313
dcd709e0
NC		 13142021-01-15 Nelson Chu <nelson.chu@sifive.com>
1315
1316 * riscv-dis.c: Comments tidy and improvement.
1317 * riscv-opc.c: Likewise.
1318
5347ed60
AM		 13192021-01-13 Alan Modra <amodra@gmail.com>
1320
1321 * Makefile.in: Regenerate.
1322
d546b610
L		 13232021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1324
1325 PR binutils/26792
1326 * configure.ac: Use GNU_MAKE_JOBSERVER.
1327 * aclocal.m4: Regenerated.
1328 * configure: Likewise.
1329
6d104cac
NC		 13302021-01-12 Nick Clifton <nickc@redhat.com>
1331
1332 * po/sr.po: Updated Serbian translation.
1333
83b33c6c
L		 13342021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1335
1336 PR ld/27173
1337 * configure: Regenerated.
1338
82c70b08
KT		 13392021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1340
1341 * aarch64-asm-2.c: Regenerate.
1342 * aarch64-dis-2.c: Likewise.
1343 * aarch64-opc-2.c: Likewise.
1344 * aarch64-opc.c (aarch64_print_operand):
1345 Delete handling of AARCH64_OPND_CSRE_CSR.
1346 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1347 (CSRE): Likewise.
1348 (_CSRE_INSN): Likewise.
1349 (aarch64_opcode_table): Delete csr.
1350
a8aa72b9
NC		 13512021-01-11 Nick Clifton <nickc@redhat.com>
1352
1353 * po/de.po: Updated German translation.
1354 * po/fr.po: Updated French translation.
1355 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1356 * po/sv.po: Updated Swedish translation.
1357 * po/uk.po: Updated Ukranian translation.
1358
a4966cd9
L		 13592021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1360
1361 * configure: Regenerated.
1362
573fe3fb
NC		 13632021-01-09 Nick Clifton <nickc@redhat.com>
1364
1365 * configure: Regenerate.
1366 * po/opcodes.pot: Regenerate.
1367
055bc77a
NC		 13682021-01-09 Nick Clifton <nickc@redhat.com>
1369
1370 * 2.36 release branch crated.
1371
aae7fcb8
PB		 13722021-01-08 Peter Bergner <bergner@linux.ibm.com>
1373
1374 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1375 (DW, (XRC_MASK): Define.
1376 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1377
64307045
AM		 13782021-01-09 Alan Modra <amodra@gmail.com>
1379
1380 * configure: Regenerate.
1381
ed205222
NC		 13822021-01-08 Nick Clifton <nickc@redhat.com>
1383
1384 * po/sv.po: Updated Swedish translation.
1385
fb932b57
NC		 13862021-01-08 Nick Clifton <nickc@redhat.com>
1387
e84c8716
NC		 1388 PR 27129
1389 * aarch64-dis.c (determine_disassembling_preference): Move call to
1390 aarch64_match_operands_constraint outside of the assertion.
1391 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1392 Replace with a return of FALSE.
1393
fb932b57
NC		 1394 PR 27139
1395 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1396 core system register.
1397
f4782128
ST		 13982021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1399
1400 * configure: Regenerate.
1401
1b0927db
NC		 14022021-01-07 Nick Clifton <nickc@redhat.com>
1403
1404 * po/fr.po: Updated French translation.
1405
3b288c8e
FN		 14062021-01-07 Fredrik Noring <noring@nocrew.org>
1407
1408 * m68k-opc.c (chkl): Change minimum architecture requirement to
1409 m68020.
1410
aa881ecd
PT		 14112021-01-07 Philipp Tomsich <prt@gnu.org>
1412
1413 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1414
2652cfad
CXW		 14152021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1416 Jim Wilson <jimw@sifive.com>
1417 Andrew Waterman <andrew@sifive.com>
1418 Maxim Blinov <maxim.blinov@embecosm.com>
1419 Kito Cheng <kito.cheng@sifive.com>
1420 Nelson Chu <nelson.chu@sifive.com>
1421
1422 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1423 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1424
250d07de
AM		 14252021-01-01 Alan Modra <amodra@gmail.com>
1426
1427 Update year range in copyright notice of all files.
1428
c2795844 1429For older changes see ChangeLog-2020
3499769a 1430\f
d87bef3a 1431Copyright (C) 2021-2023 Free Software Foundation, Inc.
3499769a
AM		 1432
1433Copying and distribution of this file, with or without modification,
1434are permitted in any medium without royalty provided the copyright
1435notice and this notice are preserved.
1436
1437Local Variables:
1438mode: change-log
1439left-margin: 8
1440fill-column: 74
1441version-control: never
1442End:
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