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Fix allocate_filenum last dir/file checks
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
718aefcf
NC		 12021-09-02 Nick Clifton <nickc@redhat.com>
2
3 PR 28292
4 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
5 of BFD_RELOC_16.
6
5d9cff51
SV		 72021-08-17 Shahab Vahedi <shahab@synopsys.com>
8
9 * arc-regs.h (DEF): Fix the register numbers.
10
3ee0cd9e
NC		 112021-08-10 Nick Clifton <nickc@redhat.com>
12
13 * po/sr.po: Updated Serbian translation.
14
8d56b9fc
CX		 152021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
16
17 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
18
b180e829
AK		 192021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
20
21 * s390-opc.txt: Add qpaci.
22
346d80ef
NC		 232021-07-03 Nick Clifton <nickc@redhat.com>
24
25 * configure: Regenerate.
26 * po/opcodes.pot: Regenerate.
27
51419248
NC		 282021-07-03 Nick Clifton <nickc@redhat.com>
29
30 * 2.37 release branch created.
31
62194b63
AM		 322021-07-02 Alan Modra <amodra@gmail.com>
33
34 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
35 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
36 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
37 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
38 (nds32_keyword_gpr): Move declarations to..
39 * nds32-asm.h: ..here, constifying to match definitions.
40
2fe36d31
MF		 412021-07-01 Mike Frysinger <vapier@gentoo.org>
42
43 * Makefile.am (GUILE): New variable.
44 (CGEN): Use $(GUILE).
45 * Makefile.in: Regenerate.
46
f375d32b
MF		 472021-07-01 Mike Frysinger <vapier@gentoo.org>
48
49 * mep-asm.c (macros): Mark static & const.
50 (lookup_macro): Change return & m to const.
51 (expand_macro): Change mac to const.
52 (expand_string): Change pmacro to const.
53
9b2beaf7
MF		 542021-07-01 Mike Frysinger <vapier@gentoo.org>
55
56 * nds32-asm.c (operand_fields): Rename to ...
57 (nds32_operand_fields): ... this.
58 (keyword_gpr): Rename to ...
59 (nds32_keyword_gpr): ... this.
60 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
61 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
62 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
63 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
64 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
65 Mark static.
66 (keywords): Rename to ...
67 (nds32_keywords): ... this.
68 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
69 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
70
ac8ef696
MF		 712021-07-01 Mike Frysinger <vapier@gentoo.org>
72
73 * z80-dis.c (opc_ed): Make const.
74 (pref_ed): Make p const.
75
52b83874
MF		 762021-07-01 Mike Frysinger <vapier@gentoo.org>
77
78 * microblaze-dis.c (get_field_special): Make op const.
79 (read_insn_microblaze): Make opr & op const. Rename opcodes to
80 microblaze_opcodes.
81 (print_insn_microblaze): Make op & pop const.
82 (get_insn_microblaze): Make op const. Rename opcodes to
83 microblaze_opcodes.
84 (microblaze_get_target_address): Likewise.
85 * microblaze-opc.h (struct op_code_struct): Make const.
86 Rename opcodes to microblaze_opcodes.
87
6c2ede01
MF		 882021-07-01 Mike Frysinger <vapier@gentoo.org>
89
90 * aarch64-gen.c (aarch64_opcode_table): Add const.
91 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
92
46b8b3d6
AB		 932021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
94
95 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
96 available.
97
ded5cb94
AM		 982021-06-22 Alan Modra <amodra@gmail.com>
99
100 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
101 print separator for pcrel insns.
102
47399e9c
AM		 1032021-06-19 Alan Modra <amodra@gmail.com>
104
105 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
106
d984392e
AM		 1072021-06-19 Alan Modra <amodra@gmail.com>
108
109 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
110 entire buffer.
111
7993124e
AM		 1122021-06-17 Alan Modra <amodra@gmail.com>
113
114 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
115 in table.
116
a38d1396
AM		 1172021-06-03 Alan Modra <amodra@gmail.com>
118
119 PR 1202
120 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
121 Use unsigned int for inst.
122
8f467114
SV		 1232021-06-02 Shahab Vahedi <shahab@synopsys.com>
124
125 * arc-dis.c (arc_option_arg_t): New enumeration.
126 (arc_options): New variable.
127 (disassembler_options_arc): New function.
128 (print_arc_disassembler_options): Reimplement in terms of
129 "disassembler_options_arc".
130
1ff6a3b8
AM		 1312021-05-29 Alan Modra <amodra@gmail.com>
132
133 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
134 Don't special case PPC_OPCODE_RAW.
135 (lookup_prefix): Likewise.
136 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
137 (print_insn_powerpc): ..update caller.
138 * ppc-opc.c (EXT): Define.
139 (powerpc_opcodes): Mark extended mnemonics with EXT.
140 (prefix_opcodes, vle_opcodes): Likewise.
141 (XISEL, XISEL_MASK): Add cr field and simplify.
142 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
143 all isel variants to where the base mnemonic belongs. Sort dstt,
144 dststt and dssall.
145
49149d59
MR		 1462021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
147
148 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
149 COP3 opcode instructions.
150
9573a461
MR		 1512021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
152
153 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
154 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
155 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
156 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
157 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
158 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
159 "cop2", and "cop3" entries.
160
fa495743
MR		 1612021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
162
163 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
164 entries and associated comments.
165
b930964c
MR		 1662021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
167
168 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
169 of "c0".
170
dd844468
MR		 1712021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
172
173 * mips-dis.c (mips_cp1_names_mips): New variable.
174 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
175 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
176 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
177 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
178 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
179 "loongson2f".
180
9204ccd4
MR		 1812021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
182
183 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
184 handling code over to...
185 <OP_REG_CONTROL>: ... this new case.
186 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
187 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
188 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
189 replacing the `G' operand code with `g'. Update "cftc1" and
190 "cftc2" entries replacing the `E' operand code with `y'.
191 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
192 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
193 entries replacing the `G' operand code with `g'.
194
a3fb396f
MR		 1952021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
196
197 * mips-dis.c (mips_cp0_names_r3900): New variable.
198 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
199 for "r3900".
200
cccc84fa
MR		 2012021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
202
203 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
204 and "mtthc2" to using the `G' rather than `g' operand code for
205 the coprocessor control register referred.
206
c9de3168
MR		 2072021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
208
209 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
210 entries with each other.
211
ebcab741
PB		 2122021-05-27 Peter Bergner <bergner@linux.ibm.com>
213
214 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
215
bc30a119
AM		 2162021-05-25 Alan Modra <amodra@gmail.com>
217
218 * cris-desc.c: Regenerate.
219 * cris-desc.h: Regenerate.
220 * cris-opc.h: Regenerate.
221 * po/POTFILES.in: Regenerate.
222
54711280
MF		 2232021-05-24 Mike Frysinger <vapier@gentoo.org>
224
225 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
226 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
227 (CGEN_CPUS): Add cris.
228 (CRIS_DEPS): Define.
229 (stamp-cris): New rule.
230 * cgen.sh: Handle desc action.
231 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
232 * Makefile.in, configure: Regenerate.
233
113bb761
JN		 2342021-05-18 Job Noorman <mtvec@pm.me>
235
236 PR 27814
237 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
238 the elf objects.
239
e683cb41
AC		 2402021-05-17 Alex Coplan <alex.coplan@arm.com>
241
242 * arm-dis.c (mve_opcodes): Fix disassembly of
243 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
244 (is_mve_encoding_conflict): MVE vector loads should not match
245 when P = W = 0.
246 (is_mve_unpredictable): It's not unpredictable to use the same
247 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
248
a680affc
NC		 2492021-05-11 Nick Clifton <nickc@redhat.com>
250
251 PR 27840
252 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
253 the end of the code buffer.
254
0b3e14c9
SH		 2552021-05-06 Stafford Horne <shorne@gmail.com>
256
257 PR 21464
258 * or1k-asm.c: Regenerate.
259
6aee2cb2
MF		 2602021-05-01 Max Filippov <jcmvbkbc@gmail.com>
261
262 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
263 info->insn_info_valid.
264
fe134c65
JB		 2652021-04-26 Jan Beulich <jbeulich@suse.com>
266
267 * i386-opc.tbl (lea): Add Optimize.
268 * opcodes/i386-tbl.h: Re-generate.
269
b3ea7639
MF		 2702020-04-23 Max Filippov <jcmvbkbc@gmail.com>
271
272 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
273 of l32r fetch and display referenced literal value.
274
c1cbb7d8
MF		 2752021-04-23 Max Filippov <jcmvbkbc@gmail.com>
276
277 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
278 to 4 for literal disassembly.
279
02202574
PW		 2802021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
281
282 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
283 for TLBI instruction.
284
cd6608e4
PW		 2852021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
286
287 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
288 DC instruction.
289
fe1640ff
JB		 2902021-04-19 Jan Beulich <jbeulich@suse.com>
291
292 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
293 "qualifier".
294 (convert_mov_to_movewide): Add initializer for "value".
295
100e914d
PW		 2962021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
297
298 * aarch64-opc.c: Add RME system registers.
299
a21b96dd
NC		 3002021-04-16 Lifang Xia <lifang_xia@c-sky.com>
301
302 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
303 "addi d,CV,z" to "c.mv d,CV".
304
43e05cd4
AM		 3052021-04-12 Alan Modra <amodra@gmail.com>
306
307 * configure.ac (--enable-checking): Add support.
308 * config.in: Regenerate.
309 * configure: Regenerate.
310
52efda82
TB		 3112021-04-09 Tejas Belagod <tejas.belagod@arm.com>
312
313 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
314 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
315
c3f72de4
AM		 3162021-04-09 Alan Modra <amodra@gmail.com>
317
318 * ppc-dis.c (struct dis_private): Add "special".
319 (POWERPC_DIALECT): Delete. Replace uses with..
320 (private_data): ..this. New inline function.
321 (disassemble_init_powerpc): Init "special" names.
322 (skip_optional_operands): Add is_pcrel arg, set when detecting R
323 field of prefix instructions.
324 (bsearch_reloc, print_got_plt): New functions.
325 (print_insn_powerpc): For pcrel instructions, print target address
326 and symbol if known, and decode plt and got loads too.
327
ce7d813a
AM		 3282021-04-08 Alan Modra <amodra@gmail.com>
329
330 PR 27684
331 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
332
97bf40d8
AM		 3332021-04-08 Alan Modra <amodra@gmail.com>
334
335 PR 27676
336 * ppc-opc.c (DCBT_EO): Move earlier.
337 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
338 (powerpc_operands): Add THCT and THDS entries.
339 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
340
a2e66773
AM		 3412021-04-06 Alan Modra <amodra@gmail.com>
342
343 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
344 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
345 symbol_at_address_func.
346
ab2af25e
AM		 3472021-04-05 Alan Modra <amodra@gmail.com>
348
349 * configure.ac: Don't check for limits.h, string.h, strings.h or
350 stdlib.h.
351 (AC_ISC_POSIX): Don't invoke.
352 * sysdep.h: Include stdlib.h and string.h unconditionally.
353 * i386-opc.h: Include limits.h unconditionally.
354 * wasm32-dis.c: Likewise.
355 * cgen-opc.c: Don't include alloca-conf.h.
356 * config.in: Regenerate.
357 * configure: Regenerate.
358
e9b095a5
ML		 3592021-04-01 Martin Liska <mliska@suse.cz>
360
361 * arm-dis.c (strneq): Remove strneq and use startswith.
362 * cr16-dis.c (print_insn_cr16): Likewise.
363 * score-dis.c (streq): Likewise.
364 (strneq): Likewise.
365 * score7-dis.c (strneq): Likewise.
366
1cb108e4
AM		 3672021-04-01 Alan Modra <amodra@gmail.com>
368
369 PR 27675
370 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
371
78933a4a
AM		 3722021-03-31 Alan Modra <amodra@gmail.com>
373
374 * sysdep.h (POISON_BFD_BOOLEAN): Define.
375 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
376 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
377 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
378 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
379 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
380 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
381 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
382 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
383 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
384 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
385 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
386 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
387 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
388 and TRUE with true throughout.
389
3dfb1b6d
AM		 3902021-03-31 Alan Modra <amodra@gmail.com>
391
392 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
393 * aarch64-dis.h: Likewise.
394 * aarch64-opc.c: Likewise.
395 * avr-dis.c: Likewise.
396 * csky-dis.c: Likewise.
397 * nds32-asm.c: Likewise.
398 * nds32-dis.c: Likewise.
399 * nfp-dis.c: Likewise.
400 * riscv-dis.c: Likewise.
401 * s12z-dis.c: Likewise.
402 * wasm32-dis.c: Likewise.
403
5e042380
JB		 4042021-03-30 Jan Beulich <jbeulich@suse.com>
405
406 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
407 (i386_seg_prefixes): New.
408 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
409 (i386_seg_prefixes): Declare.
410
34684862
JB		 4112021-03-30 Jan Beulich <jbeulich@suse.com>
412
413 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
414
6288d05f
JB		 4152021-03-30 Jan Beulich <jbeulich@suse.com>
416
417 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
418 * i386-reg.tbl (st): Move down.
419 (st(0)): Delete. Extend comment.
420 * i386-tbl.h: Re-generate.
421
bbe1eca6
JB		 4222021-03-29 Jan Beulich <jbeulich@suse.com>
423
424 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
425 (cmpsd): Move next to cmps.
426 (movsd): Move next to movs.
427 (cmpxchg16b): Move to separate section.
428 (fisttp, fisttpll): Likewise.
429 (monitor, mwait): Likewise.
430 * i386-tbl.h: Re-generate.
431
c8cad9d3
JB		 4322021-03-29 Jan Beulich <jbeulich@suse.com>
433
434 * i386-opc.tbl (psadbw): Add <sse2:comm>.
435 (vpsadbw): Add C.
436 * i386-tbl.h: Re-generate.
437
5cdaf100
JB		 4382021-03-29 Jan Beulich <jbeulich@suse.com>
439
440 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
441 pclmul, gfni): New templates. Use them wherever possible. Move
442 SSE4.1 pextrw into respective section.
443 * i386-tbl.h: Re-generate.
444
73e45eb2
JB		 4452021-03-29 Jan Beulich <jbeulich@suse.com>
446
447 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
448 strtoull(). Bump upper loop bound. Widen masks. Sanity check
449 "length".
450 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
451 Convert all of their uses to representation in opcode.
452
9df6f676
JB		 4532021-03-29 Jan Beulich <jbeulich@suse.com>
454
455 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
456 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
457 value of None. Shrink operands to 3 bits.
458
389d00a5
JB		 4592021-03-29 Jan Beulich <jbeulich@suse.com>
460
461 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 462 "space".
389d00a5
JB		 463 (output_i386_opcode): New local variable "space". Adjust
464 process_i386_opcode_modifier() invocation.
465 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
466 invocation.
467 * i386-tbl.h: Re-generate.
468
63b4cc53
AM		 4692021-03-29 Alan Modra <amodra@gmail.com>
470
471 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
472 (fp_qualifier_p, get_data_pattern): Likewise.
473 (aarch64_get_operand_modifier_from_value): Likewise.
474 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
475 (operand_variant_qualifier_p): Likewise.
476 (qualifier_value_in_range_constraint_p): Likewise.
477 (aarch64_get_qualifier_esize): Likewise.
478 (aarch64_get_qualifier_nelem): Likewise.
479 (aarch64_get_qualifier_standard_value): Likewise.
480 (get_lower_bound, get_upper_bound): Likewise.
481 (aarch64_find_best_match, match_operands_qualifier): Likewise.
482 (aarch64_print_operand): Likewise.
483 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
484 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
485 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
486 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
487 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
488 (print_insn_tic6x): Likewise.
489
3d7d6c1b
AM		 4902021-03-29 Alan Modra <amodra@gmail.com>
491
492 * arc-dis.c (extract_operand_value): Correct NULL cast.
493 * frv-opc.h: Regenerate.
494
c3344b62
JB		 4952021-03-26 Jan Beulich <jbeulich@suse.com>
496
497 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
498 MMX form.
499 * i386-tbl.h: Re-generate.
500
efa30ac3
HAQ		 5012021-03-25 Abid Qadeer <abidh@codesourcery.com>
502
503 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
504 immediate in br.n instruction.
505
596a02ff
JB		 5062021-03-25 Jan Beulich <jbeulich@suse.com>
507
508 * i386-dis.c (XMGatherD, VexGatherD): New.
509 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
510 (print_insn): Check masking for S/G insns.
511 (OP_E_memory): New local variable check_gather. Extend mandatory
512 SIB check. Check register conflicts for (EVEX-encoded) gathers.
513 Extend check for disallowed 16-bit addressing.
514 (OP_VEX): New local variables modrm_reg and sib_index. Convert
515 if()s to switch(). Check register conflicts for (VEX-encoded)
516 gathers. Drop no longer reachable cases.
517 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
518 vgatherdp*.
519
53642852
JB		 5202021-03-25 Jan Beulich <jbeulich@suse.com>
521
522 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
523 zeroing-masking without masking.
524
c0e54661
JB		 5252021-03-25 Jan Beulich <jbeulich@suse.com>
526
527 * i386-opc.tbl (invlpgb): Fix multi-operand form.
528 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
529 single-operand forms as deprecated.
530 * i386-tbl.h: Re-generate.
531
5a403766
AM		 5322021-03-25 Alan Modra <amodra@gmail.com>
533
534 PR 27647
535 * ppc-opc.c (XLOCB_MASK): Delete.
536 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
537 XLBH_MASK.
538 (powerpc_opcodes): Accept a BH field on all extended forms of
539 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
540
9a182d04
JB		 5412021-03-24 Jan Beulich <jbeulich@suse.com>
542
543 * i386-gen.c (output_i386_opcode): Drop processing of
544 opcode_length. Calculate length from base_opcode. Adjust prefix
545 encoding determination.
546 (process_i386_opcodes): Drop output of fake opcode_length.
547 * i386-opc.h (struct insn_template): Drop opcode_length field.
548 * i386-opc.tbl: Drop opcode length field from all templates.
549 * i386-tbl.h: Re-generate.
550
35648716
JB		 5512021-03-24 Jan Beulich <jbeulich@suse.com>
552
553 * i386-gen.c (process_i386_opcode_modifier): Return void. New
554 parameter "prefix". Drop local variable "regular_encoding".
555 Record prefix setting / check for consistency.
556 (output_i386_opcode): Parse opcode_length and base_opcode
557 earlier. Derive prefix encoding. Drop no longer applicable
558 consistency checking. Adjust process_i386_opcode_modifier()
559 invocation.
560 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
561 invocation.
562 * i386-tbl.h: Re-generate.
563
31184569
JB		 5642021-03-24 Jan Beulich <jbeulich@suse.com>
565
566 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
567 check.
568 * i386-opc.h (Prefix_*): Move #define-s.
569 * i386-opc.tbl: Move pseudo prefix enumerator values to
570 extension opcode field. Introduce pseudopfx template.
571 * i386-tbl.h: Re-generate.
572
b933fa4b
JB		 5732021-03-23 Jan Beulich <jbeulich@suse.com>
574
575 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
576 comment.
577 * i386-tbl.h: Re-generate.
578
dac10fb0
JB		 5792021-03-23 Jan Beulich <jbeulich@suse.com>
580
581 * i386-opc.h (struct insn_template): Move cpu_flags field past
582 opcode_modifier one.
583 * i386-tbl.h: Re-generate.
584
441f6aca
JB		 5852021-03-23 Jan Beulich <jbeulich@suse.com>
586
587 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
588 * i386-opc.h (OpcodeSpace): New enumerator.
589 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
590 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
591 SPACE_XOP09, SPACE_XOP0A): ... respectively.
592 (struct i386_opcode_modifier): New field opcodespace. Shrink
593 opcodeprefix field.
594 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
595 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
596 OpcodePrefix uses.
597 * i386-tbl.h: Re-generate.
598
08dedd66
ML		 5992021-03-22 Martin Liska <mliska@suse.cz>
600
601 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
602 * arc-dis.c (parse_option): Likewise.
603 * arm-dis.c (parse_arm_disassembler_options): Likewise.
604 * cris-dis.c (print_with_operands): Likewise.
605 * h8300-dis.c (bfd_h8_disassemble): Likewise.
606 * i386-dis.c (print_insn): Likewise.
607 * ia64-gen.c (fetch_insn_class): Likewise.
608 (parse_resource_users): Likewise.
609 (in_iclass): Likewise.
610 (lookup_specifier): Likewise.
611 (insert_opcode_dependencies): Likewise.
612 * mips-dis.c (parse_mips_ase_option): Likewise.
613 (parse_mips_dis_option): Likewise.
614 * s390-dis.c (disassemble_init_s390): Likewise.
615 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
616
80d49d6a
KLC		 6172021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
618
619 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
620
7fce7ea9
PW		 6212021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
622
623 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
624 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
625
78c84bf9
AM		 6262021-03-12 Alan Modra <amodra@gmail.com>
627
628 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
629
fd1fd061
JB		 6302021-03-11 Jan Beulich <jbeulich@suse.com>
631
632 * i386-dis.c (OP_XMM): Re-order checks.
633
ac7a2311
JB		 6342021-03-11 Jan Beulich <jbeulich@suse.com>
635
636 * i386-dis.c (putop): Drop need_vex check when also checking
637 vex.evex.
638 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
639 checking vex.b.
640
da944c8a
JB		 6412021-03-11 Jan Beulich <jbeulich@suse.com>
642
643 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
644 checks. Move case label past broadcast check.
645
b763d508
JB		 6462021-03-10 Jan Beulich <jbeulich@suse.com>
647
648 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
649 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
650 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
651 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
652 EVEX_W_0F38C7_M_0_L_2): Delete.
653 (REG_EVEX_0F38C7_M_0_L_2): New.
654 (intel_operand_size): Handle VEX and EVEX the same for
655 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
656 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
657 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
658 vex_vsib_q_w_d_mode uses.
659 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
660 0F38A1, and 0F38A3 entries.
661 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
662 entry.
663 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
664 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
665 0F38A3 entries.
666
32e31ad7
JB		 6672021-03-10 Jan Beulich <jbeulich@suse.com>
668
669 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
670 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
671 MOD_VEX_0FXOP_09_12): Rename to ...
672 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
673 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
674 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
675 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
676 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
677 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
678 (reg_table): Adjust comments.
679 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
680 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
681 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
682 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
683 (vex_len_table): Adjust opcode 0A_12 entry.
684 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
685 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
686 (rm_table): Move hreset entry.
687
85ba7507
JB		 6882021-03-10 Jan Beulich <jbeulich@suse.com>
689
690 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
691 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
692 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
693 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
694 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
695 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
696 (get_valid_dis386): Also handle 512-bit vector length when
697 vectoring into vex_len_table[].
698 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
699 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
700 entries.
701 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
702 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
703 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
704 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
705 entries.
706
066f82b9
JB		 7072021-03-10 Jan Beulich <jbeulich@suse.com>
708
709 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
710 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
711 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
712 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
713 entries.
714 * i386-dis-evex-len.h (evex_len_table): Likewise.
715 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
716
fc681dd6
JB		 7172021-03-10 Jan Beulich <jbeulich@suse.com>
718
719 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
720 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
721 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
722 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
723 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
724 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
725 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
726 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
727 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
728 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
729 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
730 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
731 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
732 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
733 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
734 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
735 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
736 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
737 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
738 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
739 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
740 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
741 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
742 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
743 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
744 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
745 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
746 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
747 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
748 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
749 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
750 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
751 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
752 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
753 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
754 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
755 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
756 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
757 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
758 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
759 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
760 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
761 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
762 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
763 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
764 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
765 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
766 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
767 EVEX_W_0F3A43_L_n): New.
768 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
769 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
770 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
771 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
772 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
773 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
774 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
775 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
776 0F385B, 0F38C6, and 0F38C7 entries.
777 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
778 0F38C6 and 0F38C7.
779 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
780 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
781 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
782 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
783
13954a31
JB		 7842021-03-10 Jan Beulich <jbeulich@suse.com>
785
786 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
787 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
788 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
789 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
790 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
791 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
792 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
793 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
794 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
795 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
796 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
797 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
798 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
799 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
800 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
801 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
802 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
803 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
804 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
805 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
806 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
807 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
808 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
809 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
810 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
811 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
812 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
813 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
814 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
815 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
816 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
817 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
818 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
819 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
820 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
821 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
822 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
823 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
824 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
825 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
826 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
827 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
828 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
829 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
830 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
831 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
832 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
833 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
834 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
835 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
836 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
837 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
838 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
839 VEX_W_0F99_P_2_LEN_0): Delete.
840 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
841 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
842 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
843 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
844 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
845 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
846 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
847 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
848 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
849 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
850 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
851 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
852 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
853 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
854 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
855 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
856 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
857 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
858 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
859 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
860 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
861 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
862 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
863 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
864 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
865 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
866 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
867 (prefix_table): No longer link to vex_len_table[] for opcodes
868 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
869 0F92, 0F93, 0F98, and 0F99.
870 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
871 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
872 0F98, and 0F99.
873 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
874 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
875 0F98, and 0F99.
876 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
877 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
878 0F98, and 0F99.
879 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
880 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
881 0F98, and 0F99.
882
14d10c6c
JB		 8832021-03-10 Jan Beulich <jbeulich@suse.com>
884
885 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
886 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
887 REG_VEX_0F73_M_0 respectively.
888 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
889 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
890 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
891 MOD_VEX_0F73_REG_7): Delete.
892 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
893 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
894 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
895 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
896 PREFIX_VEX_0F3AF0_L_0 respectively.
897 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
898 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
899 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
900 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
901 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
902 VEX_LEN_0F38F7): New.
903 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
904 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
905 0F72, and 0F73. No longer link to vex_len_table[] for opcode
906 0F38F3.
907 (prefix_table): No longer link to vex_len_table[] for opcodes
908 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
909 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
910 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
911 0F38F6, 0F38F7, and 0F3AF0.
912 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
913 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
914 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
915 0F73.
916
00ec1875
JB		 9172021-03-10 Jan Beulich <jbeulich@suse.com>
918
919 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
920 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
921 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
922 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
923 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
924 (MOD_0F71, MOD_0F72, MOD_0F73): New.
925 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
926 73.
927 (reg_table): No longer link to mod_table[] for opcodes 0F71,
928 0F72, and 0F73.
929 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
930 0F73.
931
31941983
JB		 9322021-03-10 Jan Beulich <jbeulich@suse.com>
933
934 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
935 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
936 (reg_table): Don't link to mod_table[] where not needed. Add
937 PREFIX_IGNORED to nop entries.
938 (prefix_table): Replace PREFIX_OPCODE in nop entries.
939 (mod_table): Add nop entries next to prefetch ones. Drop
940 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
941 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
942 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
943 PREFIX_OPCODE from endbr* entries.
944 (get_valid_dis386): Also consider entry's name when zapping
945 vindex.
946 (print_insn): Handle PREFIX_IGNORED.
947
742732c7
JB		 9482021-03-09 Jan Beulich <jbeulich@suse.com>
949
950 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
951 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
952 element.
953 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
954 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
955 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
956 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
957 (struct i386_opcode_modifier): Delete notrackprefixok,
958 islockable, hleprefixok, and repprefixok fields. Add prefixok
959 field.
960 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
961 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
962 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
963 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
964 Replace HLEPrefixOk.
965 * opcodes/i386-tbl.h: Re-generate.
966
e93a3b27
JB		 9672021-03-09 Jan Beulich <jbeulich@suse.com>
968
969 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
970 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
971 64-bit form.
972 * opcodes/i386-tbl.h: Re-generate.
973
75363b6d
JB		 9742021-03-03 Jan Beulich <jbeulich@suse.com>
975
976 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
977 for {} instead of {0}. Don't look for '0'.
978 * i386-opc.tbl: Drop operand count field. Drop redundant operand
979 size specifiers.
980
5a9f5403
NC		 9812021-02-19 Nelson Chu <nelson.chu@sifive.com>
982
983 PR 27158
984 * riscv-dis.c (print_insn_args): Updated encoding macros.
985 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
986 (match_c_addi16sp): Updated encoding macros.
987 (match_c_lui): Likewise.
988 (match_c_lui_with_hint): Likewise.
989 (match_c_addi4spn): Likewise.
990 (match_c_slli): Likewise.
991 (match_slli_as_c_slli): Likewise.
992 (match_c_slli64): Likewise.
993 (match_srxi_as_c_srxi): Likewise.
994 (riscv_insn_types): Added .insn css/cl/cs.
995
3d73d29e
NC		 9962021-02-18 Nelson Chu <nelson.chu@sifive.com>
997
998 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
999 (default_priv_spec): Updated type to riscv_spec_class.
1000 (parse_riscv_dis_option): Updated.
1001 * riscv-opc.c: Moved stuff and make the file tidy.
1002
b9b204b3
AM		 10032021-02-17 Alan Modra <amodra@gmail.com>
1004
1005 * wasm32-dis.c: Include limits.h.
1006 (CHAR_BIT): Provide backup define.
1007 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1008 Correct signed overflow checking.
1009
394ae71f
JB		 10102021-02-16 Jan Beulich <jbeulich@suse.com>
1011
1012 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1013 * i386-tbl.h: Re-generate.
1014
b818b220
JB		 10152021-02-16 Jan Beulich <jbeulich@suse.com>
1016
1017 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1018 Oword.
1019 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1020
ba2b480f
AK		 10212021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1022
1023 * s390-mkopc.c (main): Accept arch14 as cpu string.
1024 * s390-opc.txt: Add new arch14 instructions.
1025
95148614
NA		 10262021-02-04 Nick Alcock <nick.alcock@oracle.com>
1027
1028 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1029 favour of LIBINTL.
1030 * configure: Regenerated.
1031
bfd428bc
MF		 10322021-02-08 Mike Frysinger <vapier@gentoo.org>
1033
1034 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1035 * tic54x-opc.c (regs): Rename to ...
1036 (tic54x_regs): ... this.
1037 (mmregs): Rename to ...
1038 (tic54x_mmregs): ... this.
1039 (condition_codes): Rename to ...
1040 (tic54x_condition_codes): ... this.
1041 (cc2_codes): Rename to ...
1042 (tic54x_cc2_codes): ... this.
1043 (cc3_codes): Rename to ...
1044 (tic54x_cc3_codes): ... this.
1045 (status_bits): Rename to ...
1046 (tic54x_status_bits): ... this.
1047 (misc_symbols): Rename to ...
1048 (tic54x_misc_symbols): ... this.
1049
24075dcc
NC		 10502021-02-04 Nelson Chu <nelson.chu@sifive.com>
1051
1052 * riscv-opc.c (MASK_RVB_IMM): Removed.
1053 (riscv_opcodes): Removed zb* instructions.
1054 (riscv_ext_version_table): Removed versions for zb*.
1055
c3ffb8f3
AM		 10562021-01-26 Alan Modra <amodra@gmail.com>
1057
1058 * i386-gen.c (parse_template): Ensure entire template_instance
1059 is initialised.
1060
1942a048
NC		 10612021-01-15 Nelson Chu <nelson.chu@sifive.com>
1062
1063 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1064 (riscv_fpr_names_abi): Likewise.
1065 (riscv_opcodes): Likewise.
1066 (riscv_insn_types): Likewise.
1067
b800637e
NC		 10682021-01-15 Nelson Chu <nelson.chu@sifive.com>
1069
1070 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1071
dcd709e0
NC		 10722021-01-15 Nelson Chu <nelson.chu@sifive.com>
1073
1074 * riscv-dis.c: Comments tidy and improvement.
1075 * riscv-opc.c: Likewise.
1076
5347ed60
AM		 10772021-01-13 Alan Modra <amodra@gmail.com>
1078
1079 * Makefile.in: Regenerate.
1080
d546b610
L		 10812021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1082
1083 PR binutils/26792
1084 * configure.ac: Use GNU_MAKE_JOBSERVER.
1085 * aclocal.m4: Regenerated.
1086 * configure: Likewise.
1087
6d104cac
NC		 10882021-01-12 Nick Clifton <nickc@redhat.com>
1089
1090 * po/sr.po: Updated Serbian translation.
1091
83b33c6c
L		 10922021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1093
1094 PR ld/27173
1095 * configure: Regenerated.
1096
82c70b08
KT		 10972021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1098
1099 * aarch64-asm-2.c: Regenerate.
1100 * aarch64-dis-2.c: Likewise.
1101 * aarch64-opc-2.c: Likewise.
1102 * aarch64-opc.c (aarch64_print_operand):
1103 Delete handling of AARCH64_OPND_CSRE_CSR.
1104 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1105 (CSRE): Likewise.
1106 (_CSRE_INSN): Likewise.
1107 (aarch64_opcode_table): Delete csr.
1108
a8aa72b9
NC		 11092021-01-11 Nick Clifton <nickc@redhat.com>
1110
1111 * po/de.po: Updated German translation.
1112 * po/fr.po: Updated French translation.
1113 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1114 * po/sv.po: Updated Swedish translation.
1115 * po/uk.po: Updated Ukranian translation.
1116
a4966cd9
L		 11172021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1118
1119 * configure: Regenerated.
1120
573fe3fb
NC		 11212021-01-09 Nick Clifton <nickc@redhat.com>
1122
1123 * configure: Regenerate.
1124 * po/opcodes.pot: Regenerate.
1125
055bc77a
NC		 11262021-01-09 Nick Clifton <nickc@redhat.com>
1127
1128 * 2.36 release branch crated.
1129
aae7fcb8
PB		 11302021-01-08 Peter Bergner <bergner@linux.ibm.com>
1131
1132 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1133 (DW, (XRC_MASK): Define.
1134 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1135
64307045
AM		 11362021-01-09 Alan Modra <amodra@gmail.com>
1137
1138 * configure: Regenerate.
1139
ed205222
NC		 11402021-01-08 Nick Clifton <nickc@redhat.com>
1141
1142 * po/sv.po: Updated Swedish translation.
1143
fb932b57
NC		 11442021-01-08 Nick Clifton <nickc@redhat.com>
1145
e84c8716
NC		 1146 PR 27129
1147 * aarch64-dis.c (determine_disassembling_preference): Move call to
1148 aarch64_match_operands_constraint outside of the assertion.
1149 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1150 Replace with a return of FALSE.
1151
fb932b57
NC		 1152 PR 27139
1153 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1154 core system register.
1155
f4782128
ST		 11562021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1157
1158 * configure: Regenerate.
1159
1b0927db
NC		 11602021-01-07 Nick Clifton <nickc@redhat.com>
1161
1162 * po/fr.po: Updated French translation.
1163
3b288c8e
FN		 11642021-01-07 Fredrik Noring <noring@nocrew.org>
1165
1166 * m68k-opc.c (chkl): Change minimum architecture requirement to
1167 m68020.
1168
aa881ecd
PT		 11692021-01-07 Philipp Tomsich <prt@gnu.org>
1170
1171 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1172
2652cfad
CXW		 11732021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1174 Jim Wilson <jimw@sifive.com>
1175 Andrew Waterman <andrew@sifive.com>
1176 Maxim Blinov <maxim.blinov@embecosm.com>
1177 Kito Cheng <kito.cheng@sifive.com>
1178 Nelson Chu <nelson.chu@sifive.com>
1179
1180 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1181 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1182
250d07de
AM		 11832021-01-01 Alan Modra <amodra@gmail.com>
1184
1185 Update year range in copyright notice of all files.
1186
c2795844 1187For older changes see ChangeLog-2020
3499769a 1188\f
c2795844 1189Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1190
1191Copying and distribution of this file, with or without modification,
1192are permitted in any medium without royalty provided the copyright
1193notice and this notice are preserved.
1194
1195Local Variables:
1196mode: change-log
1197left-margin: 8
1198fill-column: 74
1199version-control: never
1200End:
A mirror of the official binutils-gdb repository