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c906108c 1/* run front end support for arm
6aba47ca 2 Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002, 2007
86c735a5 3 Free Software Foundation, Inc.
c906108c 4
86c735a5 5 This file is part of ARM SIM.
c906108c 6
86c735a5
NC
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
c906108c 11
86c735a5
NC
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
c906108c 16
86c735a5
NC
17 You should have received a copy of the GNU General Public
18 License along with this program; if not, write to the Free
380d9419
NC
19 Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
c906108c 21
86c735a5
NC
22/* This file provides the interface between the simulator and
23 run.c and gdb (when the simulator is linked with gdb).
c906108c
SS
24 All simulator interaction should go through this file. */
25
26#include <stdio.h>
27#include <stdarg.h>
6d358e86 28#include <string.h>
c906108c
SS
29#include <bfd.h>
30#include <signal.h>
3c25f8c7
AC
31#include "gdb/callback.h"
32#include "gdb/remote-sim.h"
c906108c
SS
33#include "armdefs.h"
34#include "armemu.h"
35#include "dbg_rdi.h"
6d358e86 36#include "ansidecl.h"
86c735a5 37#include "sim-utils.h"
de4112fa 38#include "run-sim.h"
26216b98 39#include "gdb/sim-arm.h"
aba6488e 40#include "gdb/signals.h"
74ec5579 41
c906108c
SS
42host_callback *sim_callback;
43
44static struct ARMul_State *state;
45
46/* Who is using the simulator. */
47static SIM_OPEN_KIND sim_kind;
48
49/* argv[0] */
50static char *myname;
51
52/* Memory size in bytes. */
058f270d 53static int mem_size = (1 << 21);
c906108c
SS
54
55/* Non-zero to display start up banner, and maybe other things. */
56static int verbosity;
57
58/* Non-zero to set big endian mode. */
59static int big_endian;
60
7a292a7a
SS
61int stop_simulator;
62
f603c8fe
NC
63/* Cirrus DSP registers.
64
65 We need to define these registers outside of maverick.c because
66 maverick.c might not be linked in unless --target=arm9e-* in which
67 case wrapper.c will not compile because it tries to access Cirrus
68 registers. This should all go away once we get the Cirrus and ARM
69 Coprocessor to coexist in armcopro.c-- aldyh. */
70
71struct maverick_regs
72{
73 union
74 {
75 int i;
76 float f;
77 } upper;
78
79 union
80 {
81 int i;
82 float f;
83 } lower;
84};
85
86union maverick_acc_regs
87{
88 long double ld; /* Acc registers are 72-bits. */
89};
90
91struct maverick_regs DSPregs[16];
92union maverick_acc_regs DSPacc[4];
93ARMword DSPsc;
94
dfcd3bfb 95static void
c906108c
SS
96init ()
97{
98 static int done;
99
100 if (!done)
101 {
dfcd3bfb 102 ARMul_EmulateInit ();
c906108c
SS
103 state = ARMul_NewState ();
104 state->bigendSig = (big_endian ? HIGH : LOW);
dfcd3bfb
JM
105 ARMul_MemoryInit (state, mem_size);
106 ARMul_OSInit (state);
c906108c
SS
107 state->verbose = verbosity;
108 done = 1;
109 }
110}
111
112/* Set verbosity level of simulator.
113 This is not intended to produce detailed tracing or debugging information.
114 Just summaries. */
115/* FIXME: common/run.c doesn't do this yet. */
116
117void
118sim_set_verbose (v)
119 int v;
120{
121 verbosity = v;
122}
123
124/* Set the memory size to SIZE bytes.
dfcd3bfb 125 Must be called before initializing simulator. */
c906108c
SS
126/* FIXME: Rename to sim_set_mem_size. */
127
dfcd3bfb 128void
c906108c
SS
129sim_size (size)
130 int size;
131{
132 mem_size = size;
133}
134
dfcd3bfb 135void
86c735a5
NC
136ARMul_ConsolePrint VPARAMS ((ARMul_State * state,
137 const char * format,
138 ...))
c906108c
SS
139{
140 va_list ap;
141
142 if (state->verbose)
143 {
144 va_start (ap, format);
145 vprintf (format, ap);
146 va_end (ap);
147 }
148}
149
6d358e86 150ARMword
86c735a5
NC
151ARMul_Debug (state, pc, instr)
152 ARMul_State * state ATTRIBUTE_UNUSED;
153 ARMword pc ATTRIBUTE_UNUSED;
154 ARMword instr ATTRIBUTE_UNUSED;
c906108c 155{
6d358e86 156 return 0;
c906108c
SS
157}
158
159int
160sim_write (sd, addr, buffer, size)
6d358e86 161 SIM_DESC sd ATTRIBUTE_UNUSED;
c906108c 162 SIM_ADDR addr;
86c735a5 163 unsigned char * buffer;
c906108c
SS
164 int size;
165{
166 int i;
3943c96b 167
c906108c 168 init ();
3943c96b 169
c906108c 170 for (i = 0; i < size; i++)
917bca4f 171 ARMul_SafeWriteByte (state, addr + i, buffer[i]);
3943c96b 172
c906108c
SS
173 return size;
174}
175
176int
177sim_read (sd, addr, buffer, size)
6d358e86 178 SIM_DESC sd ATTRIBUTE_UNUSED;
c906108c 179 SIM_ADDR addr;
86c735a5 180 unsigned char * buffer;
c906108c
SS
181 int size;
182{
183 int i;
917bca4f 184
c906108c 185 init ();
86c735a5 186
c906108c 187 for (i = 0; i < size; i++)
917bca4f
NC
188 buffer[i] = ARMul_SafeReadByte (state, addr + i);
189
c906108c
SS
190 return size;
191}
192
193int
194sim_trace (sd)
6d358e86 195 SIM_DESC sd ATTRIBUTE_UNUSED;
dfcd3bfb 196{
86c735a5
NC
197 (*sim_callback->printf_filtered)
198 (sim_callback,
199 "This simulator does not support tracing\n");
c906108c
SS
200 return 1;
201}
202
203int
204sim_stop (sd)
6d358e86 205 SIM_DESC sd ATTRIBUTE_UNUSED;
c906108c 206{
7a292a7a
SS
207 state->Emulate = STOP;
208 stop_simulator = 1;
209 return 1;
c906108c
SS
210}
211
212void
213sim_resume (sd, step, siggnal)
6d358e86
NC
214 SIM_DESC sd ATTRIBUTE_UNUSED;
215 int step;
216 int siggnal ATTRIBUTE_UNUSED;
c906108c
SS
217{
218 state->EndCondition = 0;
7a292a7a 219 stop_simulator = 0;
c906108c
SS
220
221 if (step)
222 {
223 state->Reg[15] = ARMul_DoInstr (state);
224 if (state->EndCondition == 0)
225 state->EndCondition = RDIError_BreakpointReached;
226 }
227 else
228 {
dfcd3bfb 229 state->NextInstr = RESUME; /* treat as PC change */
c906108c
SS
230 state->Reg[15] = ARMul_DoProg (state);
231 }
232
233 FLUSHPIPE;
234}
235
236SIM_RC
237sim_create_inferior (sd, abfd, argv, env)
6d358e86 238 SIM_DESC sd ATTRIBUTE_UNUSED;
6b4a8935 239 struct bfd * abfd;
86c735a5
NC
240 char ** argv;
241 char ** env;
c906108c 242{
dfcd3bfb 243 int argvlen = 0;
1e6b544a 244 int mach;
c906108c
SS
245 char **arg;
246
247 if (abfd != NULL)
248 ARMul_SetPC (state, bfd_get_start_address (abfd));
249 else
dfcd3bfb 250 ARMul_SetPC (state, 0); /* ??? */
c906108c 251
1e6b544a
AO
252 mach = bfd_get_mach (abfd);
253
3943c96b
NC
254 switch (mach)
255 {
256 default:
86c735a5
NC
257 (*sim_callback->printf_filtered)
258 (sim_callback,
10b57fcb
NC
259 "Unknown machine type '%d'; please update sim_create_inferior.\n",
260 mach);
3943c96b
NC
261 /* fall through */
262
f1129fb8 263 case 0:
3943c96b 264 /* We wouldn't set the machine type with earlier toolchains, so we
f1129fb8
NC
265 explicitly select a processor capable of supporting all ARMs in
266 32bit mode. */
0f026fd0
NC
267 /* We choose the XScale rather than the iWMMXt, because the iWMMXt
268 removes the FPE emulator, since it conflicts with its coprocessors.
269 For the most generic ARM support, we want the FPE emulator in place. */
272fcdcd 270 case bfd_mach_arm_XScale:
8207e0f2 271 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
272fcdcd
NC
272 break;
273
0f026fd0
NC
274 case bfd_mach_arm_iWMMXt:
275 {
276 extern int SWI_vector_installed;
277 ARMword i;
278
279 if (! SWI_vector_installed)
280 {
281 /* Intialise the hardware vectors to zero. */
282 if (! SWI_vector_installed)
283 for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
284 ARMul_WriteWord (state, i, 0);
285
286 /* ARM_WriteWord will have detected the write to the SWI vector,
287 but we want SWI_vector_installed to remain at 0 so that thumb
288 mode breakpoints will work. */
289 SWI_vector_installed = 0;
290 }
291 }
292 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
293 break;
294
f603c8fe
NC
295 case bfd_mach_arm_ep9312:
296 ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
297 break;
298
f1129fb8 299 case bfd_mach_arm_5:
c17aa318
NC
300 if (bfd_family_coff (abfd))
301 {
302 /* This is a special case in order to support COFF based ARM toolchains.
303 The COFF header does not have enough room to store all the different
304 kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
305 to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
306 machine type here, we assume it could be any of the above architectures
307 and so select the most feature-full. */
308 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
309 break;
310 }
311 /* Otherwise drop through. */
25180f8a 312
f1129fb8
NC
313 case bfd_mach_arm_5T:
314 ARMul_SelectProcessor (state, ARM_v5_Prop);
315 break;
3943c96b 316
f1129fb8
NC
317 case bfd_mach_arm_5TE:
318 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
319 break;
320
f1129fb8
NC
321 case bfd_mach_arm_4:
322 case bfd_mach_arm_4T:
323 ARMul_SelectProcessor (state, ARM_v4_Prop);
324 break;
325
326 case bfd_mach_arm_3:
327 case bfd_mach_arm_3M:
3943c96b
NC
328 ARMul_SelectProcessor (state, ARM_Lock_Prop);
329 break;
330
f1129fb8
NC
331 case bfd_mach_arm_2:
332 case bfd_mach_arm_2a:
3943c96b
NC
333 ARMul_SelectProcessor (state, ARM_Fix26_Prop);
334 break;
335 }
336
5f7d0a33
NC
337 if ( mach != bfd_mach_arm_3
338 && mach != bfd_mach_arm_3M
339 && mach != bfd_mach_arm_2
340 && mach != bfd_mach_arm_2a)
f1129fb8
NC
341 {
342 /* Reset mode to ARM. A gdb user may rerun a program that had entered
343 THUMB mode from the start and cause the ARM-mode startup code to be
5f7d0a33
NC
344 executed in THUMB mode. */
345 ARMul_SetCPSR (state, SVC32MODE);
f1129fb8
NC
346 }
347
c906108c
SS
348 if (argv != NULL)
349 {
5f7d0a33
NC
350 /* Set up the command line by laboriously stringing together
351 the environment carefully picked apart by our caller. */
352
353 /* Free any old stuff. */
c906108c
SS
354 if (state->CommandLine != NULL)
355 {
dfcd3bfb 356 free (state->CommandLine);
c906108c
SS
357 state->CommandLine = NULL;
358 }
dfcd3bfb 359
5f7d0a33 360 /* See how much we need. */
c906108c 361 for (arg = argv; *arg != NULL; arg++)
dfcd3bfb
JM
362 argvlen += strlen (*arg) + 1;
363
5f7d0a33 364 /* Allocate it. */
dfcd3bfb 365 state->CommandLine = malloc (argvlen + 1);
c906108c
SS
366 if (state->CommandLine != NULL)
367 {
368 arg = argv;
dfcd3bfb 369 state->CommandLine[0] = '\0';
5f7d0a33 370
c906108c
SS
371 for (arg = argv; *arg != NULL; arg++)
372 {
dfcd3bfb
JM
373 strcat (state->CommandLine, *arg);
374 strcat (state->CommandLine, " ");
c906108c
SS
375 }
376 }
377 }
378
379 if (env != NULL)
380 {
5f7d0a33 381 /* Now see if there's a MEMSIZE spec in the environment. */
c906108c
SS
382 while (*env)
383 {
dfcd3bfb 384 if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
c906108c 385 {
c906108c 386 char *end_of_num;
dfcd3bfb 387
5f7d0a33 388 /* Set up memory limit. */
dfcd3bfb
JM
389 state->MemSize =
390 strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
c906108c
SS
391 }
392 env++;
393 }
394 }
395
396 return SIM_RC_OK;
397}
398
399void
400sim_info (sd, verbose)
6d358e86
NC
401 SIM_DESC sd ATTRIBUTE_UNUSED;
402 int verbose ATTRIBUTE_UNUSED;
c906108c
SS
403{
404}
405
dfcd3bfb 406static int
c906108c
SS
407frommem (state, memory)
408 struct ARMul_State *state;
409 unsigned char *memory;
410{
411 if (state->bigendSig == HIGH)
86c735a5
NC
412 return (memory[0] << 24) | (memory[1] << 16)
413 | (memory[2] << 8) | (memory[3] << 0);
c906108c 414 else
86c735a5
NC
415 return (memory[3] << 24) | (memory[2] << 16)
416 | (memory[1] << 8) | (memory[0] << 0);
c906108c
SS
417}
418
c906108c 419static void
dfcd3bfb 420tomem (state, memory, val)
c906108c
SS
421 struct ARMul_State *state;
422 unsigned char *memory;
423 int val;
424{
425 if (state->bigendSig == HIGH)
426 {
427 memory[0] = val >> 24;
428 memory[1] = val >> 16;
429 memory[2] = val >> 8;
430 memory[3] = val >> 0;
431 }
432 else
433 {
434 memory[3] = val >> 24;
435 memory[2] = val >> 16;
436 memory[1] = val >> 8;
437 memory[0] = val >> 0;
438 }
439}
440
441int
442sim_store_register (sd, rn, memory, length)
6d358e86 443 SIM_DESC sd ATTRIBUTE_UNUSED;
c906108c
SS
444 int rn;
445 unsigned char *memory;
6d358e86 446 int length ATTRIBUTE_UNUSED;
c906108c
SS
447{
448 init ();
f1129fb8 449
26216b98 450 switch ((enum sim_arm_regs) rn)
3463c3fb 451 {
26216b98
AC
452 case SIM_ARM_R0_REGNUM:
453 case SIM_ARM_R1_REGNUM:
454 case SIM_ARM_R2_REGNUM:
455 case SIM_ARM_R3_REGNUM:
456 case SIM_ARM_R4_REGNUM:
457 case SIM_ARM_R5_REGNUM:
458 case SIM_ARM_R6_REGNUM:
459 case SIM_ARM_R7_REGNUM:
460 case SIM_ARM_R8_REGNUM:
461 case SIM_ARM_R9_REGNUM:
462 case SIM_ARM_R10_REGNUM:
463 case SIM_ARM_R11_REGNUM:
464 case SIM_ARM_R12_REGNUM:
465 case SIM_ARM_R13_REGNUM:
466 case SIM_ARM_R14_REGNUM:
467 case SIM_ARM_R15_REGNUM: /* PC */
468 case SIM_ARM_FP0_REGNUM:
469 case SIM_ARM_FP1_REGNUM:
470 case SIM_ARM_FP2_REGNUM:
471 case SIM_ARM_FP3_REGNUM:
472 case SIM_ARM_FP4_REGNUM:
473 case SIM_ARM_FP5_REGNUM:
474 case SIM_ARM_FP6_REGNUM:
475 case SIM_ARM_FP7_REGNUM:
476 case SIM_ARM_FPS_REGNUM:
477 ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
478 break;
479
480 case SIM_ARM_PS_REGNUM:
3463c3fb 481 state->Cpsr = frommem (state, memory);
10b57fcb 482 ARMul_CPSRAltered (state);
26216b98
AC
483 break;
484
f603c8fe
NC
485 case SIM_ARM_MAVERIC_COP0R0_REGNUM:
486 case SIM_ARM_MAVERIC_COP0R1_REGNUM:
487 case SIM_ARM_MAVERIC_COP0R2_REGNUM:
488 case SIM_ARM_MAVERIC_COP0R3_REGNUM:
489 case SIM_ARM_MAVERIC_COP0R4_REGNUM:
490 case SIM_ARM_MAVERIC_COP0R5_REGNUM:
491 case SIM_ARM_MAVERIC_COP0R6_REGNUM:
492 case SIM_ARM_MAVERIC_COP0R7_REGNUM:
493 case SIM_ARM_MAVERIC_COP0R8_REGNUM:
494 case SIM_ARM_MAVERIC_COP0R9_REGNUM:
495 case SIM_ARM_MAVERIC_COP0R10_REGNUM:
496 case SIM_ARM_MAVERIC_COP0R11_REGNUM:
497 case SIM_ARM_MAVERIC_COP0R12_REGNUM:
498 case SIM_ARM_MAVERIC_COP0R13_REGNUM:
499 case SIM_ARM_MAVERIC_COP0R14_REGNUM:
500 case SIM_ARM_MAVERIC_COP0R15_REGNUM:
501 memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
502 memory, sizeof (struct maverick_regs));
503 return sizeof (struct maverick_regs);
504
505 case SIM_ARM_MAVERIC_DSPSC_REGNUM:
506 memcpy (&DSPsc, memory, sizeof DSPsc);
507 return sizeof DSPsc;
508
0f026fd0
NC
509 case SIM_ARM_IWMMXT_COP0R0_REGNUM:
510 case SIM_ARM_IWMMXT_COP0R1_REGNUM:
511 case SIM_ARM_IWMMXT_COP0R2_REGNUM:
512 case SIM_ARM_IWMMXT_COP0R3_REGNUM:
513 case SIM_ARM_IWMMXT_COP0R4_REGNUM:
514 case SIM_ARM_IWMMXT_COP0R5_REGNUM:
515 case SIM_ARM_IWMMXT_COP0R6_REGNUM:
516 case SIM_ARM_IWMMXT_COP0R7_REGNUM:
517 case SIM_ARM_IWMMXT_COP0R8_REGNUM:
518 case SIM_ARM_IWMMXT_COP0R9_REGNUM:
519 case SIM_ARM_IWMMXT_COP0R10_REGNUM:
520 case SIM_ARM_IWMMXT_COP0R11_REGNUM:
521 case SIM_ARM_IWMMXT_COP0R12_REGNUM:
522 case SIM_ARM_IWMMXT_COP0R13_REGNUM:
523 case SIM_ARM_IWMMXT_COP0R14_REGNUM:
524 case SIM_ARM_IWMMXT_COP0R15_REGNUM:
525 case SIM_ARM_IWMMXT_COP1R0_REGNUM:
526 case SIM_ARM_IWMMXT_COP1R1_REGNUM:
527 case SIM_ARM_IWMMXT_COP1R2_REGNUM:
528 case SIM_ARM_IWMMXT_COP1R3_REGNUM:
529 case SIM_ARM_IWMMXT_COP1R4_REGNUM:
530 case SIM_ARM_IWMMXT_COP1R5_REGNUM:
531 case SIM_ARM_IWMMXT_COP1R6_REGNUM:
532 case SIM_ARM_IWMMXT_COP1R7_REGNUM:
533 case SIM_ARM_IWMMXT_COP1R8_REGNUM:
534 case SIM_ARM_IWMMXT_COP1R9_REGNUM:
535 case SIM_ARM_IWMMXT_COP1R10_REGNUM:
536 case SIM_ARM_IWMMXT_COP1R11_REGNUM:
537 case SIM_ARM_IWMMXT_COP1R12_REGNUM:
538 case SIM_ARM_IWMMXT_COP1R13_REGNUM:
539 case SIM_ARM_IWMMXT_COP1R14_REGNUM:
540 case SIM_ARM_IWMMXT_COP1R15_REGNUM:
541 return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
3a3d6f65 542
26216b98
AC
543 default:
544 return 0;
3463c3fb 545 }
26216b98 546
c906108c
SS
547 return -1;
548}
549
550int
551sim_fetch_register (sd, rn, memory, length)
6d358e86 552 SIM_DESC sd ATTRIBUTE_UNUSED;
c906108c
SS
553 int rn;
554 unsigned char *memory;
6d358e86 555 int length ATTRIBUTE_UNUSED;
c906108c
SS
556{
557 ARMword regval;
558
559 init ();
f1129fb8 560
26216b98
AC
561 switch ((enum sim_arm_regs) rn)
562 {
563 case SIM_ARM_R0_REGNUM:
564 case SIM_ARM_R1_REGNUM:
565 case SIM_ARM_R2_REGNUM:
566 case SIM_ARM_R3_REGNUM:
567 case SIM_ARM_R4_REGNUM:
568 case SIM_ARM_R5_REGNUM:
569 case SIM_ARM_R6_REGNUM:
570 case SIM_ARM_R7_REGNUM:
571 case SIM_ARM_R8_REGNUM:
572 case SIM_ARM_R9_REGNUM:
573 case SIM_ARM_R10_REGNUM:
574 case SIM_ARM_R11_REGNUM:
575 case SIM_ARM_R12_REGNUM:
576 case SIM_ARM_R13_REGNUM:
577 case SIM_ARM_R14_REGNUM:
578 case SIM_ARM_R15_REGNUM: /* PC */
579 regval = ARMul_GetReg (state, state->Mode, rn);
580 break;
581
582 case SIM_ARM_FP0_REGNUM:
583 case SIM_ARM_FP1_REGNUM:
584 case SIM_ARM_FP2_REGNUM:
585 case SIM_ARM_FP3_REGNUM:
586 case SIM_ARM_FP4_REGNUM:
587 case SIM_ARM_FP5_REGNUM:
588 case SIM_ARM_FP6_REGNUM:
589 case SIM_ARM_FP7_REGNUM:
590 case SIM_ARM_FPS_REGNUM:
591 memset (memory, 0, length);
592 return 0;
593
594 case SIM_ARM_PS_REGNUM:
595 regval = ARMul_GetCPSR (state);
596 break;
597
f603c8fe
NC
598 case SIM_ARM_MAVERIC_COP0R0_REGNUM:
599 case SIM_ARM_MAVERIC_COP0R1_REGNUM:
600 case SIM_ARM_MAVERIC_COP0R2_REGNUM:
601 case SIM_ARM_MAVERIC_COP0R3_REGNUM:
602 case SIM_ARM_MAVERIC_COP0R4_REGNUM:
603 case SIM_ARM_MAVERIC_COP0R5_REGNUM:
604 case SIM_ARM_MAVERIC_COP0R6_REGNUM:
605 case SIM_ARM_MAVERIC_COP0R7_REGNUM:
606 case SIM_ARM_MAVERIC_COP0R8_REGNUM:
607 case SIM_ARM_MAVERIC_COP0R9_REGNUM:
608 case SIM_ARM_MAVERIC_COP0R10_REGNUM:
609 case SIM_ARM_MAVERIC_COP0R11_REGNUM:
610 case SIM_ARM_MAVERIC_COP0R12_REGNUM:
611 case SIM_ARM_MAVERIC_COP0R13_REGNUM:
612 case SIM_ARM_MAVERIC_COP0R14_REGNUM:
613 case SIM_ARM_MAVERIC_COP0R15_REGNUM:
614 memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
615 sizeof (struct maverick_regs));
616 return sizeof (struct maverick_regs);
617
618 case SIM_ARM_MAVERIC_DSPSC_REGNUM:
619 memcpy (memory, & DSPsc, sizeof DSPsc);
620 return sizeof DSPsc;
621
0f026fd0
NC
622 case SIM_ARM_IWMMXT_COP0R0_REGNUM:
623 case SIM_ARM_IWMMXT_COP0R1_REGNUM:
624 case SIM_ARM_IWMMXT_COP0R2_REGNUM:
625 case SIM_ARM_IWMMXT_COP0R3_REGNUM:
626 case SIM_ARM_IWMMXT_COP0R4_REGNUM:
627 case SIM_ARM_IWMMXT_COP0R5_REGNUM:
628 case SIM_ARM_IWMMXT_COP0R6_REGNUM:
629 case SIM_ARM_IWMMXT_COP0R7_REGNUM:
630 case SIM_ARM_IWMMXT_COP0R8_REGNUM:
631 case SIM_ARM_IWMMXT_COP0R9_REGNUM:
632 case SIM_ARM_IWMMXT_COP0R10_REGNUM:
633 case SIM_ARM_IWMMXT_COP0R11_REGNUM:
634 case SIM_ARM_IWMMXT_COP0R12_REGNUM:
635 case SIM_ARM_IWMMXT_COP0R13_REGNUM:
636 case SIM_ARM_IWMMXT_COP0R14_REGNUM:
637 case SIM_ARM_IWMMXT_COP0R15_REGNUM:
638 case SIM_ARM_IWMMXT_COP1R0_REGNUM:
639 case SIM_ARM_IWMMXT_COP1R1_REGNUM:
640 case SIM_ARM_IWMMXT_COP1R2_REGNUM:
641 case SIM_ARM_IWMMXT_COP1R3_REGNUM:
642 case SIM_ARM_IWMMXT_COP1R4_REGNUM:
643 case SIM_ARM_IWMMXT_COP1R5_REGNUM:
644 case SIM_ARM_IWMMXT_COP1R6_REGNUM:
645 case SIM_ARM_IWMMXT_COP1R7_REGNUM:
646 case SIM_ARM_IWMMXT_COP1R8_REGNUM:
647 case SIM_ARM_IWMMXT_COP1R9_REGNUM:
648 case SIM_ARM_IWMMXT_COP1R10_REGNUM:
649 case SIM_ARM_IWMMXT_COP1R11_REGNUM:
650 case SIM_ARM_IWMMXT_COP1R12_REGNUM:
651 case SIM_ARM_IWMMXT_COP1R13_REGNUM:
652 case SIM_ARM_IWMMXT_COP1R14_REGNUM:
653 case SIM_ARM_IWMMXT_COP1R15_REGNUM:
654 return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
3a3d6f65 655
26216b98
AC
656 default:
657 return 0;
658 }
272fcdcd
NC
659
660 while (length)
661 {
662 tomem (state, memory, regval);
663
664 length -= 4;
665 memory += 4;
666 regval = 0;
667 }
668
c906108c
SS
669 return -1;
670}
671
de4112fa
NC
672#ifdef SIM_TARGET_SWITCHES
673
674static void sim_target_parse_arg_array PARAMS ((char **));
675
676typedef struct
677{
678 char * swi_option;
679 unsigned int swi_mask;
680} swi_options;
681
682#define SWI_SWITCH "--swi-support"
683
684static swi_options options[] =
685 {
686 { "none", 0 },
687 { "demon", SWI_MASK_DEMON },
688 { "angel", SWI_MASK_ANGEL },
689 { "redboot", SWI_MASK_REDBOOT },
690 { "all", -1 },
691 { "NONE", 0 },
692 { "DEMON", SWI_MASK_DEMON },
693 { "ANGEL", SWI_MASK_ANGEL },
694 { "REDBOOT", SWI_MASK_REDBOOT },
695 { "ALL", -1 }
696 };
697
698
699int
700sim_target_parse_command_line (argc, argv)
701 int argc;
702 char ** argv;
703{
704 int i;
705
706 for (i = 1; i < argc; i++)
707 {
708 char * ptr = argv[i];
709 int arg;
710
711 if ((ptr == NULL) || (* ptr != '-'))
712 break;
713
714 if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
715 continue;
716
717 if (ptr[sizeof SWI_SWITCH - 1] == 0)
718 {
719 /* Remove this option from the argv array. */
720 for (arg = i; arg < argc; arg ++)
721 argv[arg] = argv[arg + 1];
722 argc --;
723
724 ptr = argv[i];
725 }
726 else
727 ptr += sizeof SWI_SWITCH;
728
729 swi_mask = 0;
730
731 while (* ptr)
732 {
733 int i;
734
735 for (i = sizeof options / sizeof options[0]; i--;)
736 if (strncmp (ptr, options[i].swi_option,
737 strlen (options[i].swi_option)) == 0)
738 {
739 swi_mask |= options[i].swi_mask;
740 ptr += strlen (options[i].swi_option);
741
742 if (* ptr == ',')
743 ++ ptr;
744
745 break;
746 }
747
748 if (i < 0)
749 break;
750 }
751
752 if (* ptr != 0)
753 fprintf (stderr, "Ignoring swi options: %s\n", ptr);
754
755 /* Remove this option from the argv array. */
756 for (arg = i; arg < argc; arg ++)
757 argv[arg] = argv[arg + 1];
758 argc --;
759 i --;
760 }
761 return argc;
762}
763
764static void
765sim_target_parse_arg_array (argv)
766 char ** argv;
767{
768 int i;
769
770 for (i = 0; argv[i]; i++)
771 ;
772
773 return (void) sim_target_parse_command_line (i, argv);
774}
775
776void
777sim_target_display_usage ()
778{
779 fprintf (stderr, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\
780 This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
781 SWI_SWITCH);
782}
783#endif
784
c906108c
SS
785SIM_DESC
786sim_open (kind, ptr, abfd, argv)
787 SIM_OPEN_KIND kind;
788 host_callback *ptr;
6b4a8935 789 struct bfd *abfd;
c906108c
SS
790 char **argv;
791{
792 sim_kind = kind;
6c9e0292 793 if (myname) free (myname);
c1a72ffd 794 myname = (char *) xstrdup (argv[0]);
c906108c 795 sim_callback = ptr;
dfcd3bfb 796
de4112fa
NC
797#ifdef SIM_TARGET_SWITCHES
798 sim_target_parse_arg_array (argv);
799#endif
800
c906108c
SS
801 /* Decide upon the endian-ness of the processor.
802 If we can, get the information from the bfd itself.
803 Otherwise look to see if we have been given a command
804 line switch that tells us. Otherwise default to little endian. */
805 if (abfd != NULL)
806 big_endian = bfd_big_endian (abfd);
807 else if (argv[1] != NULL)
808 {
809 int i;
dfcd3bfb 810
058f270d 811 /* Scan for endian-ness and memory-size switches. */
c906108c 812 for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
dfcd3bfb
JM
813 if (argv[i][0] == '-' && argv[i][1] == 'E')
814 {
815 char c;
816
817 if ((c = argv[i][2]) == 0)
818 {
819 ++i;
820 c = argv[i][0];
821 }
822
823 switch (c)
824 {
825 case 0:
826 sim_callback->printf_filtered
827 (sim_callback, "No argument to -E option provided\n");
828 break;
829
830 case 'b':
831 case 'B':
832 big_endian = 1;
833 break;
834
835 case 'l':
836 case 'L':
837 big_endian = 0;
838 break;
839
840 default:
841 sim_callback->printf_filtered
842 (sim_callback, "Unrecognised argument to -E option\n");
843 break;
844 }
845 }
058f270d
AC
846 else if (argv[i][0] == '-' && argv[i][1] == 'm')
847 {
848 if (argv[i][2] != '\0')
849 sim_size (atoi (&argv[i][2]));
850 else if (argv[i + 1] != NULL)
851 {
852 sim_size (atoi (argv[i + 1]));
853 i++;
854 }
855 else
856 {
857 sim_callback->printf_filtered (sim_callback,
858 "Missing argument to -m option\n");
859 return NULL;
860 }
861
862 }
c906108c
SS
863 }
864
865 return (SIM_DESC) 1;
866}
867
868void
869sim_close (sd, quitting)
6d358e86
NC
870 SIM_DESC sd ATTRIBUTE_UNUSED;
871 int quitting ATTRIBUTE_UNUSED;
c906108c 872{
86c735a5
NC
873 if (myname)
874 free (myname);
6c9e0292 875 myname = NULL;
c906108c
SS
876}
877
878SIM_RC
879sim_load (sd, prog, abfd, from_tty)
880 SIM_DESC sd;
881 char *prog;
882 bfd *abfd;
6d358e86 883 int from_tty ATTRIBUTE_UNUSED;
c906108c 884{
c906108c
SS
885 bfd *prog_bfd;
886
887 prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
dfcd3bfb 888 sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
c906108c
SS
889 if (prog_bfd == NULL)
890 return SIM_RC_FAIL;
891 ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
892 if (abfd == NULL)
893 bfd_close (prog_bfd);
894 return SIM_RC_OK;
895}
896
897void
898sim_stop_reason (sd, reason, sigrc)
6d358e86 899 SIM_DESC sd ATTRIBUTE_UNUSED;
c906108c
SS
900 enum sim_stop *reason;
901 int *sigrc;
902{
7a292a7a
SS
903 if (stop_simulator)
904 {
905 *reason = sim_stopped;
aba6488e 906 *sigrc = TARGET_SIGNAL_INT;
7a292a7a
SS
907 }
908 else if (state->EndCondition == 0)
c906108c
SS
909 {
910 *reason = sim_exited;
911 *sigrc = state->Reg[0] & 255;
912 }
913 else
914 {
915 *reason = sim_stopped;
916 if (state->EndCondition == RDIError_BreakpointReached)
aba6488e 917 *sigrc = TARGET_SIGNAL_TRAP;
0f026fd0
NC
918 else if ( state->EndCondition == RDIError_DataAbort
919 || state->EndCondition == RDIError_AddressException)
aba6488e 920 *sigrc = TARGET_SIGNAL_BUS;
c906108c
SS
921 else
922 *sigrc = 0;
923 }
924}
925
926void
927sim_do_command (sd, cmd)
6d358e86
NC
928 SIM_DESC sd ATTRIBUTE_UNUSED;
929 char *cmd ATTRIBUTE_UNUSED;
dfcd3bfb 930{
86c735a5
NC
931 (*sim_callback->printf_filtered)
932 (sim_callback,
933 "This simulator does not accept any commands.\n");
c906108c
SS
934}
935
c906108c
SS
936void
937sim_set_callbacks (ptr)
938 host_callback *ptr;
939{
940 sim_callback = ptr;
941}