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df1756f4 1/* Simulator for Atmel's AVR core.
1d506c26 2 Copyright (C) 2009-2024 Free Software Foundation, Inc.
df1756f4
TG		 3 Written by Tristan Gingold, AdaCore.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
6df01ab8
MF		 20/* This must come before any other includes. */
21#include "defs.h"
df1756f4 22
df1756f4 23#include <string.h>
68ed2854 24
df1756f4 25#include "bfd.h"
df1756f4 26#include "libiberty.h"
df68e12b 27#include "sim/sim.h"
9943d318
MF		 28
29#include "sim-main.h"
30#include "sim-base.h"
31#include "sim-options.h"
1fef66b0 32#include "sim-signal.h"
42b68db1 33#include "avr-sim.h"
df1756f4
TG		 34
35/* As AVR is a 8/16 bits processor, define handy types. */
36typedef unsigned short int word;
37typedef signed short int sword;
38typedef unsigned char byte;
39typedef signed char sbyte;
40
df1756f4
TG		 41/* Max size of I space (which is always flash on avr). */
42#define MAX_AVR_FLASH (128 * 1024)
43#define PC_MASK (MAX_AVR_FLASH - 1)
44
45/* Mac size of D space. */
46#define MAX_AVR_SRAM (64 * 1024)
47#define SRAM_MASK (MAX_AVR_SRAM - 1)
48
49/* D space offset in ELF file. */
50#define SRAM_VADDR 0x800000
51
52/* Simulator specific ports. */
53#define STDIO_PORT 0x52
54#define EXIT_PORT 0x4F
55#define ABORT_PORT 0x49
56
57/* GDB defined register numbers. */
58#define AVR_SREG_REGNUM 32
59#define AVR_SP_REGNUM 33
60#define AVR_PC_REGNUM 34
61
62/* Memory mapped registers. */
63#define SREG 0x5F
64#define REG_SP 0x5D
65#define EIND 0x5C
66#define RAMPZ 0x5B
67
68#define REGX 0x1a
69#define REGY 0x1c
70#define REGZ 0x1e
71#define REGZ_LO 0x1e
72#define REGZ_HI 0x1f
73
74/* Sreg (status) bits. */
75#define SREG_I 0x80
76#define SREG_T 0x40
77#define SREG_H 0x20
78#define SREG_S 0x10
79#define SREG_V 0x08
80#define SREG_N 0x04
81#define SREG_Z 0x02
82#define SREG_C 0x01
83
84/* In order to speed up emulation we use a simple approach:
85 a code is associated with each instruction. The pre-decoding occurs
86 usually once when the instruction is first seen.
87 This works well because I&D spaces are separated.
88
89 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
90*/
91enum avr_opcode
92 {
93 /* Opcode not yet decoded. */
94 OP_unknown,
95 OP_bad,
96
97 OP_nop,
98
99 OP_rjmp,
100 OP_rcall,
101 OP_ret,
102 OP_reti,
103
104 OP_break,
105
106 OP_brbs,
107 OP_brbc,
108
109 OP_bset,
110 OP_bclr,
111
112 OP_bld,
113 OP_bst,
114
115 OP_sbrc,
116 OP_sbrs,
117
118 OP_eor,
119 OP_and,
120 OP_andi,
121 OP_or,
122 OP_ori,
123 OP_com,
124 OP_swap,
125 OP_neg,
126
127 OP_out,
128 OP_in,
129 OP_cbi,
130 OP_sbi,
131
132 OP_sbic,
133 OP_sbis,
134
135 OP_ldi,
136 OP_cpse,
137 OP_cp,
138 OP_cpi,
139 OP_cpc,
140 OP_sub,
141 OP_sbc,
142 OP_sbiw,
143 OP_adiw,
144 OP_add,
145 OP_adc,
146 OP_subi,
147 OP_sbci,
148 OP_inc,
149 OP_dec,
150 OP_lsr,
151 OP_ror,
152 OP_asr,
153
154 OP_mul,
155 OP_muls,
156 OP_mulsu,
157 OP_fmul,
158 OP_fmuls,
159 OP_fmulsu,
160
161 OP_mov,
162 OP_movw,
163
164 OP_push,
165 OP_pop,
166
167 OP_st_X,
168 OP_st_dec_X,
169 OP_st_X_inc,
170 OP_st_Y_inc,
171 OP_st_dec_Y,
172 OP_st_Z_inc,
173 OP_st_dec_Z,
174 OP_std_Y,
175 OP_std_Z,
176 OP_ldd_Y,
177 OP_ldd_Z,
178 OP_ld_Z_inc,
179 OP_ld_dec_Z,
180 OP_ld_Y_inc,
181 OP_ld_dec_Y,
182 OP_ld_X,
183 OP_ld_X_inc,
184 OP_ld_dec_X,
185
186 OP_lpm,
187 OP_lpm_Z,
188 OP_lpm_inc_Z,
189 OP_elpm,
190 OP_elpm_Z,
191 OP_elpm_inc_Z,
192
193 OP_ijmp,
194 OP_icall,
195
196 OP_eijmp,
197 OP_eicall,
198
199 /* 2 words opcodes. */
200#define OP_2words OP_jmp
201 OP_jmp,
202 OP_call,
203 OP_sts,
204 OP_lds
205 };
206
207struct avr_insn_cell
208{
209 /* The insn (16 bits). */
210 word op;
211
212 /* Pre-decoding code. */
213 enum avr_opcode code : 8;
214 /* One byte of additional information. */
215 byte r;
216};
217
218/* I&D memories. */
9943d318 219/* TODO: Should be moved to SIM_CPU. */
df1756f4
TG		 220static struct avr_insn_cell flash[MAX_AVR_FLASH];
221static byte sram[MAX_AVR_SRAM];
222
df1756f4
TG		 223/* Sign extend a value. */
224static int sign_ext (word val, int nb_bits)
225{
226 if (val & (1 << (nb_bits - 1)))
1d19cae7 227 return val | -(1 << nb_bits);
df1756f4
TG		 228 return val;
229}
230
231/* Insn field extractors. */
232
233/* Extract xxxx_xxxRx_xxxx_RRRR. */
234static inline byte get_r (word op)
235{
236 return (op & 0xf) | ((op >> 5) & 0x10);
237}
238
239/* Extract xxxx_xxxxx_xxxx_RRRR. */
240static inline byte get_r16 (word op)
241{
242 return 16 + (op & 0xf);
243}
244
245/* Extract xxxx_xxxxx_xxxx_xRRR. */
246static inline byte get_r16_23 (word op)
247{
248 return 16 + (op & 0x7);
249}
250
251/* Extract xxxx_xxxD_DDDD_xxxx. */
252static inline byte get_d (word op)
253{
254 return (op >> 4) & 0x1f;
255}
256
257/* Extract xxxx_xxxx_DDDD_xxxx. */
258static inline byte get_d16 (word op)
259{
260 return 16 + ((op >> 4) & 0x0f);
261}
262
263/* Extract xxxx_xxxx_xDDD_xxxx. */
264static inline byte get_d16_23 (word op)
265{
266 return 16 + ((op >> 4) & 0x07);
267}
268
269/* Extract xxxx_xAAx_xxxx_AAAA. */
270static inline byte get_A (word op)
271{
272 return (op & 0x0f) | ((op & 0x600) >> 5);
273}
274
275/* Extract xxxx_xxxx_AAAA_Axxx. */
276static inline byte get_biA (word op)
277{
278 return (op >> 3) & 0x1f;
279}
280
281/* Extract xxxx_KKKK_xxxx_KKKK. */
282static inline byte get_K (word op)
283{
284 return (op & 0xf) | ((op & 0xf00) >> 4);
285}
286
287/* Extract xxxx_xxKK_KKKK_Kxxx. */
288static inline int get_k (word op)
289{
290 return sign_ext ((op & 0x3f8) >> 3, 7);
291}
292
293/* Extract xxxx_xxxx_xxDD_xxxx. */
294static inline byte get_d24 (word op)
295{
296 return 24 + ((op >> 3) & 6);
297}
298
299/* Extract xxxx_xxxx_KKxx_KKKK. */
300static inline byte get_k6 (word op)
301{
302 return (op & 0xf) | ((op >> 2) & 0x30);
303}
304
305/* Extract xxQx_QQxx_xxxx_xQQQ. */
306static inline byte get_q (word op)
307{
308 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
309}
310
311/* Extract xxxx_xxxx_xxxx_xBBB. */
312static inline byte get_b (word op)
313{
314 return (op & 7);
315}
316
317/* AVR is little endian. */
318static inline word
319read_word (unsigned int addr)
320{
321 return sram[addr] | (sram[addr + 1] << 8);
322}
323
324static inline void
325write_word (unsigned int addr, word w)
326{
327 sram[addr] = w;
328 sram[addr + 1] = w >> 8;
329}
330
331static inline word
332read_word_post_inc (unsigned int addr)
333{
334 word v = read_word (addr);
335 write_word (addr, v + 1);
336 return v;
337}
338
339static inline word
340read_word_pre_dec (unsigned int addr)
341{
342 word v = read_word (addr) - 1;
343 write_word (addr, v);
344 return v;
345}
346
347static void
348update_flags_logic (byte res)
349{
350 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
351 if (res == 0)
352 sram[SREG] |= SREG_Z;
353 if (res & 0x80)
354 sram[SREG] |= SREG_N | SREG_S;
355}
356
357static void
358update_flags_add (byte r, byte a, byte b)
359{
360 byte carry;
361
362 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
363 if (r & 0x80)
364 sram[SREG] |= SREG_N;
365 carry = (a & b) | (a & ~r) | (b & ~r);
366 if (carry & 0x08)
367 sram[SREG] |= SREG_H;
368 if (carry & 0x80)
369 sram[SREG] |= SREG_C;
370 if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
371 sram[SREG] |= SREG_V;
372 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
373 sram[SREG] |= SREG_S;
374 if (r == 0)
375 sram[SREG] |= SREG_Z;
376}
377
378static void update_flags_sub (byte r, byte a, byte b)
379{
380 byte carry;
381
382 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
383 if (r & 0x80)
384 sram[SREG] |= SREG_N;
385 carry = (~a & b) | (b & r) | (r & ~a);
386 if (carry & 0x08)
387 sram[SREG] |= SREG_H;
388 if (carry & 0x80)
389 sram[SREG] |= SREG_C;
390 if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
391 sram[SREG] |= SREG_V;
392 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
393 sram[SREG] |= SREG_S;
394 /* Note: Z is not set. */
395}
396
397static enum avr_opcode
398decode (unsigned int pc)
399{
400 word op1 = flash[pc].op;
401
402 switch ((op1 >> 12) & 0x0f)
403 {
404 case 0x0:
405 switch ((op1 >> 10) & 0x3)
406 {
407 case 0x0:
408 switch ((op1 >> 8) & 0x3)
409 {
410 case 0x0:
411 if (op1 == 0)
412 return OP_nop;
413 break;
414 case 0x1:
415 return OP_movw;
416 case 0x2:
417 return OP_muls;
418 case 0x3:
419 if (op1 & 0x80)
420 {
421 if (op1 & 0x08)
422 return OP_fmulsu;
423 else
424 return OP_fmuls;
425 }
426 else
427 {
428 if (op1 & 0x08)
429 return OP_fmul;
430 else
431 return OP_mulsu;
432 }
433 }
434 break;
435 case 0x1:
436 return OP_cpc;
437 case 0x2:
438 flash[pc].r = SREG_C;
439 return OP_sbc;
440 case 0x3:
441 flash[pc].r = 0;
442 return OP_add;
443 }
444 break;
445 case 0x1:
446 switch ((op1 >> 10) & 0x3)
447 {
448 case 0x0:
449 return OP_cpse;
450 case 0x1:
451 return OP_cp;
452 case 0x2:
453 flash[pc].r = 0;
454 return OP_sub;
455 case 0x3:
456 flash[pc].r = SREG_C;
457 return OP_adc;
458 }
459 break;
460 case 0x2:
461 switch ((op1 >> 10) & 0x3)
462 {
463 case 0x0:
464 return OP_and;
465 case 0x1:
466 return OP_eor;
467 case 0x2:
468 return OP_or;
469 case 0x3:
470 return OP_mov;
471 }
472 break;
473 case 0x3:
474 return OP_cpi;
475 case 0x4:
476 return OP_sbci;
477 case 0x5:
478 return OP_subi;
479 case 0x6:
480 return OP_ori;
481 case 0x7:
482 return OP_andi;
483 case 0x8:
484 case 0xa:
485 if (op1 & 0x0200)
486 {
487 if (op1 & 0x0008)
488 {
489 flash[pc].r = get_q (op1);
490 return OP_std_Y;
491 }
492 else
493 {
494 flash[pc].r = get_q (op1);
495 return OP_std_Z;
496 }
497 }
498 else
499 {
500 if (op1 & 0x0008)
501 {
502 flash[pc].r = get_q (op1);
503 return OP_ldd_Y;
504 }
505 else
506 {
507 flash[pc].r = get_q (op1);
508 return OP_ldd_Z;
509 }
510 }
511 break;
512 case 0x9: /* 9xxx */
513 switch ((op1 >> 8) & 0xf)
514 {
515 case 0x0:
516 case 0x1:
517 switch ((op1 >> 0) & 0xf)
518 {
519 case 0x0:
520 return OP_lds;
521 case 0x1:
522 return OP_ld_Z_inc;
523 case 0x2:
524 return OP_ld_dec_Z;
525 case 0x4:
526 return OP_lpm_Z;
527 case 0x5:
528 return OP_lpm_inc_Z;
529 case 0x6:
530 return OP_elpm_Z;
531 case 0x7:
532 return OP_elpm_inc_Z;
533 case 0x9:
534 return OP_ld_Y_inc;
535 case 0xa:
536 return OP_ld_dec_Y;
537 case 0xc:
538 return OP_ld_X;
539 case 0xd:
540 return OP_ld_X_inc;
541 case 0xe:
542 return OP_ld_dec_X;
543 case 0xf:
544 return OP_pop;
545 }
546 break;
547 case 0x2:
548 case 0x3:
549 switch ((op1 >> 0) & 0xf)
550 {
551 case 0x0:
552 return OP_sts;
553 case 0x1:
554 return OP_st_Z_inc;
555 case 0x2:
556 return OP_st_dec_Z;
557 case 0x9:
558 return OP_st_Y_inc;
559 case 0xa:
560 return OP_st_dec_Y;
561 case 0xc:
562 return OP_st_X;
563 case 0xd:
564 return OP_st_X_inc;
565 case 0xe:
566 return OP_st_dec_X;
567 case 0xf:
568 return OP_push;
569 }
570 break;
571 case 0x4:
572 case 0x5:
573 switch (op1 & 0xf)
574 {
575 case 0x0:
576 return OP_com;
577 case 0x1:
578 return OP_neg;
579 case 0x2:
580 return OP_swap;
581 case 0x3:
582 return OP_inc;
583 case 0x5:
584 flash[pc].r = 0x80;
585 return OP_asr;
586 case 0x6:
587 flash[pc].r = 0;
588 return OP_lsr;
589 case 0x7:
590 return OP_ror;
591 case 0x8: /* 9[45]x8 */
592 switch ((op1 >> 4) & 0x1f)
593 {
594 case 0x00:
595 case 0x01:
596 case 0x02:
597 case 0x03:
598 case 0x04:
599 case 0x05:
600 case 0x06:
601 case 0x07:
602 return OP_bset;
603 case 0x08:
604 case 0x09:
605 case 0x0a:
606 case 0x0b:
607 case 0x0c:
608 case 0x0d:
609 case 0x0e:
610 case 0x0f:
611 return OP_bclr;
612 case 0x10:
613 return OP_ret;
614 case 0x11:
615 return OP_reti;
616 case 0x19:
617 return OP_break;
618 case 0x1c:
619 return OP_lpm;
620 case 0x1d:
621 return OP_elpm;
622 default:
623 break;
624 }
625 break;
626 case 0x9: /* 9[45]x9 */
627 switch ((op1 >> 4) & 0x1f)
628 {
629 case 0x00:
630 return OP_ijmp;
631 case 0x01:
632 return OP_eijmp;
633 case 0x10:
634 return OP_icall;
635 case 0x11:
636 return OP_eicall;
637 default:
638 break;
639 }
640 break;
641 case 0xa:
642 return OP_dec;
643 case 0xc:
644 case 0xd:
645 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
646 return OP_jmp;
647 case 0xe:
648 case 0xf:
649 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
650 return OP_call;
651 }
652 break;
653 case 0x6:
654 return OP_adiw;
655 case 0x7:
656 return OP_sbiw;
657 case 0x8:
658 return OP_cbi;
659 case 0x9:
660 return OP_sbic;
661 case 0xa:
662 return OP_sbi;
663 case 0xb:
664 return OP_sbis;
665 case 0xc:
666 case 0xd:
667 case 0xe:
668 case 0xf:
669 return OP_mul;
670 }
671 break;
672 case 0xb:
673 flash[pc].r = get_A (op1);
674 if (((op1 >> 11) & 1) == 0)
675 return OP_in;
676 else
677 return OP_out;
678 case 0xc:
679 return OP_rjmp;
680 case 0xd:
681 return OP_rcall;
682 case 0xe:
683 return OP_ldi;
684 case 0xf:
685 switch ((op1 >> 9) & 7)
686 {
687 case 0:
688 case 1:
689 flash[pc].r = 1 << (op1 & 7);
690 return OP_brbs;
691 case 2:
692 case 3:
693 flash[pc].r = 1 << (op1 & 7);
694 return OP_brbc;
695 case 4:
696 if ((op1 & 8) == 0)
697 {
698 flash[pc].r = 1 << (op1 & 7);
699 return OP_bld;
700 }
701 break;
702 case 5:
703 if ((op1 & 8) == 0)
704 {
705 flash[pc].r = 1 << (op1 & 7);
706 return OP_bst;
707 }
708 break;
709 case 6:
710 if ((op1 & 8) == 0)
711 {
712 flash[pc].r = 1 << (op1 & 7);
713 return OP_sbrc;
714 }
715 break;
716 case 7:
717 if ((op1 & 8) == 0)
718 {
719 flash[pc].r = 1 << (op1 & 7);
720 return OP_sbrs;
721 }
722 break;
723 }
724 }
df1756f4 725
9943d318 726 return OP_bad;
df1756f4
TG		 727}
728
729static void
82d442c6 730do_call (SIM_CPU *cpu, unsigned int npc)
df1756f4 731{
937af0fd 732 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu));
f246dc72 733 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu);
df1756f4
TG		 734 unsigned int sp = read_word (REG_SP);
735
736 /* Big endian! */
f246dc72
MF		 737 sram[sp--] = avr_cpu->pc;
738 sram[sp--] = avr_cpu->pc >> 8;
937af0fd 739 if (state->avr_pc22)
df1756f4 740 {
f246dc72
MF		 741 sram[sp--] = avr_cpu->pc >> 16;
742 avr_cpu->cycles++;
df1756f4
TG		 743 }
744 write_word (REG_SP, sp);
f246dc72
MF		 745 avr_cpu->pc = npc & PC_MASK;
746 avr_cpu->cycles += 3;
df1756f4
TG		 747}
748
749static int
750get_insn_length (unsigned int p)
751{
752 if (flash[p].code == OP_unknown)
753 flash[p].code = decode(p);
754 if (flash[p].code >= OP_2words)
755 return 2;
756 else
757 return 1;
758}
759
760static unsigned int
761get_z (void)
762{
763 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
764}
765
766static unsigned char
767get_lpm (unsigned int addr)
768{
769 word w;
770
771 w = flash[(addr >> 1) & PC_MASK].op;
772 if (addr & 1)
773 w >>= 8;
774 return w;
775}
776
777static void
82d442c6 778gen_mul (SIM_CPU *cpu, unsigned int res)
df1756f4 779{
f246dc72
MF		 780 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu);
781
df1756f4
TG		 782 write_word (0, res);
783 sram[SREG] &= ~(SREG_Z | SREG_C);
784 if (res == 0)
785 sram[SREG] |= SREG_Z;
786 if (res & 0x8000)
787 sram[SREG] |= SREG_C;
f246dc72 788 avr_cpu->cycles++;
df1756f4
TG		 789}
790
9943d318
MF		 791static void
792step_once (SIM_CPU *cpu)
df1756f4 793{
f246dc72 794 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu);
df1756f4
TG		 795 unsigned int ipc;
796
9943d318
MF		 797 int code;
798 word op;
799 byte res;
800 byte r, d, vd;
df1756f4 801
9943d318 802 again:
f246dc72
MF		 803 code = flash[avr_cpu->pc].code;
804 op = flash[avr_cpu->pc].op;
df1756f4 805
9943d318
MF		 806#if 0
807 if (tracing && code != OP_unknown)
df1756f4
TG		 808 {
809 if (verbose > 0) {
810 int flags;
811 int i;
9943d318 812
df1756f4
TG		 813 sim_cb_eprintf (callback, "R00-07:");
814 for (i = 0; i < 8; i++)
815 sim_cb_eprintf (callback, " %02x", sram[i]);
816 sim_cb_eprintf (callback, " -");
817 for (i = 8; i < 16; i++)
818 sim_cb_eprintf (callback, " %02x", sram[i]);
819 sim_cb_eprintf (callback, " SP: %02x %02x",
820 sram[REG_SP + 1], sram[REG_SP]);
821 sim_cb_eprintf (callback, "\n");
822 sim_cb_eprintf (callback, "R16-31:");
823 for (i = 16; i < 24; i++)
824 sim_cb_eprintf (callback, " %02x", sram[i]);
825 sim_cb_eprintf (callback, " -");
826 for (i = 24; i < 32; i++)
827 sim_cb_eprintf (callback, " %02x", sram[i]);
828 sim_cb_eprintf (callback, " ");
829 flags = sram[SREG];
830 for (i = 0; i < 8; i++)
831 sim_cb_eprintf (callback, "%c",
832 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
833 sim_cb_eprintf (callback, "\n");
834 }
835
9943d318 836 if (!tracing)
f246dc72 837 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * avr_cpu->pc, flash[avr_cpu->pc].op);
df1756f4
TG		 838 else
839 {
840 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
f246dc72
MF		 841 2 * avr_cpu->pc, flash[avr_cpu->pc].op, code, flash[avr_cpu->pc].r);
842 disassemble_insn (CPU_STATE (cpu), avr_cpu->pc);
df1756f4
TG		 843 sim_cb_eprintf (callback, "\n");
844 }
845 }
9943d318 846#endif
df1756f4 847
f246dc72
MF		 848 ipc = avr_cpu->pc;
849 avr_cpu->pc = (avr_cpu->pc + 1) & PC_MASK;
850 avr_cpu->cycles++;
df1756f4 851
9943d318
MF		 852 switch (code)
853 {
854 case OP_unknown:
855 flash[ipc].code = decode(ipc);
f246dc72
MF		 856 avr_cpu->pc = ipc;
857 avr_cpu->cycles--;
9943d318
MF		 858 goto again;
859
860 case OP_nop:
861 break;
862
863 case OP_jmp:
864 /* 2 words instruction, but we don't care about the pc. */
f246dc72
MF		 865 avr_cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
866 avr_cpu->cycles += 2;
9943d318
MF		 867 break;
868
869 case OP_eijmp:
f246dc72
MF		 870 avr_cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
871 avr_cpu->cycles += 2;
9943d318
MF		 872 break;
873
874 case OP_ijmp:
f246dc72
MF		 875 avr_cpu->pc = read_word (REGZ) & PC_MASK;
876 avr_cpu->cycles += 1;
9943d318
MF		 877 break;
878
879 case OP_call:
880 /* 2 words instruction. */
f246dc72 881 avr_cpu->pc++;
82d442c6 882 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op);
9943d318
MF		 883 break;
884
885 case OP_eicall:
82d442c6 886 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ));
9943d318
MF		 887 break;
888
889 case OP_icall:
82d442c6 890 do_call (cpu, read_word (REGZ));
9943d318
MF		 891 break;
892
893 case OP_rcall:
f246dc72 894 do_call (cpu, avr_cpu->pc + sign_ext (op & 0xfff, 12));
9943d318
MF		 895 break;
896
897 case OP_reti:
898 sram[SREG] |= SREG_I;
639bab3c 899 ATTRIBUTE_FALLTHROUGH;
9943d318 900 case OP_ret:
df1756f4 901 {
937af0fd 902 const struct avr_sim_state *state = AVR_SIM_STATE (CPU_STATE (cpu));
9943d318 903 unsigned int sp = read_word (REG_SP);
937af0fd 904 if (state->avr_pc22)
9943d318 905 {
f246dc72
MF		 906 avr_cpu->pc = sram[++sp] << 16;
907 avr_cpu->cycles++;
9943d318 908 }
df1756f4 909 else
f246dc72
MF		 910 avr_cpu->pc = 0;
911 avr_cpu->pc |= sram[++sp] << 8;
912 avr_cpu->pc |= sram[++sp];
9943d318
MF		 913 write_word (REG_SP, sp);
914 }
f246dc72 915 avr_cpu->cycles += 3;
9943d318
MF		 916 break;
917
918 case OP_break:
919 /* Stop on this address. */
59f48f5a 920 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, ipc, sim_stopped, SIM_SIGTRAP);
9943d318
MF		 921 break;
922
923 case OP_bld:
924 d = get_d (op);
925 r = flash[ipc].r;
926 if (sram[SREG] & SREG_T)
927 sram[d] |= r;
928 else
929 sram[d] &= ~r;
930 break;
931
932 case OP_bst:
933 if (sram[get_d (op)] & flash[ipc].r)
934 sram[SREG] |= SREG_T;
935 else
936 sram[SREG] &= ~SREG_T;
937 break;
938
939 case OP_sbrc:
940 case OP_sbrs:
941 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
df1756f4 942 {
f246dc72
MF		 943 int l = get_insn_length (avr_cpu->pc);
944 avr_cpu->pc += l;
945 avr_cpu->cycles += l;
df1756f4 946 }
9943d318 947 break;
df1756f4 948
9943d318
MF		 949 case OP_push:
950 {
951 unsigned int sp = read_word (REG_SP);
952 sram[sp--] = sram[get_d (op)];
953 write_word (REG_SP, sp);
954 }
f246dc72 955 avr_cpu->cycles++;
9943d318 956 break;
df1756f4 957
9943d318
MF		 958 case OP_pop:
959 {
960 unsigned int sp = read_word (REG_SP);
961 sram[get_d (op)] = sram[++sp];
962 write_word (REG_SP, sp);
963 }
f246dc72 964 avr_cpu->cycles++;
9943d318
MF		 965 break;
966
967 case OP_bclr:
968 sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
969 break;
970
971 case OP_bset:
972 sram[SREG] |= 1 << ((op >> 4) & 0x7);
973 break;
974
975 case OP_rjmp:
f246dc72
MF		 976 avr_cpu->pc = (avr_cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
977 avr_cpu->cycles++;
9943d318
MF		 978 break;
979
980 case OP_eor:
981 d = get_d (op);
982 res = sram[d] ^ sram[get_r (op)];
983 sram[d] = res;
984 update_flags_logic (res);
985 break;
986
987 case OP_and:
988 d = get_d (op);
989 res = sram[d] & sram[get_r (op)];
990 sram[d] = res;
991 update_flags_logic (res);
992 break;
993
994 case OP_andi:
995 d = get_d16 (op);
996 res = sram[d] & get_K (op);
997 sram[d] = res;
998 update_flags_logic (res);
999 break;
1000
1001 case OP_or:
1002 d = get_d (op);
1003 res = sram[d] | sram[get_r (op)];
1004 sram[d] = res;
1005 update_flags_logic (res);
1006 break;
1007
1008 case OP_ori:
1009 d = get_d16 (op);
1010 res = sram[d] | get_K (op);
1011 sram[d] = res;
1012 update_flags_logic (res);
1013 break;
1014
1015 case OP_com:
1016 d = get_d (op);
1017 res = ~sram[d];
1018 sram[d] = res;
1019 update_flags_logic (res);
1020 sram[SREG] |= SREG_C;
1021 break;
1022
1023 case OP_swap:
1024 d = get_d (op);
1025 vd = sram[d];
1026 sram[d] = (vd >> 4) | (vd << 4);
1027 break;
1028
1029 case OP_neg:
1030 d = get_d (op);
1031 vd = sram[d];
1032 res = -vd;
1033 sram[d] = res;
1034 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1035 if (res == 0)
1036 sram[SREG] |= SREG_Z;
1037 else
df1756f4 1038 sram[SREG] |= SREG_C;
9943d318
MF		 1039 if (res == 0x80)
1040 sram[SREG] |= SREG_V | SREG_N;
1041 else if (res & 0x80)
1042 sram[SREG] |= SREG_N | SREG_S;
1043 if ((res | vd) & 0x08)
1044 sram[SREG] |= SREG_H;
1045 break;
1046
1047 case OP_inc:
1048 d = get_d (op);
1049 res = sram[d] + 1;
1050 sram[d] = res;
1051 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1052 if (res == 0x80)
1053 sram[SREG] |= SREG_V | SREG_N;
1054 else if (res & 0x80)
1055 sram[SREG] |= SREG_N | SREG_S;
1056 else if (res == 0)
1057 sram[SREG] |= SREG_Z;
1058 break;
1059
1060 case OP_dec:
1061 d = get_d (op);
1062 res = sram[d] - 1;
1063 sram[d] = res;
1064 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1065 if (res == 0x7f)
1066 sram[SREG] |= SREG_V | SREG_S;
1067 else if (res & 0x80)
1068 sram[SREG] |= SREG_N | SREG_S;
1069 else if (res == 0)
1070 sram[SREG] |= SREG_Z;
1071 break;
1072
1073 case OP_lsr:
1074 case OP_asr:
1075 d = get_d (op);
1076 vd = sram[d];
1077 res = (vd >> 1) | (vd & flash[ipc].r);
1078 sram[d] = res;
1079 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1080 if (vd & 1)
1081 sram[SREG] |= SREG_C | SREG_S;
1082 if (res & 0x80)
1083 sram[SREG] |= SREG_N;
1084 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1085 sram[SREG] |= SREG_V;
1086 if (res == 0)
1087 sram[SREG] |= SREG_Z;
1088 break;
1089
1090 case OP_ror:
1091 d = get_d (op);
1092 vd = sram[d];
1093 res = vd >> 1 | (sram[SREG] << 7);
1094 sram[d] = res;
1095 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1096 if (vd & 1)
1097 sram[SREG] |= SREG_C | SREG_S;
1098 if (res & 0x80)
1099 sram[SREG] |= SREG_N;
1100 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1101 sram[SREG] |= SREG_V;
1102 if (res == 0)
1103 sram[SREG] |= SREG_Z;
1104 break;
1105
1106 case OP_mul:
82d442c6 1107 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]);
9943d318
MF		 1108 break;
1109
1110 case OP_muls:
82d442c6
MF		 1111 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)]
1112 * (sword)(sbyte)sram[get_d16 (op)]);
9943d318
MF		 1113 break;
1114
1115 case OP_mulsu:
82d442c6
MF		 1116 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)]
1117 * (sword)(sbyte)sram[get_d16_23 (op)]);
9943d318
MF		 1118 break;
1119
1120 case OP_fmul:
82d442c6
MF		 1121 gen_mul (cpu, ((word)sram[get_r16_23 (op)]
1122 * (word)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1123 break;
1124
1125 case OP_fmuls:
82d442c6
MF		 1126 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)]
1127 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1128 break;
1129
1130 case OP_fmulsu:
82d442c6
MF		 1131 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)]
1132 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1133 break;
1134
1135 case OP_adc:
1136 case OP_add:
1137 r = sram[get_r (op)];
1138 d = get_d (op);
1139 vd = sram[d];
1140 res = r + vd + (sram[SREG] & flash[ipc].r);
1141 sram[d] = res;
1142 update_flags_add (res, vd, r);
1143 break;
1144
1145 case OP_sub:
1146 d = get_d (op);
1147 vd = sram[d];
1148 r = sram[get_r (op)];
1149 res = vd - r;
1150 sram[d] = res;
1151 update_flags_sub (res, vd, r);
1152 if (res == 0)
1153 sram[SREG] |= SREG_Z;
1154 break;
1155
1156 case OP_sbc:
1157 {
1158 byte old = sram[SREG];
df1756f4
TG		 1159 d = get_d (op);
1160 vd = sram[d];
1161 r = sram[get_r (op)];
9943d318 1162 res = vd - r - (old & SREG_C);
df1756f4
TG		 1163 sram[d] = res;
1164 update_flags_sub (res, vd, r);
9943d318 1165 if (res == 0 && (old & SREG_Z))
df1756f4 1166 sram[SREG] |= SREG_Z;
9943d318
MF		 1167 }
1168 break;
1169
1170 case OP_subi:
1171 d = get_d16 (op);
1172 vd = sram[d];
1173 r = get_K (op);
1174 res = vd - r;
1175 sram[d] = res;
1176 update_flags_sub (res, vd, r);
1177 if (res == 0)
1178 sram[SREG] |= SREG_Z;
1179 break;
1180
1181 case OP_sbci:
1182 {
1183 byte old = sram[SREG];
df1756f4 1184
df1756f4
TG		 1185 d = get_d16 (op);
1186 vd = sram[d];
1187 r = get_K (op);
9943d318 1188 res = vd - r - (old & SREG_C);
df1756f4
TG		 1189 sram[d] = res;
1190 update_flags_sub (res, vd, r);
9943d318 1191 if (res == 0 && (old & SREG_Z))
df1756f4 1192 sram[SREG] |= SREG_Z;
9943d318
MF		 1193 }
1194 break;
1195
1196 case OP_mov:
1197 sram[get_d (op)] = sram[get_r (op)];
1198 break;
1199
1200 case OP_movw:
1201 d = (op & 0xf0) >> 3;
1202 r = (op & 0x0f) << 1;
1203 sram[d] = sram[r];
1204 sram[d + 1] = sram[r + 1];
1205 break;
1206
1207 case OP_out:
1208 d = get_A (op) + 0x20;
1209 res = sram[get_d (op)];
1210 sram[d] = res;
1211 if (d == STDIO_PORT)
1212 putchar (res);
1213 else if (d == EXIT_PORT)
f246dc72 1214 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_exited, 0);
9943d318 1215 else if (d == ABORT_PORT)
f246dc72 1216 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_exited, 1);
9943d318
MF		 1217 break;
1218
1219 case OP_in:
1220 d = get_A (op) + 0x20;
1221 sram[get_d (op)] = sram[d];
1222 break;
1223
1224 case OP_cbi:
1225 d = get_biA (op) + 0x20;
1226 sram[d] &= ~(1 << get_b(op));
1227 break;
1228
1229 case OP_sbi:
1230 d = get_biA (op) + 0x20;
1231 sram[d] |= 1 << get_b(op);
1232 break;
1233
1234 case OP_sbic:
1235 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
df1756f4 1236 {
f246dc72
MF		 1237 int l = get_insn_length (avr_cpu->pc);
1238 avr_cpu->pc += l;
1239 avr_cpu->cycles += l;
df1756f4 1240 }
9943d318 1241 break;
df1756f4 1242
9943d318
MF		 1243 case OP_sbis:
1244 if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1245 {
f246dc72
MF		 1246 int l = get_insn_length (avr_cpu->pc);
1247 avr_cpu->pc += l;
1248 avr_cpu->cycles += l;
9943d318
MF		 1249 }
1250 break;
1251
1252 case OP_ldi:
1253 res = get_K (op);
1254 d = get_d16 (op);
1255 sram[d] = res;
1256 break;
1257
1258 case OP_lds:
f246dc72
MF		 1259 sram[get_d (op)] = sram[flash[avr_cpu->pc].op];
1260 avr_cpu->pc++;
1261 avr_cpu->cycles++;
9943d318
MF		 1262 break;
1263
1264 case OP_sts:
f246dc72
MF		 1265 sram[flash[avr_cpu->pc].op] = sram[get_d (op)];
1266 avr_cpu->pc++;
1267 avr_cpu->cycles++;
9943d318
MF		 1268 break;
1269
1270 case OP_cpse:
1271 if (sram[get_r (op)] == sram[get_d (op)])
1272 {
f246dc72
MF		 1273 int l = get_insn_length (avr_cpu->pc);
1274 avr_cpu->pc += l;
1275 avr_cpu->cycles += l;
9943d318
MF		 1276 }
1277 break;
1278
1279 case OP_cp:
1280 r = sram[get_r (op)];
1281 d = sram[get_d (op)];
1282 res = d - r;
1283 update_flags_sub (res, d, r);
1284 if (res == 0)
1285 sram[SREG] |= SREG_Z;
1286 break;
1287
1288 case OP_cpi:
1289 r = get_K (op);
1290 d = sram[get_d16 (op)];
1291 res = d - r;
1292 update_flags_sub (res, d, r);
1293 if (res == 0)
1294 sram[SREG] |= SREG_Z;
1295 break;
1296
1297 case OP_cpc:
1298 {
1299 byte old = sram[SREG];
df1756f4 1300 d = sram[get_d (op)];
9943d318
MF		 1301 r = sram[get_r (op)];
1302 res = d - r - (old & SREG_C);
df1756f4 1303 update_flags_sub (res, d, r);
9943d318 1304 if (res == 0 && (old & SREG_Z))
df1756f4 1305 sram[SREG] |= SREG_Z;
9943d318
MF		 1306 }
1307 break;
df1756f4 1308
9943d318
MF		 1309 case OP_brbc:
1310 if (!(sram[SREG] & flash[ipc].r))
1311 {
f246dc72
MF		 1312 avr_cpu->pc = (avr_cpu->pc + get_k (op)) & PC_MASK;
1313 avr_cpu->cycles++;
9943d318
MF		 1314 }
1315 break;
df1756f4 1316
9943d318
MF		 1317 case OP_brbs:
1318 if (sram[SREG] & flash[ipc].r)
df1756f4 1319 {
f246dc72
MF		 1320 avr_cpu->pc = (avr_cpu->pc + get_k (op)) & PC_MASK;
1321 avr_cpu->cycles++;
df1756f4 1322 }
9943d318
MF		 1323 break;
1324
1325 case OP_lpm:
1326 sram[0] = get_lpm (read_word (REGZ));
f246dc72 1327 avr_cpu->cycles += 2;
9943d318
MF		 1328 break;
1329
1330 case OP_lpm_Z:
1331 sram[get_d (op)] = get_lpm (read_word (REGZ));
f246dc72 1332 avr_cpu->cycles += 2;
9943d318
MF		 1333 break;
1334
1335 case OP_lpm_inc_Z:
1336 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
f246dc72 1337 avr_cpu->cycles += 2;
9943d318
MF		 1338 break;
1339
1340 case OP_elpm:
1341 sram[0] = get_lpm (get_z ());
f246dc72 1342 avr_cpu->cycles += 2;
9943d318
MF		 1343 break;
1344
1345 case OP_elpm_Z:
1346 sram[get_d (op)] = get_lpm (get_z ());
f246dc72 1347 avr_cpu->cycles += 2;
9943d318
MF		 1348 break;
1349
1350 case OP_elpm_inc_Z:
1351 {
1352 unsigned int z = get_z ();
df1756f4 1353
9943d318
MF		 1354 sram[get_d (op)] = get_lpm (z);
1355 z++;
1356 sram[REGZ_LO] = z;
1357 sram[REGZ_HI] = z >> 8;
1358 sram[RAMPZ] = z >> 16;
1359 }
f246dc72 1360 avr_cpu->cycles += 2;
9943d318
MF		 1361 break;
1362
1363 case OP_ld_Z_inc:
1364 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
f246dc72 1365 avr_cpu->cycles++;
9943d318
MF		 1366 break;
1367
1368 case OP_ld_dec_Z:
1369 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
f246dc72 1370 avr_cpu->cycles++;
9943d318
MF		 1371 break;
1372
1373 case OP_ld_X_inc:
1374 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
f246dc72 1375 avr_cpu->cycles++;
9943d318
MF		 1376 break;
1377
1378 case OP_ld_dec_X:
1379 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
f246dc72 1380 avr_cpu->cycles++;
9943d318
MF		 1381 break;
1382
1383 case OP_ld_Y_inc:
1384 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
f246dc72 1385 avr_cpu->cycles++;
9943d318
MF		 1386 break;
1387
1388 case OP_ld_dec_Y:
1389 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
f246dc72 1390 avr_cpu->cycles++;
9943d318
MF		 1391 break;
1392
1393 case OP_st_X:
1394 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1395 avr_cpu->cycles++;
9943d318
MF		 1396 break;
1397
1398 case OP_st_X_inc:
1399 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1400 avr_cpu->cycles++;
9943d318
MF		 1401 break;
1402
1403 case OP_st_dec_X:
1404 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1405 avr_cpu->cycles++;
9943d318
MF		 1406 break;
1407
1408 case OP_st_Z_inc:
1409 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1410 avr_cpu->cycles++;
9943d318
MF		 1411 break;
1412
1413 case OP_st_dec_Z:
1414 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1415 avr_cpu->cycles++;
9943d318
MF		 1416 break;
1417
1418 case OP_st_Y_inc:
1419 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1420 avr_cpu->cycles++;
9943d318
MF		 1421 break;
1422
1423 case OP_st_dec_Y:
1424 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
f246dc72 1425 avr_cpu->cycles++;
9943d318
MF		 1426 break;
1427
1428 case OP_std_Y:
1429 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
f246dc72 1430 avr_cpu->cycles++;
9943d318
MF		 1431 break;
1432
1433 case OP_std_Z:
1434 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
f246dc72 1435 avr_cpu->cycles++;
9943d318
MF		 1436 break;
1437
1438 case OP_ldd_Z:
1439 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
f246dc72 1440 avr_cpu->cycles++;
9943d318
MF		 1441 break;
1442
1443 case OP_ldd_Y:
1444 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
f246dc72 1445 avr_cpu->cycles++;
9943d318
MF		 1446 break;
1447
1448 case OP_ld_X:
1449 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
f246dc72 1450 avr_cpu->cycles++;
9943d318
MF		 1451 break;
1452
1453 case OP_sbiw:
1454 {
1455 word wk = get_k6 (op);
1456 word wres;
1457 word wr;
df1756f4 1458
9943d318
MF		 1459 d = get_d24 (op);
1460 wr = read_word (d);
1461 wres = wr - wk;
df1756f4 1462
9943d318
MF		 1463 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1464 if (wres == 0)
1465 sram[SREG] |= SREG_Z;
1466 if (wres & 0x8000)
1467 sram[SREG] |= SREG_N;
1468 if (wres & ~wr & 0x8000)
1469 sram[SREG] |= SREG_C;
1470 if (~wres & wr & 0x8000)
1471 sram[SREG] |= SREG_V;
1472 if (((~wres & wr) ^ wres) & 0x8000)
1473 sram[SREG] |= SREG_S;
1474 write_word (d, wres);
1475 }
f246dc72 1476 avr_cpu->cycles++;
9943d318 1477 break;
df1756f4 1478
9943d318
MF		 1479 case OP_adiw:
1480 {
1481 word wk = get_k6 (op);
1482 word wres;
1483 word wr;
1484
1485 d = get_d24 (op);
1486 wr = read_word (d);
1487 wres = wr + wk;
1488
1489 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1490 if (wres == 0)
1491 sram[SREG] |= SREG_Z;
1492 if (wres & 0x8000)
1493 sram[SREG] |= SREG_N;
1494 if (~wres & wr & 0x8000)
1495 sram[SREG] |= SREG_C;
1496 if (wres & ~wr & 0x8000)
1497 sram[SREG] |= SREG_V;
1498 if (((wres & ~wr) ^ wres) & 0x8000)
1499 sram[SREG] |= SREG_S;
1500 write_word (d, wres);
df1756f4 1501 }
f246dc72 1502 avr_cpu->cycles++;
9943d318 1503 break;
df1756f4 1504
9943d318 1505 case OP_bad:
f246dc72 1506 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_signalled, SIM_SIGILL);
df1756f4 1507
9943d318 1508 default:
f246dc72 1509 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, avr_cpu->pc, sim_signalled, SIM_SIGILL);
9943d318
MF		 1510 }
1511}
1512
1513void
1514sim_engine_run (SIM_DESC sd,
1515 int next_cpu_nr, /* ignore */
1516 int nr_cpus, /* ignore */
1517 int siggnal) /* ignore */
df1756f4 1518{
9943d318
MF		 1519 SIM_CPU *cpu;
1520
1521 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1522
1523 cpu = STATE_CPU (sd, 0);
df1756f4 1524
9943d318
MF		 1525 while (1)
1526 {
1527 step_once (cpu);
1528 if (sim_events_tick (sd))
1529 sim_events_process (sd);
1530 }
df1756f4
TG		 1531}
1532
63fd5b5d
MF		 1533uint64_t
1534sim_write (SIM_DESC sd, uint64_t addr, const void *buffer, uint64_t size)
df1756f4
TG		 1535{
1536 int osize = size;
1537
1538 if (addr >= 0 && addr < SRAM_VADDR)
1539 {
5b94c380 1540 const unsigned char *data = buffer;
8f0ac700 1541 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1542 {
8f0ac700
TG		 1543 word val = flash[addr >> 1].op;
1544
1545 if (addr & 1)
5b94c380 1546 val = (val & 0xff) | (data[0] << 8);
8f0ac700 1547 else
5b94c380 1548 val = (val & 0xff00) | data[0];
8f0ac700
TG		 1549
1550 flash[addr >> 1].op = val;
1551 flash[addr >> 1].code = OP_unknown;
df1756f4 1552 addr++;
5b94c380 1553 data++;
8f0ac700 1554 size--;
df1756f4
TG		 1555 }
1556 return osize - size;
1557 }
1558 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1559 {
1560 addr -= SRAM_VADDR;
1561 if (addr + size > MAX_AVR_SRAM)
1562 size = MAX_AVR_SRAM - addr;
1563 memcpy (sram + addr, buffer, size);
1564 return size;
1565 }
1566 else
1567 return 0;
1568}
1569
63fd5b5d
MF		 1570uint64_t
1571sim_read (SIM_DESC sd, uint64_t addr, void *buffer, uint64_t size)
df1756f4
TG		 1572{
1573 int osize = size;
1574
1575 if (addr >= 0 && addr < SRAM_VADDR)
1576 {
5b94c380 1577 unsigned char *data = buffer;
8f0ac700 1578 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1579 {
8f0ac700
TG		 1580 word val = flash[addr >> 1].op;
1581
1582 if (addr & 1)
1583 val >>= 8;
1584
5b94c380 1585 *data++ = val;
df1756f4 1586 addr++;
8f0ac700 1587 size--;
df1756f4
TG		 1588 }
1589 return osize - size;
1590 }
1591 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1592 {
1593 addr -= SRAM_VADDR;
1594 if (addr + size > MAX_AVR_SRAM)
1595 size = MAX_AVR_SRAM - addr;
1596 memcpy (buffer, sram + addr, size);
1597 return size;
1598 }
1599 else
1600 {
1601 /* Avoid errors. */
1602 memset (buffer, 0, size);
1603 return size;
1604 }
1605}
1606
807eaf04 1607static int
ee1cffd3 1608avr_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length)
df1756f4 1609{
f246dc72 1610 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu);
ee1cffd3
MF		 1611 const unsigned char *memory = buf;
1612
df1756f4
TG		 1613 if (rn < 32 && length == 1)
1614 {
1615 sram[rn] = *memory;
1616 return 1;
1617 }
1618 if (rn == AVR_SREG_REGNUM && length == 1)
1619 {
1620 sram[SREG] = *memory;
1621 return 1;
1622 }
1623 if (rn == AVR_SP_REGNUM && length == 2)
1624 {
1625 sram[REG_SP] = memory[0];
1626 sram[REG_SP + 1] = memory[1];
1627 return 2;
1628 }
1629 if (rn == AVR_PC_REGNUM && length == 4)
1630 {
f246dc72 1631 avr_cpu->pc = (memory[0] >> 1) | (memory[1] << 7)
82d442c6 1632 | (memory[2] << 15) | (memory[3] << 23);
f246dc72 1633 avr_cpu->pc &= PC_MASK;
df1756f4
TG		 1634 return 4;
1635 }
1636 return 0;
1637}
1638
807eaf04 1639static int
ee1cffd3 1640avr_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length)
df1756f4 1641{
f246dc72 1642 struct avr_sim_cpu *avr_cpu = AVR_SIM_CPU (cpu);
ee1cffd3
MF		 1643 unsigned char *memory = buf;
1644
df1756f4
TG		 1645 if (rn < 32 && length == 1)
1646 {
1647 *memory = sram[rn];
1648 return 1;
1649 }
1650 if (rn == AVR_SREG_REGNUM && length == 1)
1651 {
1652 *memory = sram[SREG];
1653 return 1;
1654 }
1655 if (rn == AVR_SP_REGNUM && length == 2)
1656 {
1657 memory[0] = sram[REG_SP];
1658 memory[1] = sram[REG_SP + 1];
1659 return 2;
1660 }
1661 if (rn == AVR_PC_REGNUM && length == 4)
1662 {
f246dc72
MF		 1663 memory[0] = avr_cpu->pc << 1;
1664 memory[1] = avr_cpu->pc >> 7;
1665 memory[2] = avr_cpu->pc >> 15;
1666 memory[3] = avr_cpu->pc >> 23;
df1756f4
TG		 1667 return 4;
1668 }
1669 return 0;
1670}
1671
4c0cab1e
MF		 1672static sim_cia
1673avr_pc_get (sim_cpu *cpu)
1674{
f246dc72 1675 return AVR_SIM_CPU (cpu)->pc;
4c0cab1e
MF		 1676}
1677
1678static void
82d442c6 1679avr_pc_set (sim_cpu *cpu, sim_cia pc)
4c0cab1e 1680{
f246dc72 1681 AVR_SIM_CPU (cpu)->pc = pc;
4c0cab1e
MF		 1682}
1683
9943d318
MF		 1684static void
1685free_state (SIM_DESC sd)
df1756f4 1686{
9943d318
MF		 1687 if (STATE_MODULES (sd) != NULL)
1688 sim_module_uninstall (sd);
1689 sim_cpu_free_all (sd);
1690 sim_state_free (sd);
df1756f4
TG		 1691}
1692
1693SIM_DESC
2e3d4f4d
MF		 1694sim_open (SIM_OPEN_KIND kind, host_callback *cb,
1695 struct bfd *abfd, char * const *argv)
df1756f4 1696{
4c0cab1e 1697 int i;
937af0fd 1698 SIM_DESC sd = sim_state_alloc_extra (kind, cb, sizeof (struct avr_sim_state));
9943d318 1699 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
df1756f4 1700
ba307cdd
MF		 1701 /* Set default options before parsing user options. */
1702 current_alignment = STRICT_ALIGNMENT;
f9a4d543 1703 current_target_byte_order = BFD_ENDIAN_LITTLE;
ba307cdd 1704
9943d318 1705 /* The cpu data is kept in a separately allocated chunk of memory. */
883be197 1706 if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct avr_sim_cpu))
f246dc72 1707 != SIM_RC_OK)
9943d318
MF		 1708 {
1709 free_state (sd);
1710 return 0;
1711 }
df1756f4 1712
9943d318
MF		 1713 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1714 {
1715 free_state (sd);
1716 return 0;
1717 }
df1756f4 1718
77cf2ef5 1719 /* The parser will print an error message for us, so we silently return. */
9943d318
MF		 1720 if (sim_parse_args (sd, argv) != SIM_RC_OK)
1721 {
1722 free_state (sd);
1723 return 0;
1724 }
33bcfade 1725
9943d318 1726 /* Check for/establish the a reference program image. */
e8f20a28 1727 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
9943d318
MF		 1728 {
1729 free_state (sd);
1730 return 0;
1731 }
df1756f4 1732
9943d318
MF		 1733 /* Configure/verify the target byte order and other runtime
1734 configuration options. */
1735 if (sim_config (sd) != SIM_RC_OK)
1736 {
1737 sim_module_uninstall (sd);
1738 return 0;
1739 }
df1756f4 1740
9943d318
MF		 1741 if (sim_post_argv_init (sd) != SIM_RC_OK)
1742 {
1743 /* Uninstall the modules to avoid memory leaks,
1744 file descriptor leaks, etc. */
1745 sim_module_uninstall (sd);
1746 return 0;
1747 }
df1756f4 1748
4c0cab1e
MF		 1749 /* CPU specific initialization. */
1750 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1751 {
1752 SIM_CPU *cpu = STATE_CPU (sd, i);
1753
807eaf04
MF		 1754 CPU_REG_FETCH (cpu) = avr_reg_fetch;
1755 CPU_REG_STORE (cpu) = avr_reg_store;
4c0cab1e
MF		 1756 CPU_PC_FETCH (cpu) = avr_pc_get;
1757 CPU_PC_STORE (cpu) = avr_pc_set;
1758 }
1759
9943d318
MF		 1760 /* Clear all the memory. */
1761 memset (sram, 0, sizeof (sram));
1762 memset (flash, 0, sizeof (flash));
df1756f4 1763
9943d318 1764 return sd;
df1756f4
TG		 1765}
1766
9943d318 1767SIM_RC
2e3d4f4d
MF		 1768sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
1769 char * const *argv, char * const *env)
df1756f4 1770{
937af0fd 1771 struct avr_sim_state *state = AVR_SIM_STATE (sd);
82d442c6 1772 SIM_CPU *cpu = STATE_CPU (sd, 0);
20fea663 1773 bfd_vma addr;
82d442c6 1774
9943d318
MF		 1775 /* Set the PC. */
1776 if (abfd != NULL)
82d442c6 1777 addr = bfd_get_start_address (abfd);
9943d318 1778 else
82d442c6
MF		 1779 addr = 0;
1780 sim_pc_set (cpu, addr);
af9f7da7 1781
9943d318 1782 if (abfd != NULL)
937af0fd 1783 state->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6);
9943d318
MF		 1784
1785 return SIM_RC_OK;
af9f7da7 1786}
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