]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/avr/interp.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: create header namespace
[thirdparty/binutils-gdb.git] / sim / avr / interp.c
CommitLineData
df1756f4 1/* Simulator for Atmel's AVR core.
3666a048 2 Copyright (C) 2009-2021 Free Software Foundation, Inc.
df1756f4
TG		 3 Written by Tristan Gingold, AdaCore.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "config.h"
21
df1756f4 22#include <string.h>
68ed2854 23
df1756f4 24#include "bfd.h"
df1756f4 25#include "libiberty.h"
df68e12b 26#include "sim/sim.h"
9943d318
MF		 27
28#include "sim-main.h"
29#include "sim-base.h"
30#include "sim-options.h"
df1756f4
TG		 31
32/* As AVR is a 8/16 bits processor, define handy types. */
33typedef unsigned short int word;
34typedef signed short int sword;
35typedef unsigned char byte;
36typedef signed char sbyte;
37
df1756f4
TG		 38/* Max size of I space (which is always flash on avr). */
39#define MAX_AVR_FLASH (128 * 1024)
40#define PC_MASK (MAX_AVR_FLASH - 1)
41
42/* Mac size of D space. */
43#define MAX_AVR_SRAM (64 * 1024)
44#define SRAM_MASK (MAX_AVR_SRAM - 1)
45
46/* D space offset in ELF file. */
47#define SRAM_VADDR 0x800000
48
49/* Simulator specific ports. */
50#define STDIO_PORT 0x52
51#define EXIT_PORT 0x4F
52#define ABORT_PORT 0x49
53
54/* GDB defined register numbers. */
55#define AVR_SREG_REGNUM 32
56#define AVR_SP_REGNUM 33
57#define AVR_PC_REGNUM 34
58
59/* Memory mapped registers. */
60#define SREG 0x5F
61#define REG_SP 0x5D
62#define EIND 0x5C
63#define RAMPZ 0x5B
64
65#define REGX 0x1a
66#define REGY 0x1c
67#define REGZ 0x1e
68#define REGZ_LO 0x1e
69#define REGZ_HI 0x1f
70
71/* Sreg (status) bits. */
72#define SREG_I 0x80
73#define SREG_T 0x40
74#define SREG_H 0x20
75#define SREG_S 0x10
76#define SREG_V 0x08
77#define SREG_N 0x04
78#define SREG_Z 0x02
79#define SREG_C 0x01
80
81/* In order to speed up emulation we use a simple approach:
82 a code is associated with each instruction. The pre-decoding occurs
83 usually once when the instruction is first seen.
84 This works well because I&D spaces are separated.
85
86 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
87*/
88enum avr_opcode
89 {
90 /* Opcode not yet decoded. */
91 OP_unknown,
92 OP_bad,
93
94 OP_nop,
95
96 OP_rjmp,
97 OP_rcall,
98 OP_ret,
99 OP_reti,
100
101 OP_break,
102
103 OP_brbs,
104 OP_brbc,
105
106 OP_bset,
107 OP_bclr,
108
109 OP_bld,
110 OP_bst,
111
112 OP_sbrc,
113 OP_sbrs,
114
115 OP_eor,
116 OP_and,
117 OP_andi,
118 OP_or,
119 OP_ori,
120 OP_com,
121 OP_swap,
122 OP_neg,
123
124 OP_out,
125 OP_in,
126 OP_cbi,
127 OP_sbi,
128
129 OP_sbic,
130 OP_sbis,
131
132 OP_ldi,
133 OP_cpse,
134 OP_cp,
135 OP_cpi,
136 OP_cpc,
137 OP_sub,
138 OP_sbc,
139 OP_sbiw,
140 OP_adiw,
141 OP_add,
142 OP_adc,
143 OP_subi,
144 OP_sbci,
145 OP_inc,
146 OP_dec,
147 OP_lsr,
148 OP_ror,
149 OP_asr,
150
151 OP_mul,
152 OP_muls,
153 OP_mulsu,
154 OP_fmul,
155 OP_fmuls,
156 OP_fmulsu,
157
158 OP_mov,
159 OP_movw,
160
161 OP_push,
162 OP_pop,
163
164 OP_st_X,
165 OP_st_dec_X,
166 OP_st_X_inc,
167 OP_st_Y_inc,
168 OP_st_dec_Y,
169 OP_st_Z_inc,
170 OP_st_dec_Z,
171 OP_std_Y,
172 OP_std_Z,
173 OP_ldd_Y,
174 OP_ldd_Z,
175 OP_ld_Z_inc,
176 OP_ld_dec_Z,
177 OP_ld_Y_inc,
178 OP_ld_dec_Y,
179 OP_ld_X,
180 OP_ld_X_inc,
181 OP_ld_dec_X,
182
183 OP_lpm,
184 OP_lpm_Z,
185 OP_lpm_inc_Z,
186 OP_elpm,
187 OP_elpm_Z,
188 OP_elpm_inc_Z,
189
190 OP_ijmp,
191 OP_icall,
192
193 OP_eijmp,
194 OP_eicall,
195
196 /* 2 words opcodes. */
197#define OP_2words OP_jmp
198 OP_jmp,
199 OP_call,
200 OP_sts,
201 OP_lds
202 };
203
204struct avr_insn_cell
205{
206 /* The insn (16 bits). */
207 word op;
208
209 /* Pre-decoding code. */
210 enum avr_opcode code : 8;
211 /* One byte of additional information. */
212 byte r;
213};
214
215/* I&D memories. */
9943d318 216/* TODO: Should be moved to SIM_CPU. */
df1756f4
TG		 217static struct avr_insn_cell flash[MAX_AVR_FLASH];
218static byte sram[MAX_AVR_SRAM];
219
df1756f4
TG		 220/* Sign extend a value. */
221static int sign_ext (word val, int nb_bits)
222{
223 if (val & (1 << (nb_bits - 1)))
1d19cae7 224 return val | -(1 << nb_bits);
df1756f4
TG		 225 return val;
226}
227
228/* Insn field extractors. */
229
230/* Extract xxxx_xxxRx_xxxx_RRRR. */
231static inline byte get_r (word op)
232{
233 return (op & 0xf) | ((op >> 5) & 0x10);
234}
235
236/* Extract xxxx_xxxxx_xxxx_RRRR. */
237static inline byte get_r16 (word op)
238{
239 return 16 + (op & 0xf);
240}
241
242/* Extract xxxx_xxxxx_xxxx_xRRR. */
243static inline byte get_r16_23 (word op)
244{
245 return 16 + (op & 0x7);
246}
247
248/* Extract xxxx_xxxD_DDDD_xxxx. */
249static inline byte get_d (word op)
250{
251 return (op >> 4) & 0x1f;
252}
253
254/* Extract xxxx_xxxx_DDDD_xxxx. */
255static inline byte get_d16 (word op)
256{
257 return 16 + ((op >> 4) & 0x0f);
258}
259
260/* Extract xxxx_xxxx_xDDD_xxxx. */
261static inline byte get_d16_23 (word op)
262{
263 return 16 + ((op >> 4) & 0x07);
264}
265
266/* Extract xxxx_xAAx_xxxx_AAAA. */
267static inline byte get_A (word op)
268{
269 return (op & 0x0f) | ((op & 0x600) >> 5);
270}
271
272/* Extract xxxx_xxxx_AAAA_Axxx. */
273static inline byte get_biA (word op)
274{
275 return (op >> 3) & 0x1f;
276}
277
278/* Extract xxxx_KKKK_xxxx_KKKK. */
279static inline byte get_K (word op)
280{
281 return (op & 0xf) | ((op & 0xf00) >> 4);
282}
283
284/* Extract xxxx_xxKK_KKKK_Kxxx. */
285static inline int get_k (word op)
286{
287 return sign_ext ((op & 0x3f8) >> 3, 7);
288}
289
290/* Extract xxxx_xxxx_xxDD_xxxx. */
291static inline byte get_d24 (word op)
292{
293 return 24 + ((op >> 3) & 6);
294}
295
296/* Extract xxxx_xxxx_KKxx_KKKK. */
297static inline byte get_k6 (word op)
298{
299 return (op & 0xf) | ((op >> 2) & 0x30);
300}
301
302/* Extract xxQx_QQxx_xxxx_xQQQ. */
303static inline byte get_q (word op)
304{
305 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
306}
307
308/* Extract xxxx_xxxx_xxxx_xBBB. */
309static inline byte get_b (word op)
310{
311 return (op & 7);
312}
313
314/* AVR is little endian. */
315static inline word
316read_word (unsigned int addr)
317{
318 return sram[addr] | (sram[addr + 1] << 8);
319}
320
321static inline void
322write_word (unsigned int addr, word w)
323{
324 sram[addr] = w;
325 sram[addr + 1] = w >> 8;
326}
327
328static inline word
329read_word_post_inc (unsigned int addr)
330{
331 word v = read_word (addr);
332 write_word (addr, v + 1);
333 return v;
334}
335
336static inline word
337read_word_pre_dec (unsigned int addr)
338{
339 word v = read_word (addr) - 1;
340 write_word (addr, v);
341 return v;
342}
343
344static void
345update_flags_logic (byte res)
346{
347 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
348 if (res == 0)
349 sram[SREG] |= SREG_Z;
350 if (res & 0x80)
351 sram[SREG] |= SREG_N | SREG_S;
352}
353
354static void
355update_flags_add (byte r, byte a, byte b)
356{
357 byte carry;
358
359 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
360 if (r & 0x80)
361 sram[SREG] |= SREG_N;
362 carry = (a & b) | (a & ~r) | (b & ~r);
363 if (carry & 0x08)
364 sram[SREG] |= SREG_H;
365 if (carry & 0x80)
366 sram[SREG] |= SREG_C;
367 if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
368 sram[SREG] |= SREG_V;
369 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
370 sram[SREG] |= SREG_S;
371 if (r == 0)
372 sram[SREG] |= SREG_Z;
373}
374
375static void update_flags_sub (byte r, byte a, byte b)
376{
377 byte carry;
378
379 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
380 if (r & 0x80)
381 sram[SREG] |= SREG_N;
382 carry = (~a & b) | (b & r) | (r & ~a);
383 if (carry & 0x08)
384 sram[SREG] |= SREG_H;
385 if (carry & 0x80)
386 sram[SREG] |= SREG_C;
387 if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
388 sram[SREG] |= SREG_V;
389 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
390 sram[SREG] |= SREG_S;
391 /* Note: Z is not set. */
392}
393
394static enum avr_opcode
395decode (unsigned int pc)
396{
397 word op1 = flash[pc].op;
398
399 switch ((op1 >> 12) & 0x0f)
400 {
401 case 0x0:
402 switch ((op1 >> 10) & 0x3)
403 {
404 case 0x0:
405 switch ((op1 >> 8) & 0x3)
406 {
407 case 0x0:
408 if (op1 == 0)
409 return OP_nop;
410 break;
411 case 0x1:
412 return OP_movw;
413 case 0x2:
414 return OP_muls;
415 case 0x3:
416 if (op1 & 0x80)
417 {
418 if (op1 & 0x08)
419 return OP_fmulsu;
420 else
421 return OP_fmuls;
422 }
423 else
424 {
425 if (op1 & 0x08)
426 return OP_fmul;
427 else
428 return OP_mulsu;
429 }
430 }
431 break;
432 case 0x1:
433 return OP_cpc;
434 case 0x2:
435 flash[pc].r = SREG_C;
436 return OP_sbc;
437 case 0x3:
438 flash[pc].r = 0;
439 return OP_add;
440 }
441 break;
442 case 0x1:
443 switch ((op1 >> 10) & 0x3)
444 {
445 case 0x0:
446 return OP_cpse;
447 case 0x1:
448 return OP_cp;
449 case 0x2:
450 flash[pc].r = 0;
451 return OP_sub;
452 case 0x3:
453 flash[pc].r = SREG_C;
454 return OP_adc;
455 }
456 break;
457 case 0x2:
458 switch ((op1 >> 10) & 0x3)
459 {
460 case 0x0:
461 return OP_and;
462 case 0x1:
463 return OP_eor;
464 case 0x2:
465 return OP_or;
466 case 0x3:
467 return OP_mov;
468 }
469 break;
470 case 0x3:
471 return OP_cpi;
472 case 0x4:
473 return OP_sbci;
474 case 0x5:
475 return OP_subi;
476 case 0x6:
477 return OP_ori;
478 case 0x7:
479 return OP_andi;
480 case 0x8:
481 case 0xa:
482 if (op1 & 0x0200)
483 {
484 if (op1 & 0x0008)
485 {
486 flash[pc].r = get_q (op1);
487 return OP_std_Y;
488 }
489 else
490 {
491 flash[pc].r = get_q (op1);
492 return OP_std_Z;
493 }
494 }
495 else
496 {
497 if (op1 & 0x0008)
498 {
499 flash[pc].r = get_q (op1);
500 return OP_ldd_Y;
501 }
502 else
503 {
504 flash[pc].r = get_q (op1);
505 return OP_ldd_Z;
506 }
507 }
508 break;
509 case 0x9: /* 9xxx */
510 switch ((op1 >> 8) & 0xf)
511 {
512 case 0x0:
513 case 0x1:
514 switch ((op1 >> 0) & 0xf)
515 {
516 case 0x0:
517 return OP_lds;
518 case 0x1:
519 return OP_ld_Z_inc;
520 case 0x2:
521 return OP_ld_dec_Z;
522 case 0x4:
523 return OP_lpm_Z;
524 case 0x5:
525 return OP_lpm_inc_Z;
526 case 0x6:
527 return OP_elpm_Z;
528 case 0x7:
529 return OP_elpm_inc_Z;
530 case 0x9:
531 return OP_ld_Y_inc;
532 case 0xa:
533 return OP_ld_dec_Y;
534 case 0xc:
535 return OP_ld_X;
536 case 0xd:
537 return OP_ld_X_inc;
538 case 0xe:
539 return OP_ld_dec_X;
540 case 0xf:
541 return OP_pop;
542 }
543 break;
544 case 0x2:
545 case 0x3:
546 switch ((op1 >> 0) & 0xf)
547 {
548 case 0x0:
549 return OP_sts;
550 case 0x1:
551 return OP_st_Z_inc;
552 case 0x2:
553 return OP_st_dec_Z;
554 case 0x9:
555 return OP_st_Y_inc;
556 case 0xa:
557 return OP_st_dec_Y;
558 case 0xc:
559 return OP_st_X;
560 case 0xd:
561 return OP_st_X_inc;
562 case 0xe:
563 return OP_st_dec_X;
564 case 0xf:
565 return OP_push;
566 }
567 break;
568 case 0x4:
569 case 0x5:
570 switch (op1 & 0xf)
571 {
572 case 0x0:
573 return OP_com;
574 case 0x1:
575 return OP_neg;
576 case 0x2:
577 return OP_swap;
578 case 0x3:
579 return OP_inc;
580 case 0x5:
581 flash[pc].r = 0x80;
582 return OP_asr;
583 case 0x6:
584 flash[pc].r = 0;
585 return OP_lsr;
586 case 0x7:
587 return OP_ror;
588 case 0x8: /* 9[45]x8 */
589 switch ((op1 >> 4) & 0x1f)
590 {
591 case 0x00:
592 case 0x01:
593 case 0x02:
594 case 0x03:
595 case 0x04:
596 case 0x05:
597 case 0x06:
598 case 0x07:
599 return OP_bset;
600 case 0x08:
601 case 0x09:
602 case 0x0a:
603 case 0x0b:
604 case 0x0c:
605 case 0x0d:
606 case 0x0e:
607 case 0x0f:
608 return OP_bclr;
609 case 0x10:
610 return OP_ret;
611 case 0x11:
612 return OP_reti;
613 case 0x19:
614 return OP_break;
615 case 0x1c:
616 return OP_lpm;
617 case 0x1d:
618 return OP_elpm;
619 default:
620 break;
621 }
622 break;
623 case 0x9: /* 9[45]x9 */
624 switch ((op1 >> 4) & 0x1f)
625 {
626 case 0x00:
627 return OP_ijmp;
628 case 0x01:
629 return OP_eijmp;
630 case 0x10:
631 return OP_icall;
632 case 0x11:
633 return OP_eicall;
634 default:
635 break;
636 }
637 break;
638 case 0xa:
639 return OP_dec;
640 case 0xc:
641 case 0xd:
642 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
643 return OP_jmp;
644 case 0xe:
645 case 0xf:
646 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
647 return OP_call;
648 }
649 break;
650 case 0x6:
651 return OP_adiw;
652 case 0x7:
653 return OP_sbiw;
654 case 0x8:
655 return OP_cbi;
656 case 0x9:
657 return OP_sbic;
658 case 0xa:
659 return OP_sbi;
660 case 0xb:
661 return OP_sbis;
662 case 0xc:
663 case 0xd:
664 case 0xe:
665 case 0xf:
666 return OP_mul;
667 }
668 break;
669 case 0xb:
670 flash[pc].r = get_A (op1);
671 if (((op1 >> 11) & 1) == 0)
672 return OP_in;
673 else
674 return OP_out;
675 case 0xc:
676 return OP_rjmp;
677 case 0xd:
678 return OP_rcall;
679 case 0xe:
680 return OP_ldi;
681 case 0xf:
682 switch ((op1 >> 9) & 7)
683 {
684 case 0:
685 case 1:
686 flash[pc].r = 1 << (op1 & 7);
687 return OP_brbs;
688 case 2:
689 case 3:
690 flash[pc].r = 1 << (op1 & 7);
691 return OP_brbc;
692 case 4:
693 if ((op1 & 8) == 0)
694 {
695 flash[pc].r = 1 << (op1 & 7);
696 return OP_bld;
697 }
698 break;
699 case 5:
700 if ((op1 & 8) == 0)
701 {
702 flash[pc].r = 1 << (op1 & 7);
703 return OP_bst;
704 }
705 break;
706 case 6:
707 if ((op1 & 8) == 0)
708 {
709 flash[pc].r = 1 << (op1 & 7);
710 return OP_sbrc;
711 }
712 break;
713 case 7:
714 if ((op1 & 8) == 0)
715 {
716 flash[pc].r = 1 << (op1 & 7);
717 return OP_sbrs;
718 }
719 break;
720 }
721 }
df1756f4 722
9943d318 723 return OP_bad;
df1756f4
TG		 724}
725
726static void
82d442c6 727do_call (SIM_CPU *cpu, unsigned int npc)
df1756f4 728{
82d442c6 729 SIM_DESC sd = CPU_STATE (cpu);
df1756f4
TG		 730 unsigned int sp = read_word (REG_SP);
731
732 /* Big endian! */
82d442c6
MF		 733 sram[sp--] = cpu->pc;
734 sram[sp--] = cpu->pc >> 8;
735 if (sd->avr_pc22)
df1756f4 736 {
82d442c6
MF		 737 sram[sp--] = cpu->pc >> 16;
738 cpu->cycles++;
df1756f4
TG		 739 }
740 write_word (REG_SP, sp);
82d442c6
MF		 741 cpu->pc = npc & PC_MASK;
742 cpu->cycles += 3;
df1756f4
TG		 743}
744
745static int
746get_insn_length (unsigned int p)
747{
748 if (flash[p].code == OP_unknown)
749 flash[p].code = decode(p);
750 if (flash[p].code >= OP_2words)
751 return 2;
752 else
753 return 1;
754}
755
756static unsigned int
757get_z (void)
758{
759 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
760}
761
762static unsigned char
763get_lpm (unsigned int addr)
764{
765 word w;
766
767 w = flash[(addr >> 1) & PC_MASK].op;
768 if (addr & 1)
769 w >>= 8;
770 return w;
771}
772
773static void
82d442c6 774gen_mul (SIM_CPU *cpu, unsigned int res)
df1756f4
TG		 775{
776 write_word (0, res);
777 sram[SREG] &= ~(SREG_Z | SREG_C);
778 if (res == 0)
779 sram[SREG] |= SREG_Z;
780 if (res & 0x8000)
781 sram[SREG] |= SREG_C;
82d442c6 782 cpu->cycles++;
df1756f4
TG		 783}
784
9943d318
MF		 785static void
786step_once (SIM_CPU *cpu)
df1756f4
TG		 787{
788 unsigned int ipc;
789
9943d318
MF		 790 int code;
791 word op;
792 byte res;
793 byte r, d, vd;
df1756f4 794
9943d318 795 again:
82d442c6
MF		 796 code = flash[cpu->pc].code;
797 op = flash[cpu->pc].op;
df1756f4 798
9943d318
MF		 799#if 0
800 if (tracing && code != OP_unknown)
df1756f4
TG		 801 {
802 if (verbose > 0) {
803 int flags;
804 int i;
9943d318 805
df1756f4
TG		 806 sim_cb_eprintf (callback, "R00-07:");
807 for (i = 0; i < 8; i++)
808 sim_cb_eprintf (callback, " %02x", sram[i]);
809 sim_cb_eprintf (callback, " -");
810 for (i = 8; i < 16; i++)
811 sim_cb_eprintf (callback, " %02x", sram[i]);
812 sim_cb_eprintf (callback, " SP: %02x %02x",
813 sram[REG_SP + 1], sram[REG_SP]);
814 sim_cb_eprintf (callback, "\n");
815 sim_cb_eprintf (callback, "R16-31:");
816 for (i = 16; i < 24; i++)
817 sim_cb_eprintf (callback, " %02x", sram[i]);
818 sim_cb_eprintf (callback, " -");
819 for (i = 24; i < 32; i++)
820 sim_cb_eprintf (callback, " %02x", sram[i]);
821 sim_cb_eprintf (callback, " ");
822 flags = sram[SREG];
823 for (i = 0; i < 8; i++)
824 sim_cb_eprintf (callback, "%c",
825 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
826 sim_cb_eprintf (callback, "\n");
827 }
828
9943d318 829 if (!tracing)
82d442c6 830 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * cpu->pc, flash[cpu->pc].op);
df1756f4
TG		 831 else
832 {
833 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
82d442c6
MF		 834 2 * cpu->pc, flash[cpu->pc].op, code, flash[cpu->pc].r);
835 disassemble_insn (CPU_STATE (cpu), cpu->pc);
df1756f4
TG		 836 sim_cb_eprintf (callback, "\n");
837 }
838 }
9943d318 839#endif
df1756f4 840
82d442c6
MF		 841 ipc = cpu->pc;
842 cpu->pc = (cpu->pc + 1) & PC_MASK;
843 cpu->cycles++;
df1756f4 844
9943d318
MF		 845 switch (code)
846 {
847 case OP_unknown:
848 flash[ipc].code = decode(ipc);
82d442c6
MF		 849 cpu->pc = ipc;
850 cpu->cycles--;
9943d318
MF		 851 goto again;
852
853 case OP_nop:
854 break;
855
856 case OP_jmp:
857 /* 2 words instruction, but we don't care about the pc. */
82d442c6
MF		 858 cpu->pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
859 cpu->cycles += 2;
9943d318
MF		 860 break;
861
862 case OP_eijmp:
82d442c6
MF		 863 cpu->pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
864 cpu->cycles += 2;
9943d318
MF		 865 break;
866
867 case OP_ijmp:
82d442c6
MF		 868 cpu->pc = read_word (REGZ) & PC_MASK;
869 cpu->cycles += 1;
9943d318
MF		 870 break;
871
872 case OP_call:
873 /* 2 words instruction. */
82d442c6
MF		 874 cpu->pc++;
875 do_call (cpu, (flash[ipc].r << 16) | flash[ipc + 1].op);
9943d318
MF		 876 break;
877
878 case OP_eicall:
82d442c6 879 do_call (cpu, (sram[EIND] << 16) | read_word (REGZ));
9943d318
MF		 880 break;
881
882 case OP_icall:
82d442c6 883 do_call (cpu, read_word (REGZ));
9943d318
MF		 884 break;
885
886 case OP_rcall:
82d442c6 887 do_call (cpu, cpu->pc + sign_ext (op & 0xfff, 12));
9943d318
MF		 888 break;
889
890 case OP_reti:
891 sram[SREG] |= SREG_I;
892 /* Fall through */
893 case OP_ret:
df1756f4 894 {
82d442c6 895 SIM_DESC sd = CPU_STATE (cpu);
9943d318 896 unsigned int sp = read_word (REG_SP);
82d442c6 897 if (sd->avr_pc22)
9943d318 898 {
82d442c6
MF		 899 cpu->pc = sram[++sp] << 16;
900 cpu->cycles++;
9943d318 901 }
df1756f4 902 else
82d442c6
MF		 903 cpu->pc = 0;
904 cpu->pc |= sram[++sp] << 8;
905 cpu->pc |= sram[++sp];
9943d318
MF		 906 write_word (REG_SP, sp);
907 }
82d442c6 908 cpu->cycles += 3;
9943d318
MF		 909 break;
910
911 case OP_break:
912 /* Stop on this address. */
59f48f5a 913 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, ipc, sim_stopped, SIM_SIGTRAP);
9943d318
MF		 914 break;
915
916 case OP_bld:
917 d = get_d (op);
918 r = flash[ipc].r;
919 if (sram[SREG] & SREG_T)
920 sram[d] |= r;
921 else
922 sram[d] &= ~r;
923 break;
924
925 case OP_bst:
926 if (sram[get_d (op)] & flash[ipc].r)
927 sram[SREG] |= SREG_T;
928 else
929 sram[SREG] &= ~SREG_T;
930 break;
931
932 case OP_sbrc:
933 case OP_sbrs:
934 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
df1756f4 935 {
82d442c6
MF		 936 int l = get_insn_length (cpu->pc);
937 cpu->pc += l;
938 cpu->cycles += l;
df1756f4 939 }
9943d318 940 break;
df1756f4 941
9943d318
MF		 942 case OP_push:
943 {
944 unsigned int sp = read_word (REG_SP);
945 sram[sp--] = sram[get_d (op)];
946 write_word (REG_SP, sp);
947 }
82d442c6 948 cpu->cycles++;
9943d318 949 break;
df1756f4 950
9943d318
MF		 951 case OP_pop:
952 {
953 unsigned int sp = read_word (REG_SP);
954 sram[get_d (op)] = sram[++sp];
955 write_word (REG_SP, sp);
956 }
82d442c6 957 cpu->cycles++;
9943d318
MF		 958 break;
959
960 case OP_bclr:
961 sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
962 break;
963
964 case OP_bset:
965 sram[SREG] |= 1 << ((op >> 4) & 0x7);
966 break;
967
968 case OP_rjmp:
82d442c6
MF		 969 cpu->pc = (cpu->pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
970 cpu->cycles++;
9943d318
MF		 971 break;
972
973 case OP_eor:
974 d = get_d (op);
975 res = sram[d] ^ sram[get_r (op)];
976 sram[d] = res;
977 update_flags_logic (res);
978 break;
979
980 case OP_and:
981 d = get_d (op);
982 res = sram[d] & sram[get_r (op)];
983 sram[d] = res;
984 update_flags_logic (res);
985 break;
986
987 case OP_andi:
988 d = get_d16 (op);
989 res = sram[d] & get_K (op);
990 sram[d] = res;
991 update_flags_logic (res);
992 break;
993
994 case OP_or:
995 d = get_d (op);
996 res = sram[d] | sram[get_r (op)];
997 sram[d] = res;
998 update_flags_logic (res);
999 break;
1000
1001 case OP_ori:
1002 d = get_d16 (op);
1003 res = sram[d] | get_K (op);
1004 sram[d] = res;
1005 update_flags_logic (res);
1006 break;
1007
1008 case OP_com:
1009 d = get_d (op);
1010 res = ~sram[d];
1011 sram[d] = res;
1012 update_flags_logic (res);
1013 sram[SREG] |= SREG_C;
1014 break;
1015
1016 case OP_swap:
1017 d = get_d (op);
1018 vd = sram[d];
1019 sram[d] = (vd >> 4) | (vd << 4);
1020 break;
1021
1022 case OP_neg:
1023 d = get_d (op);
1024 vd = sram[d];
1025 res = -vd;
1026 sram[d] = res;
1027 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1028 if (res == 0)
1029 sram[SREG] |= SREG_Z;
1030 else
df1756f4 1031 sram[SREG] |= SREG_C;
9943d318
MF		 1032 if (res == 0x80)
1033 sram[SREG] |= SREG_V | SREG_N;
1034 else if (res & 0x80)
1035 sram[SREG] |= SREG_N | SREG_S;
1036 if ((res | vd) & 0x08)
1037 sram[SREG] |= SREG_H;
1038 break;
1039
1040 case OP_inc:
1041 d = get_d (op);
1042 res = sram[d] + 1;
1043 sram[d] = res;
1044 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1045 if (res == 0x80)
1046 sram[SREG] |= SREG_V | SREG_N;
1047 else if (res & 0x80)
1048 sram[SREG] |= SREG_N | SREG_S;
1049 else if (res == 0)
1050 sram[SREG] |= SREG_Z;
1051 break;
1052
1053 case OP_dec:
1054 d = get_d (op);
1055 res = sram[d] - 1;
1056 sram[d] = res;
1057 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1058 if (res == 0x7f)
1059 sram[SREG] |= SREG_V | SREG_S;
1060 else if (res & 0x80)
1061 sram[SREG] |= SREG_N | SREG_S;
1062 else if (res == 0)
1063 sram[SREG] |= SREG_Z;
1064 break;
1065
1066 case OP_lsr:
1067 case OP_asr:
1068 d = get_d (op);
1069 vd = sram[d];
1070 res = (vd >> 1) | (vd & flash[ipc].r);
1071 sram[d] = res;
1072 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1073 if (vd & 1)
1074 sram[SREG] |= SREG_C | SREG_S;
1075 if (res & 0x80)
1076 sram[SREG] |= SREG_N;
1077 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1078 sram[SREG] |= SREG_V;
1079 if (res == 0)
1080 sram[SREG] |= SREG_Z;
1081 break;
1082
1083 case OP_ror:
1084 d = get_d (op);
1085 vd = sram[d];
1086 res = vd >> 1 | (sram[SREG] << 7);
1087 sram[d] = res;
1088 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1089 if (vd & 1)
1090 sram[SREG] |= SREG_C | SREG_S;
1091 if (res & 0x80)
1092 sram[SREG] |= SREG_N;
1093 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1094 sram[SREG] |= SREG_V;
1095 if (res == 0)
1096 sram[SREG] |= SREG_Z;
1097 break;
1098
1099 case OP_mul:
82d442c6 1100 gen_mul (cpu, (word)sram[get_r (op)] * (word)sram[get_d (op)]);
9943d318
MF		 1101 break;
1102
1103 case OP_muls:
82d442c6
MF		 1104 gen_mul (cpu, (sword)(sbyte)sram[get_r16 (op)]
1105 * (sword)(sbyte)sram[get_d16 (op)]);
9943d318
MF		 1106 break;
1107
1108 case OP_mulsu:
82d442c6
MF		 1109 gen_mul (cpu, (sword)(word)sram[get_r16_23 (op)]
1110 * (sword)(sbyte)sram[get_d16_23 (op)]);
9943d318
MF		 1111 break;
1112
1113 case OP_fmul:
82d442c6
MF		 1114 gen_mul (cpu, ((word)sram[get_r16_23 (op)]
1115 * (word)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1116 break;
1117
1118 case OP_fmuls:
82d442c6
MF		 1119 gen_mul (cpu, ((sword)(sbyte)sram[get_r16_23 (op)]
1120 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1121 break;
1122
1123 case OP_fmulsu:
82d442c6
MF		 1124 gen_mul (cpu, ((sword)(word)sram[get_r16_23 (op)]
1125 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
9943d318
MF		 1126 break;
1127
1128 case OP_adc:
1129 case OP_add:
1130 r = sram[get_r (op)];
1131 d = get_d (op);
1132 vd = sram[d];
1133 res = r + vd + (sram[SREG] & flash[ipc].r);
1134 sram[d] = res;
1135 update_flags_add (res, vd, r);
1136 break;
1137
1138 case OP_sub:
1139 d = get_d (op);
1140 vd = sram[d];
1141 r = sram[get_r (op)];
1142 res = vd - r;
1143 sram[d] = res;
1144 update_flags_sub (res, vd, r);
1145 if (res == 0)
1146 sram[SREG] |= SREG_Z;
1147 break;
1148
1149 case OP_sbc:
1150 {
1151 byte old = sram[SREG];
df1756f4
TG		 1152 d = get_d (op);
1153 vd = sram[d];
1154 r = sram[get_r (op)];
9943d318 1155 res = vd - r - (old & SREG_C);
df1756f4
TG		 1156 sram[d] = res;
1157 update_flags_sub (res, vd, r);
9943d318 1158 if (res == 0 && (old & SREG_Z))
df1756f4 1159 sram[SREG] |= SREG_Z;
9943d318
MF		 1160 }
1161 break;
1162
1163 case OP_subi:
1164 d = get_d16 (op);
1165 vd = sram[d];
1166 r = get_K (op);
1167 res = vd - r;
1168 sram[d] = res;
1169 update_flags_sub (res, vd, r);
1170 if (res == 0)
1171 sram[SREG] |= SREG_Z;
1172 break;
1173
1174 case OP_sbci:
1175 {
1176 byte old = sram[SREG];
df1756f4 1177
df1756f4
TG		 1178 d = get_d16 (op);
1179 vd = sram[d];
1180 r = get_K (op);
9943d318 1181 res = vd - r - (old & SREG_C);
df1756f4
TG		 1182 sram[d] = res;
1183 update_flags_sub (res, vd, r);
9943d318 1184 if (res == 0 && (old & SREG_Z))
df1756f4 1185 sram[SREG] |= SREG_Z;
9943d318
MF		 1186 }
1187 break;
1188
1189 case OP_mov:
1190 sram[get_d (op)] = sram[get_r (op)];
1191 break;
1192
1193 case OP_movw:
1194 d = (op & 0xf0) >> 3;
1195 r = (op & 0x0f) << 1;
1196 sram[d] = sram[r];
1197 sram[d + 1] = sram[r + 1];
1198 break;
1199
1200 case OP_out:
1201 d = get_A (op) + 0x20;
1202 res = sram[get_d (op)];
1203 sram[d] = res;
1204 if (d == STDIO_PORT)
1205 putchar (res);
1206 else if (d == EXIT_PORT)
82d442c6 1207 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 0);
9943d318 1208 else if (d == ABORT_PORT)
82d442c6 1209 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_exited, 1);
9943d318
MF		 1210 break;
1211
1212 case OP_in:
1213 d = get_A (op) + 0x20;
1214 sram[get_d (op)] = sram[d];
1215 break;
1216
1217 case OP_cbi:
1218 d = get_biA (op) + 0x20;
1219 sram[d] &= ~(1 << get_b(op));
1220 break;
1221
1222 case OP_sbi:
1223 d = get_biA (op) + 0x20;
1224 sram[d] |= 1 << get_b(op);
1225 break;
1226
1227 case OP_sbic:
1228 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
df1756f4 1229 {
82d442c6
MF		 1230 int l = get_insn_length (cpu->pc);
1231 cpu->pc += l;
1232 cpu->cycles += l;
df1756f4 1233 }
9943d318 1234 break;
df1756f4 1235
9943d318
MF		 1236 case OP_sbis:
1237 if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1238 {
82d442c6
MF		 1239 int l = get_insn_length (cpu->pc);
1240 cpu->pc += l;
1241 cpu->cycles += l;
9943d318
MF		 1242 }
1243 break;
1244
1245 case OP_ldi:
1246 res = get_K (op);
1247 d = get_d16 (op);
1248 sram[d] = res;
1249 break;
1250
1251 case OP_lds:
82d442c6
MF		 1252 sram[get_d (op)] = sram[flash[cpu->pc].op];
1253 cpu->pc++;
1254 cpu->cycles++;
9943d318
MF		 1255 break;
1256
1257 case OP_sts:
82d442c6
MF		 1258 sram[flash[cpu->pc].op] = sram[get_d (op)];
1259 cpu->pc++;
1260 cpu->cycles++;
9943d318
MF		 1261 break;
1262
1263 case OP_cpse:
1264 if (sram[get_r (op)] == sram[get_d (op)])
1265 {
82d442c6
MF		 1266 int l = get_insn_length (cpu->pc);
1267 cpu->pc += l;
1268 cpu->cycles += l;
9943d318
MF		 1269 }
1270 break;
1271
1272 case OP_cp:
1273 r = sram[get_r (op)];
1274 d = sram[get_d (op)];
1275 res = d - r;
1276 update_flags_sub (res, d, r);
1277 if (res == 0)
1278 sram[SREG] |= SREG_Z;
1279 break;
1280
1281 case OP_cpi:
1282 r = get_K (op);
1283 d = sram[get_d16 (op)];
1284 res = d - r;
1285 update_flags_sub (res, d, r);
1286 if (res == 0)
1287 sram[SREG] |= SREG_Z;
1288 break;
1289
1290 case OP_cpc:
1291 {
1292 byte old = sram[SREG];
df1756f4 1293 d = sram[get_d (op)];
9943d318
MF		 1294 r = sram[get_r (op)];
1295 res = d - r - (old & SREG_C);
df1756f4 1296 update_flags_sub (res, d, r);
9943d318 1297 if (res == 0 && (old & SREG_Z))
df1756f4 1298 sram[SREG] |= SREG_Z;
9943d318
MF		 1299 }
1300 break;
df1756f4 1301
9943d318
MF		 1302 case OP_brbc:
1303 if (!(sram[SREG] & flash[ipc].r))
1304 {
82d442c6
MF		 1305 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK;
1306 cpu->cycles++;
9943d318
MF		 1307 }
1308 break;
df1756f4 1309
9943d318
MF		 1310 case OP_brbs:
1311 if (sram[SREG] & flash[ipc].r)
df1756f4 1312 {
82d442c6
MF		 1313 cpu->pc = (cpu->pc + get_k (op)) & PC_MASK;
1314 cpu->cycles++;
df1756f4 1315 }
9943d318
MF		 1316 break;
1317
1318 case OP_lpm:
1319 sram[0] = get_lpm (read_word (REGZ));
82d442c6 1320 cpu->cycles += 2;
9943d318
MF		 1321 break;
1322
1323 case OP_lpm_Z:
1324 sram[get_d (op)] = get_lpm (read_word (REGZ));
82d442c6 1325 cpu->cycles += 2;
9943d318
MF		 1326 break;
1327
1328 case OP_lpm_inc_Z:
1329 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
82d442c6 1330 cpu->cycles += 2;
9943d318
MF		 1331 break;
1332
1333 case OP_elpm:
1334 sram[0] = get_lpm (get_z ());
82d442c6 1335 cpu->cycles += 2;
9943d318
MF		 1336 break;
1337
1338 case OP_elpm_Z:
1339 sram[get_d (op)] = get_lpm (get_z ());
82d442c6 1340 cpu->cycles += 2;
9943d318
MF		 1341 break;
1342
1343 case OP_elpm_inc_Z:
1344 {
1345 unsigned int z = get_z ();
df1756f4 1346
9943d318
MF		 1347 sram[get_d (op)] = get_lpm (z);
1348 z++;
1349 sram[REGZ_LO] = z;
1350 sram[REGZ_HI] = z >> 8;
1351 sram[RAMPZ] = z >> 16;
1352 }
82d442c6 1353 cpu->cycles += 2;
9943d318
MF		 1354 break;
1355
1356 case OP_ld_Z_inc:
1357 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
82d442c6 1358 cpu->cycles++;
9943d318
MF		 1359 break;
1360
1361 case OP_ld_dec_Z:
1362 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
82d442c6 1363 cpu->cycles++;
9943d318
MF		 1364 break;
1365
1366 case OP_ld_X_inc:
1367 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
82d442c6 1368 cpu->cycles++;
9943d318
MF		 1369 break;
1370
1371 case OP_ld_dec_X:
1372 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
82d442c6 1373 cpu->cycles++;
9943d318
MF		 1374 break;
1375
1376 case OP_ld_Y_inc:
1377 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
82d442c6 1378 cpu->cycles++;
9943d318
MF		 1379 break;
1380
1381 case OP_ld_dec_Y:
1382 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
82d442c6 1383 cpu->cycles++;
9943d318
MF		 1384 break;
1385
1386 case OP_st_X:
1387 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1388 cpu->cycles++;
9943d318
MF		 1389 break;
1390
1391 case OP_st_X_inc:
1392 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1393 cpu->cycles++;
9943d318
MF		 1394 break;
1395
1396 case OP_st_dec_X:
1397 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1398 cpu->cycles++;
9943d318
MF		 1399 break;
1400
1401 case OP_st_Z_inc:
1402 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1403 cpu->cycles++;
9943d318
MF		 1404 break;
1405
1406 case OP_st_dec_Z:
1407 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1408 cpu->cycles++;
9943d318
MF		 1409 break;
1410
1411 case OP_st_Y_inc:
1412 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1413 cpu->cycles++;
9943d318
MF		 1414 break;
1415
1416 case OP_st_dec_Y:
1417 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
82d442c6 1418 cpu->cycles++;
9943d318
MF		 1419 break;
1420
1421 case OP_std_Y:
1422 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
82d442c6 1423 cpu->cycles++;
9943d318
MF		 1424 break;
1425
1426 case OP_std_Z:
1427 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
82d442c6 1428 cpu->cycles++;
9943d318
MF		 1429 break;
1430
1431 case OP_ldd_Z:
1432 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
82d442c6 1433 cpu->cycles++;
9943d318
MF		 1434 break;
1435
1436 case OP_ldd_Y:
1437 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
82d442c6 1438 cpu->cycles++;
9943d318
MF		 1439 break;
1440
1441 case OP_ld_X:
1442 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
82d442c6 1443 cpu->cycles++;
9943d318
MF		 1444 break;
1445
1446 case OP_sbiw:
1447 {
1448 word wk = get_k6 (op);
1449 word wres;
1450 word wr;
df1756f4 1451
9943d318
MF		 1452 d = get_d24 (op);
1453 wr = read_word (d);
1454 wres = wr - wk;
df1756f4 1455
9943d318
MF		 1456 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1457 if (wres == 0)
1458 sram[SREG] |= SREG_Z;
1459 if (wres & 0x8000)
1460 sram[SREG] |= SREG_N;
1461 if (wres & ~wr & 0x8000)
1462 sram[SREG] |= SREG_C;
1463 if (~wres & wr & 0x8000)
1464 sram[SREG] |= SREG_V;
1465 if (((~wres & wr) ^ wres) & 0x8000)
1466 sram[SREG] |= SREG_S;
1467 write_word (d, wres);
1468 }
82d442c6 1469 cpu->cycles++;
9943d318 1470 break;
df1756f4 1471
9943d318
MF		 1472 case OP_adiw:
1473 {
1474 word wk = get_k6 (op);
1475 word wres;
1476 word wr;
1477
1478 d = get_d24 (op);
1479 wr = read_word (d);
1480 wres = wr + wk;
1481
1482 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1483 if (wres == 0)
1484 sram[SREG] |= SREG_Z;
1485 if (wres & 0x8000)
1486 sram[SREG] |= SREG_N;
1487 if (~wres & wr & 0x8000)
1488 sram[SREG] |= SREG_C;
1489 if (wres & ~wr & 0x8000)
1490 sram[SREG] |= SREG_V;
1491 if (((wres & ~wr) ^ wres) & 0x8000)
1492 sram[SREG] |= SREG_S;
1493 write_word (d, wres);
df1756f4 1494 }
82d442c6 1495 cpu->cycles++;
9943d318 1496 break;
df1756f4 1497
9943d318 1498 case OP_bad:
82d442c6 1499 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
df1756f4 1500
9943d318 1501 default:
82d442c6 1502 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
9943d318
MF		 1503 }
1504}
1505
1506void
1507sim_engine_run (SIM_DESC sd,
1508 int next_cpu_nr, /* ignore */
1509 int nr_cpus, /* ignore */
1510 int siggnal) /* ignore */
df1756f4 1511{
9943d318
MF		 1512 SIM_CPU *cpu;
1513
1514 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1515
1516 cpu = STATE_CPU (sd, 0);
df1756f4 1517
9943d318
MF		 1518 while (1)
1519 {
1520 step_once (cpu);
1521 if (sim_events_tick (sd))
1522 sim_events_process (sd);
1523 }
df1756f4
TG		 1524}
1525
1526int
5558e7e6 1527sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
df1756f4
TG		 1528{
1529 int osize = size;
1530
1531 if (addr >= 0 && addr < SRAM_VADDR)
1532 {
8f0ac700 1533 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1534 {
8f0ac700
TG		 1535 word val = flash[addr >> 1].op;
1536
1537 if (addr & 1)
1538 val = (val & 0xff) | (buffer[0] << 8);
1539 else
1540 val = (val & 0xff00) | buffer[0];
1541
1542 flash[addr >> 1].op = val;
1543 flash[addr >> 1].code = OP_unknown;
df1756f4 1544 addr++;
8f0ac700
TG		 1545 buffer++;
1546 size--;
df1756f4
TG		 1547 }
1548 return osize - size;
1549 }
1550 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1551 {
1552 addr -= SRAM_VADDR;
1553 if (addr + size > MAX_AVR_SRAM)
1554 size = MAX_AVR_SRAM - addr;
1555 memcpy (sram + addr, buffer, size);
1556 return size;
1557 }
1558 else
1559 return 0;
1560}
1561
1562int
1563sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1564{
1565 int osize = size;
1566
1567 if (addr >= 0 && addr < SRAM_VADDR)
1568 {
8f0ac700 1569 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
df1756f4 1570 {
8f0ac700
TG		 1571 word val = flash[addr >> 1].op;
1572
1573 if (addr & 1)
1574 val >>= 8;
1575
1576 *buffer++ = val;
df1756f4 1577 addr++;
8f0ac700 1578 size--;
df1756f4
TG		 1579 }
1580 return osize - size;
1581 }
1582 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1583 {
1584 addr -= SRAM_VADDR;
1585 if (addr + size > MAX_AVR_SRAM)
1586 size = MAX_AVR_SRAM - addr;
1587 memcpy (buffer, sram + addr, size);
1588 return size;
1589 }
1590 else
1591 {
1592 /* Avoid errors. */
1593 memset (buffer, 0, size);
1594 return size;
1595 }
1596}
1597
807eaf04
MF		 1598static int
1599avr_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
df1756f4
TG		 1600{
1601 if (rn < 32 && length == 1)
1602 {
1603 sram[rn] = *memory;
1604 return 1;
1605 }
1606 if (rn == AVR_SREG_REGNUM && length == 1)
1607 {
1608 sram[SREG] = *memory;
1609 return 1;
1610 }
1611 if (rn == AVR_SP_REGNUM && length == 2)
1612 {
1613 sram[REG_SP] = memory[0];
1614 sram[REG_SP + 1] = memory[1];
1615 return 2;
1616 }
1617 if (rn == AVR_PC_REGNUM && length == 4)
1618 {
82d442c6
MF		 1619 cpu->pc = (memory[0] >> 1) | (memory[1] << 7)
1620 | (memory[2] << 15) | (memory[3] << 23);
1621 cpu->pc &= PC_MASK;
df1756f4
TG		 1622 return 4;
1623 }
1624 return 0;
1625}
1626
807eaf04
MF		 1627static int
1628avr_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
df1756f4
TG		 1629{
1630 if (rn < 32 && length == 1)
1631 {
1632 *memory = sram[rn];
1633 return 1;
1634 }
1635 if (rn == AVR_SREG_REGNUM && length == 1)
1636 {
1637 *memory = sram[SREG];
1638 return 1;
1639 }
1640 if (rn == AVR_SP_REGNUM && length == 2)
1641 {
1642 memory[0] = sram[REG_SP];
1643 memory[1] = sram[REG_SP + 1];
1644 return 2;
1645 }
1646 if (rn == AVR_PC_REGNUM && length == 4)
1647 {
82d442c6
MF		 1648 memory[0] = cpu->pc << 1;
1649 memory[1] = cpu->pc >> 7;
1650 memory[2] = cpu->pc >> 15;
1651 memory[3] = cpu->pc >> 23;
df1756f4
TG		 1652 return 4;
1653 }
1654 return 0;
1655}
1656
4c0cab1e
MF		 1657static sim_cia
1658avr_pc_get (sim_cpu *cpu)
1659{
82d442c6 1660 return cpu->pc;
4c0cab1e
MF		 1661}
1662
1663static void
82d442c6 1664avr_pc_set (sim_cpu *cpu, sim_cia pc)
4c0cab1e 1665{
82d442c6 1666 cpu->pc = pc;
4c0cab1e
MF		 1667}
1668
9943d318
MF		 1669static void
1670free_state (SIM_DESC sd)
df1756f4 1671{
9943d318
MF		 1672 if (STATE_MODULES (sd) != NULL)
1673 sim_module_uninstall (sd);
1674 sim_cpu_free_all (sd);
1675 sim_state_free (sd);
df1756f4
TG		 1676}
1677
1678SIM_DESC
2e3d4f4d
MF		 1679sim_open (SIM_OPEN_KIND kind, host_callback *cb,
1680 struct bfd *abfd, char * const *argv)
df1756f4 1681{
4c0cab1e 1682 int i;
9943d318
MF		 1683 SIM_DESC sd = sim_state_alloc (kind, cb);
1684 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
df1756f4 1685
9943d318 1686 /* The cpu data is kept in a separately allocated chunk of memory. */
d5a71b11 1687 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
9943d318
MF		 1688 {
1689 free_state (sd);
1690 return 0;
1691 }
df1756f4 1692
9943d318
MF		 1693 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1694 {
1695 free_state (sd);
1696 return 0;
1697 }
df1756f4 1698
77cf2ef5 1699 /* The parser will print an error message for us, so we silently return. */
9943d318
MF		 1700 if (sim_parse_args (sd, argv) != SIM_RC_OK)
1701 {
1702 free_state (sd);
1703 return 0;
1704 }
33bcfade 1705
9943d318
MF		 1706 /* Check for/establish the a reference program image. */
1707 if (sim_analyze_program (sd,
1708 (STATE_PROG_ARGV (sd) != NULL
1709 ? *STATE_PROG_ARGV (sd)
1710 : NULL), abfd) != SIM_RC_OK)
1711 {
1712 free_state (sd);
1713 return 0;
1714 }
df1756f4 1715
9943d318
MF		 1716 /* Configure/verify the target byte order and other runtime
1717 configuration options. */
1718 if (sim_config (sd) != SIM_RC_OK)
1719 {
1720 sim_module_uninstall (sd);
1721 return 0;
1722 }
df1756f4 1723
9943d318
MF		 1724 if (sim_post_argv_init (sd) != SIM_RC_OK)
1725 {
1726 /* Uninstall the modules to avoid memory leaks,
1727 file descriptor leaks, etc. */
1728 sim_module_uninstall (sd);
1729 return 0;
1730 }
df1756f4 1731
4c0cab1e
MF		 1732 /* CPU specific initialization. */
1733 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
1734 {
1735 SIM_CPU *cpu = STATE_CPU (sd, i);
1736
807eaf04
MF		 1737 CPU_REG_FETCH (cpu) = avr_reg_fetch;
1738 CPU_REG_STORE (cpu) = avr_reg_store;
4c0cab1e
MF		 1739 CPU_PC_FETCH (cpu) = avr_pc_get;
1740 CPU_PC_STORE (cpu) = avr_pc_set;
1741 }
1742
9943d318
MF		 1743 /* Clear all the memory. */
1744 memset (sram, 0, sizeof (sram));
1745 memset (flash, 0, sizeof (flash));
df1756f4 1746
9943d318 1747 return sd;
df1756f4
TG		 1748}
1749
9943d318 1750SIM_RC
2e3d4f4d
MF		 1751sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
1752 char * const *argv, char * const *env)
df1756f4 1753{
82d442c6
MF		 1754 SIM_CPU *cpu = STATE_CPU (sd, 0);
1755 SIM_ADDR addr;
1756
9943d318
MF		 1757 /* Set the PC. */
1758 if (abfd != NULL)
82d442c6 1759 addr = bfd_get_start_address (abfd);
9943d318 1760 else
82d442c6
MF		 1761 addr = 0;
1762 sim_pc_set (cpu, addr);
af9f7da7 1763
9943d318 1764 if (abfd != NULL)
82d442c6 1765 sd->avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6);
9943d318
MF		 1766
1767 return SIM_RC_OK;
af9f7da7 1768}
A mirror of the official binutils-gdb repository