[thirdparty/binutils-gdb.git] / sim / bfin / dv-bfin_otp.c

/* Blackfin One-Time Programmable Memory (OTP) model

   Copyright (C) 2010-2021 Free Software Foundation, Inc.
   Contributed by Analog Devices, Inc.

   This file is part of simulators.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This must come before any other includes.  */
#include "defs.h"

#include "sim-main.h"
#include "devices.h"
#include "dv-bfin_otp.h"

/* XXX: No public documentation on this interface.  This seems to work
        with the on-chip ROM functions though and was figured out by
        disassembling & walking that code.  */
/* XXX: About only thing that should be done here are CRC fields.  And
        supposedly there is an interrupt that could be generated.  */

struct bfin_otp
{
  bu32 base;

  /* The actual OTP storage -- 0x200 pages, each page is 128bits.
     While certain pages have predefined and/or secure access, we don't
     bother trying to implement that coverage.  All pages are open for
     reading & writing.  */
  bu32 mem[0x200 * 4];

  /* Order after here is important -- matches hardware MMR layout.  */
  bu16 BFIN_MMR_16(control);
  bu16 BFIN_MMR_16(ben);
  bu16 BFIN_MMR_16(status);
  bu32 timing;
  bu32 _pad0[28];
  bu32 data0, data1, data2, data3;
};
#define mmr_base()      offsetof(struct bfin_otp, control)
#define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
#define mmr_idx(mmr)    (mmr_offset (mmr) / 4)

static const char * const mmr_names[] =
{
  "OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
  [mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
};
#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")

/* XXX: This probably misbehaves with big endian hosts.  */
static void
bfin_otp_transfer (struct bfin_otp *otp, void *vdst, void *vsrc)
{
  bu8 *dst = vdst, *src = vsrc;
  int bidx;
  for (bidx = 0; bidx < 16; ++bidx)
    if (otp->ben & (1 << bidx))
      dst[bidx] = src[bidx];
}

static void
bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
{
  bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
}

static void
bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
{
  bfin_otp_transfer (otp, &otp->mem[page * 4], val);
}
static void
bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
{
  bu64 val[2] = { lo, hi };
  bfin_otp_write_page_val (otp, page, val);
}
static void
bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
{
  bfin_otp_write_page_val2 (otp, page, ((bu64)otp->data1 << 32) | otp->data0,
			    ((bu64)otp->data3 << 32) | otp->data2);
}

static unsigned
bfin_otp_io_write_buffer (struct hw *me, const void *source, int space,
			  address_word addr, unsigned nr_bytes)
{
  struct bfin_otp *otp = hw_data (me);
  bu32 mmr_off;
  bu32 value;
  bu16 *value16p;
  bu32 *value32p;
  void *valuep;

  /* Invalid access mode is higher priority than missing register.  */
  if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
    return 0;

  if (nr_bytes == 4)
    value = dv_load_4 (source);
  else
    value = dv_load_2 (source);

  mmr_off = addr - otp->base;
  valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
  value16p = valuep;
  value32p = valuep;

  HW_TRACE_WRITE ();

  switch (mmr_off)
    {
    case mmr_offset(control):
      {
	int page;

	if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
	  return 0;
	/* XXX: Seems like these bits aren't writable.  */
	*value16p = value & 0x39FF;

	/* Low bits seem to be the page address.  */
	page = value & PAGE_ADDR;

	/* Write operation.  */
	if (value & DO_WRITE)
	  bfin_otp_write_page (otp, page);

	/* Read operation.  */
	if (value & DO_READ)
	  bfin_otp_read_page (otp, page);

	otp->status |= STATUS_DONE;

	break;
      }
    case mmr_offset(ben):
      if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
	return 0;
      /* XXX: All bits seem to be writable.  */
      *value16p = value;
      break;
    case mmr_offset(status):
      if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
	return 0;
      /* XXX: All bits seem to be W1C.  */
      dv_w1c_2 (value16p, value, -1);
      break;
    case mmr_offset(timing):
    case mmr_offset(data0):
    case mmr_offset(data1):
    case mmr_offset(data2):
    case mmr_offset(data3):
      if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
	return 0;
      *value32p = value;
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
      return 0;
    }

  return nr_bytes;
}

static unsigned
bfin_otp_io_read_buffer (struct hw *me, void *dest, int space,
			 address_word addr, unsigned nr_bytes)
{
  struct bfin_otp *otp = hw_data (me);
  bu32 mmr_off;
  bu16 *value16p;
  bu32 *value32p;
  void *valuep;

  /* Invalid access mode is higher priority than missing register.  */
  if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
    return 0;

  mmr_off = addr - otp->base;
  valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
  value16p = valuep;
  value32p = valuep;

  HW_TRACE_READ ();

  switch (mmr_off)
    {
    case mmr_offset(control):
    case mmr_offset(ben):
    case mmr_offset(status):
      if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
	return 0;
      dv_store_2 (dest, *value16p);
      break;
    case mmr_offset(timing):
    case mmr_offset(data0):
    case mmr_offset(data1):
    case mmr_offset(data2):
    case mmr_offset(data3):
      if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
	return 0;
      dv_store_4 (dest, *value32p);
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
      return 0;
    }

  return nr_bytes;
}

static void
attach_bfin_otp_regs (struct hw *me, struct bfin_otp *otp)
{
  address_word attach_address;
  int attach_space;
  unsigned attach_size;
  reg_property_spec reg;

  if (hw_find_property (me, "reg") == NULL)
    hw_abort (me, "Missing \"reg\" property");

  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
    hw_abort (me, "\"reg\" property must contain three addr/size entries");

  hw_unit_address_to_attach_address (hw_parent (me),
				     &reg.address,
				     &attach_space, &attach_address, me);
  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);

  if (attach_size != BFIN_MMR_OTP_SIZE)
    hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);

  hw_attach_address (hw_parent (me),
		     0, attach_space, attach_address, attach_size, me);

  otp->base = attach_address;
}

static const struct hw_port_descriptor bfin_otp_ports[] =
{
  { "stat", 0, 0, output_port, },
  { NULL, 0, 0, 0, },
};

static void
bfin_otp_finish (struct hw *me)
{
  char part_str[16];
  struct bfin_otp *otp;
  unsigned int fps03;
  int type = hw_find_integer_property (me, "type");

  otp = HW_ZALLOC (me, struct bfin_otp);

  set_hw_data (me, otp);
  set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
  set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
  set_hw_ports (me, bfin_otp_ports);

  attach_bfin_otp_regs (me, otp);

  /* Initialize the OTP.  */
  otp->ben     = 0xFFFF;
  otp->timing  = 0x00001485;

  /* Semi-random value for unique chip id.  */
  bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);

  memset (part_str, 0, sizeof (part_str));
  sprintf (part_str, "ADSP-BF%iX", type);
  switch (type)
    {
    case 512:
      fps03 = FPS03_BF512;
      break;
    case 514:
      fps03 = FPS03_BF514;
      break;
    case 516:
      fps03 = FPS03_BF516;
      break;
    case 518:
      fps03 = FPS03_BF518;
      break;
    case 522:
      fps03 = FPS03_BF522;
      break;
    case 523:
      fps03 = FPS03_BF523;
      break;
    case 524:
      fps03 = FPS03_BF524;
      break;
    case 525:
      fps03 = FPS03_BF525;
      break;
    case 526:
      fps03 = FPS03_BF526;
      break;
    case 527:
      fps03 = FPS03_BF527;
      break;
    default:
      fps03 = 0;
      break;
    }
  part_str[14] = (fps03 >> 0);
  part_str[15] = (fps03 >> 8);
  bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
}

const struct hw_descriptor dv_bfin_otp_descriptor[] =
{
  {"bfin_otp", bfin_otp_finish,},
  {NULL, NULL},
};
Commit	Line	Data
ef016f83 MF	1	/* Blackfin One-Time Programmable Memory (OTP) model
ef016f83 MF	2
3666a048	3	Copyright (C) 2010-2021 Free Software Foundation, Inc.
ef016f83 MF	4	Contributed by Analog Devices, Inc.
	5
	6	This file is part of simulators.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
6df01ab8 MF	21	/* This must come before any other includes. */
6df01ab8 MF	22	#include "defs.h"
ef016f83 MF	23
	24	#include "sim-main.h"
	25	#include "devices.h"
	26	#include "dv-bfin_otp.h"
	27
	28	/* XXX: No public documentation on this interface. This seems to work
	29	with the on-chip ROM functions though and was figured out by
	30	disassembling & walking that code. */
	31	/* XXX: About only thing that should be done here are CRC fields. And
	32	supposedly there is an interrupt that could be generated. */
	33
	34	struct bfin_otp
	35	{
	36	bu32 base;
	37
	38	/* The actual OTP storage -- 0x200 pages, each page is 128bits.
	39	While certain pages have predefined and/or secure access, we don't
	40	bother trying to implement that coverage. All pages are open for
	41	reading & writing. */
	42	bu32 mem[0x200 * 4];
	43
	44	/* Order after here is important -- matches hardware MMR layout. */
	45	bu16 BFIN_MMR_16(control);
	46	bu16 BFIN_MMR_16(ben);
	47	bu16 BFIN_MMR_16(status);
	48	bu32 timing;
	49	bu32 _pad0[28];
	50	bu32 data0, data1, data2, data3;
	51	};
	52	#define mmr_base() offsetof(struct bfin_otp, control)
	53	#define mmr_offset(mmr) (offsetof(struct bfin_otp, mmr) - mmr_base())
	54	#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
	55
990d19fd MF	56	static const char * const mmr_names[] =
990d19fd MF	57	{
ef016f83 MF	58	"OTP_CONTROL", "OTP_BEN", "OTP_STATUS", "OTP_TIMING",
	59	[mmr_idx (data0)] = "OTP_DATA0", "OTP_DATA1", "OTP_DATA2", "OTP_DATA3",
	60	};
	61	#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
	62
	63	/* XXX: This probably misbehaves with big endian hosts. */
	64	static void
	65	bfin_otp_transfer (struct bfin_otp otp, void vdst, void *vsrc)
	66	{
	67	bu8 dst = vdst, src = vsrc;
	68	int bidx;
	69	for (bidx = 0; bidx < 16; ++bidx)
	70	if (otp->ben & (1 << bidx))
	71	dst[bidx] = src[bidx];
	72	}
	73
	74	static void
	75	bfin_otp_read_page (struct bfin_otp *otp, bu16 page)
	76	{
	77	bfin_otp_transfer (otp, &otp->data0, &otp->mem[page * 4]);
	78	}
	79
	80	static void
	81	bfin_otp_write_page_val (struct bfin_otp *otp, bu16 page, bu64 val[2])
	82	{
	83	bfin_otp_transfer (otp, &otp->mem[page * 4], val);
	84	}
	85	static void
	86	bfin_otp_write_page_val2 (struct bfin_otp *otp, bu16 page, bu64 lo, bu64 hi)
	87	{
	88	bu64 val[2] = { lo, hi };
	89	bfin_otp_write_page_val (otp, page, val);
	90	}
	91	static void
	92	bfin_otp_write_page (struct bfin_otp *otp, bu16 page)
	93	{
f006d9e2 MF	94	bfin_otp_write_page_val2 (otp, page, ((bu64)otp->data1 << 32) \| otp->data0,
f006d9e2 MF	95	((bu64)otp->data3 << 32) \| otp->data2);
ef016f83 MF	96	}
	97
	98	static unsigned
	99	bfin_otp_io_write_buffer (struct hw me, const void source, int space,
	100	address_word addr, unsigned nr_bytes)
	101	{
	102	struct bfin_otp *otp = hw_data (me);
	103	bu32 mmr_off;
	104	bu32 value;
	105	bu16 *value16p;
	106	bu32 *value32p;
	107	void *valuep;
	108
466b619e MF	109	/* Invalid access mode is higher priority than missing register. */
	110	if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
	111	return 0;
	112
ef016f83 MF	113	if (nr_bytes == 4)
	114	value = dv_load_4 (source);
	115	else
	116	value = dv_load_2 (source);
	117
	118	mmr_off = addr - otp->base;
	119	valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
	120	value16p = valuep;
	121	value32p = valuep;
	122
	123	HW_TRACE_WRITE ();
	124
	125	switch (mmr_off)
	126	{
	127	case mmr_offset(control):
	128	{
	129	int page;
	130
466b619e MF	131	if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
466b619e MF	132	return 0;
ef016f83 MF	133	/* XXX: Seems like these bits aren't writable. */
	134	*value16p = value & 0x39FF;
	135
	136	/* Low bits seem to be the page address. */
	137	page = value & PAGE_ADDR;
	138
	139	/* Write operation. */
	140	if (value & DO_WRITE)
	141	bfin_otp_write_page (otp, page);
	142
	143	/* Read operation. */
	144	if (value & DO_READ)
	145	bfin_otp_read_page (otp, page);
	146
	147	otp->status \|= STATUS_DONE;
	148
	149	break;
	150	}
	151	case mmr_offset(ben):
466b619e MF	152	if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
466b619e MF	153	return 0;
ef016f83 MF	154	/* XXX: All bits seem to be writable. */
	155	*value16p = value;
	156	break;
	157	case mmr_offset(status):
466b619e MF	158	if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
466b619e MF	159	return 0;
ef016f83	160	/* XXX: All bits seem to be W1C. */
9922f803	161	dv_w1c_2 (value16p, value, -1);
ef016f83 MF	162	break;
	163	case mmr_offset(timing):
	164	case mmr_offset(data0):
	165	case mmr_offset(data1):
	166	case mmr_offset(data2):
	167	case mmr_offset(data3):
466b619e MF	168	if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
466b619e MF	169	return 0;
ef016f83 MF	170	*value32p = value;
	171	break;
	172	default:
	173	dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
466b619e	174	return 0;
ef016f83 MF	175	}
	176
	177	return nr_bytes;
	178	}
	179
	180	static unsigned
	181	bfin_otp_io_read_buffer (struct hw me, void dest, int space,
	182	address_word addr, unsigned nr_bytes)
	183	{
	184	struct bfin_otp *otp = hw_data (me);
	185	bu32 mmr_off;
	186	bu16 *value16p;
	187	bu32 *value32p;
	188	void *valuep;
	189
466b619e MF	190	/* Invalid access mode is higher priority than missing register. */
	191	if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
	192	return 0;
	193
ef016f83 MF	194	mmr_off = addr - otp->base;
	195	valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
	196	value16p = valuep;
	197	value32p = valuep;
	198
	199	HW_TRACE_READ ();
	200
	201	switch (mmr_off)
	202	{
	203	case mmr_offset(control):
	204	case mmr_offset(ben):
	205	case mmr_offset(status):
466b619e MF	206	if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
466b619e MF	207	return 0;
ef016f83 MF	208	dv_store_2 (dest, *value16p);
	209	break;
	210	case mmr_offset(timing):
	211	case mmr_offset(data0):
	212	case mmr_offset(data1):
	213	case mmr_offset(data2):
	214	case mmr_offset(data3):
466b619e MF	215	if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
466b619e MF	216	return 0;
ef016f83 MF	217	dv_store_4 (dest, *value32p);
	218	break;
	219	default:
	220	dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
466b619e	221	return 0;
ef016f83 MF	222	}
	223
	224	return nr_bytes;
	225	}
	226
	227	static void
	228	attach_bfin_otp_regs (struct hw me, struct bfin_otp otp)
	229	{
	230	address_word attach_address;
	231	int attach_space;
	232	unsigned attach_size;
	233	reg_property_spec reg;
	234
	235	if (hw_find_property (me, "reg") == NULL)
	236	hw_abort (me, "Missing \"reg\" property");
	237
	238	if (!hw_find_reg_array_property (me, "reg", 0, &reg))
	239	hw_abort (me, "\"reg\" property must contain three addr/size entries");
	240
	241	hw_unit_address_to_attach_address (hw_parent (me),
	242	&reg.address,
	243	&attach_space, &attach_address, me);
	244	hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
	245
	246	if (attach_size != BFIN_MMR_OTP_SIZE)
	247	hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_OTP_SIZE);
	248
	249	hw_attach_address (hw_parent (me),
	250	0, attach_space, attach_address, attach_size, me);
	251
	252	otp->base = attach_address;
	253	}
	254
2b12772f MF	255	static const struct hw_port_descriptor bfin_otp_ports[] =
	256	{
	257	{ "stat", 0, 0, output_port, },
	258	{ NULL, 0, 0, 0, },
	259	};
	260
ef016f83 MF	261	static void
	262	bfin_otp_finish (struct hw *me)
	263	{
	264	char part_str[16];
	265	struct bfin_otp *otp;
	266	unsigned int fps03;
	267	int type = hw_find_integer_property (me, "type");
	268
	269	otp = HW_ZALLOC (me, struct bfin_otp);
	270
	271	set_hw_data (me, otp);
	272	set_hw_io_read_buffer (me, bfin_otp_io_read_buffer);
	273	set_hw_io_write_buffer (me, bfin_otp_io_write_buffer);
2b12772f	274	set_hw_ports (me, bfin_otp_ports);
ef016f83 MF	275
	276	attach_bfin_otp_regs (me, otp);
	277
	278	/* Initialize the OTP. */
	279	otp->ben = 0xFFFF;
	280	otp->timing = 0x00001485;
	281
	282	/* Semi-random value for unique chip id. */
	283	bfin_otp_write_page_val2 (otp, FPS00, (unsigned long)otp, ~(unsigned long)otp);
	284
	285	memset (part_str, 0, sizeof (part_str));
	286	sprintf (part_str, "ADSP-BF%iX", type);
	287	switch (type)
	288	{
	289	case 512:
	290	fps03 = FPS03_BF512;
	291	break;
	292	case 514:
	293	fps03 = FPS03_BF514;
	294	break;
	295	case 516:
	296	fps03 = FPS03_BF516;
	297	break;
	298	case 518:
	299	fps03 = FPS03_BF518;
	300	break;
	301	case 522:
	302	fps03 = FPS03_BF522;
	303	break;
	304	case 523:
	305	fps03 = FPS03_BF523;
	306	break;
	307	case 524:
	308	fps03 = FPS03_BF524;
	309	break;
	310	case 525:
	311	fps03 = FPS03_BF525;
	312	break;
	313	case 526:
	314	fps03 = FPS03_BF526;
	315	break;
	316	case 527:
	317	fps03 = FPS03_BF527;
	318	break;
	319	default:
	320	fps03 = 0;
	321	break;
	322	}
	323	part_str[14] = (fps03 >> 0);
	324	part_str[15] = (fps03 >> 8);
	325	bfin_otp_write_page_val (otp, FPS03, (void *)part_str);
	326	}
	327
81d126c3 MF	328	const struct hw_descriptor dv_bfin_otp_descriptor[] =
81d126c3 MF	329	{
ef016f83 MF	330	{"bfin_otp", bfin_otp_finish,},
	331	{NULL, NULL},
	332	};