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c28c63d8 JB |
1 | /* Lattice Mico32 CPU model. |
2 | Contributed by Jon Beniston <jon@beniston.com> | |
3 | ||
3666a048 | 4 | Copyright (C) 2009-2021 Free Software Foundation, Inc. |
c28c63d8 JB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
6df01ab8 MF |
21 | /* This must come before any other includes. */ |
22 | #include "defs.h" | |
23 | ||
c28c63d8 JB |
24 | #include "hw-main.h" |
25 | #include "sim-main.h" | |
26 | ||
27 | ||
28 | struct lm32cpu | |
29 | { | |
30 | struct hw_event *event; | |
31 | }; | |
32 | ||
33 | /* input port ID's. */ | |
34 | ||
35 | enum | |
36 | { | |
37 | INT0_PORT, | |
38 | INT1_PORT, | |
39 | INT2_PORT, | |
40 | INT3_PORT, | |
41 | INT4_PORT, | |
42 | INT5_PORT, | |
43 | INT6_PORT, | |
44 | INT7_PORT, | |
45 | INT8_PORT, | |
46 | INT9_PORT, | |
47 | INT10_PORT, | |
48 | INT11_PORT, | |
49 | INT12_PORT, | |
50 | INT13_PORT, | |
51 | INT14_PORT, | |
52 | INT15_PORT, | |
53 | INT16_PORT, | |
54 | INT17_PORT, | |
55 | INT18_PORT, | |
56 | INT19_PORT, | |
57 | INT20_PORT, | |
58 | INT21_PORT, | |
59 | INT22_PORT, | |
60 | INT23_PORT, | |
61 | INT24_PORT, | |
62 | INT25_PORT, | |
63 | INT26_PORT, | |
64 | INT27_PORT, | |
65 | INT28_PORT, | |
66 | INT29_PORT, | |
67 | INT30_PORT, | |
68 | INT31_PORT, | |
69 | }; | |
70 | ||
71 | static const struct hw_port_descriptor lm32cpu_ports[] = { | |
72 | /* interrupt inputs. */ | |
73 | {"int0", INT0_PORT, 0, input_port,}, | |
74 | {"int1", INT1_PORT, 0, input_port,}, | |
75 | {"int2", INT2_PORT, 0, input_port,}, | |
76 | {"int3", INT3_PORT, 0, input_port,}, | |
77 | {"int4", INT4_PORT, 0, input_port,}, | |
78 | {"int5", INT5_PORT, 0, input_port,}, | |
79 | {"int6", INT6_PORT, 0, input_port,}, | |
80 | {"int7", INT7_PORT, 0, input_port,}, | |
81 | {"int8", INT8_PORT, 0, input_port,}, | |
82 | {"int9", INT9_PORT, 0, input_port,}, | |
83 | {"int10", INT10_PORT, 0, input_port,}, | |
84 | {"int11", INT11_PORT, 0, input_port,}, | |
85 | {"int12", INT12_PORT, 0, input_port,}, | |
86 | {"int13", INT13_PORT, 0, input_port,}, | |
87 | {"int14", INT14_PORT, 0, input_port,}, | |
88 | {"int15", INT15_PORT, 0, input_port,}, | |
89 | {"int16", INT16_PORT, 0, input_port,}, | |
90 | {"int17", INT17_PORT, 0, input_port,}, | |
91 | {"int18", INT18_PORT, 0, input_port,}, | |
92 | {"int19", INT19_PORT, 0, input_port,}, | |
93 | {"int20", INT20_PORT, 0, input_port,}, | |
94 | {"int21", INT21_PORT, 0, input_port,}, | |
95 | {"int22", INT22_PORT, 0, input_port,}, | |
96 | {"int23", INT23_PORT, 0, input_port,}, | |
97 | {"int24", INT24_PORT, 0, input_port,}, | |
98 | {"int25", INT25_PORT, 0, input_port,}, | |
99 | {"int26", INT26_PORT, 0, input_port,}, | |
100 | {"int27", INT27_PORT, 0, input_port,}, | |
101 | {"int28", INT28_PORT, 0, input_port,}, | |
102 | {"int29", INT29_PORT, 0, input_port,}, | |
103 | {"int30", INT30_PORT, 0, input_port,}, | |
104 | {"int31", INT31_PORT, 0, input_port,}, | |
105 | {NULL,}, | |
106 | }; | |
107 | ||
108 | ||
109 | ||
110 | /* | |
111 | * Finish off the partially created hw device. Attach our local | |
112 | * callbacks. Wire up our port names etc. | |
113 | */ | |
114 | static hw_port_event_method lm32cpu_port_event; | |
115 | ||
116 | ||
117 | static void | |
118 | lm32cpu_finish (struct hw *me) | |
119 | { | |
120 | struct lm32cpu *controller; | |
121 | ||
122 | controller = HW_ZALLOC (me, struct lm32cpu); | |
123 | set_hw_data (me, controller); | |
124 | set_hw_ports (me, lm32cpu_ports); | |
125 | set_hw_port_event (me, lm32cpu_port_event); | |
126 | ||
127 | /* Initialize the pending interrupt flags. */ | |
128 | controller->event = NULL; | |
129 | } | |
130 | ||
131 | ||
132 | /* An event arrives on an interrupt port. */ | |
133 | static unsigned int s_ui_ExtIntrs = 0; | |
134 | ||
135 | ||
136 | static void | |
137 | deliver_lm32cpu_interrupt (struct hw *me, void *data) | |
138 | { | |
139 | static unsigned int ip, im, im_and_ip_result; | |
140 | struct lm32cpu *controller = hw_data (me); | |
141 | SIM_DESC sd = hw_system (me); | |
142 | sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ | |
034685f9 | 143 | address_word cia = CPU_PC_GET (cpu); |
c28c63d8 JB |
144 | int interrupt = (int) data; |
145 | ||
146 | ||
147 | HW_TRACE ((me, "interrupt-check event")); | |
148 | ||
149 | ||
150 | /* | |
151 | * Determine if an external interrupt is active | |
152 | * and needs to cause an exception. | |
153 | */ | |
154 | im = lm32bf_h_csr_get (cpu, LM32_CSR_IM); | |
155 | ip = lm32bf_h_csr_get (cpu, LM32_CSR_IP); | |
156 | im_and_ip_result = im & ip; | |
157 | ||
158 | ||
159 | if ((lm32bf_h_csr_get (cpu, LM32_CSR_IE) & 1) && (im_and_ip_result != 0)) | |
160 | { | |
161 | /* Save PC in exception address register. */ | |
162 | lm32bf_h_gr_set (cpu, 30, lm32bf_h_pc_get (cpu)); | |
163 | /* Restart at interrupt offset in handler exception table. */ | |
164 | lm32bf_h_pc_set (cpu, | |
165 | lm32bf_h_csr_get (cpu, | |
166 | LM32_CSR_EBA) + | |
167 | LM32_EID_INTERRUPT * 32); | |
168 | /* Save interrupt enable and then clear. */ | |
169 | lm32bf_h_csr_set (cpu, LM32_CSR_IE, 0x2); | |
170 | } | |
171 | ||
172 | /* reschedule soon. */ | |
173 | if (controller->event != NULL) | |
174 | hw_event_queue_deschedule (me, controller->event); | |
175 | controller->event = NULL; | |
176 | ||
177 | ||
178 | /* if there are external interrupts, schedule an interrupt-check again. | |
179 | * NOTE: THIS MAKES IT VERY INEFFICIENT. INSTEAD, TRIGGER THIS | |
180 | * CHECk_EVENT WHEN THE USER ENABLES IE OR USER MODIFIES IM REGISTERS. | |
181 | */ | |
182 | if (s_ui_ExtIntrs != 0) | |
183 | controller->event = | |
184 | hw_event_queue_schedule (me, 1, deliver_lm32cpu_interrupt, data); | |
185 | } | |
186 | ||
187 | ||
188 | ||
189 | /* Handle an event on one of the CPU's ports. */ | |
190 | static void | |
191 | lm32cpu_port_event (struct hw *me, | |
192 | int my_port, | |
193 | struct hw *source, int source_port, int level) | |
194 | { | |
195 | struct lm32cpu *controller = hw_data (me); | |
196 | SIM_DESC sd = hw_system (me); | |
197 | sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ | |
034685f9 | 198 | address_word cia = CPU_PC_GET (cpu); |
c28c63d8 JB |
199 | |
200 | ||
201 | HW_TRACE ((me, "interrupt event on port %d, level %d", my_port, level)); | |
202 | ||
203 | ||
204 | ||
205 | /* | |
206 | * Activate IP if the interrupt's activated; don't do anything if | |
207 | * the interrupt's deactivated. | |
208 | */ | |
209 | if (level == 1) | |
210 | { | |
211 | /* | |
212 | * save state of external interrupt. | |
213 | */ | |
214 | s_ui_ExtIntrs |= (1 << my_port); | |
215 | ||
216 | /* interrupt-activated so set IP. */ | |
217 | lm32bf_h_csr_set (cpu, LM32_CSR_IP, | |
218 | lm32bf_h_csr_get (cpu, LM32_CSR_IP) | (1 << my_port)); | |
219 | ||
220 | /* | |
221 | * Since interrupt is activated, queue an immediate event | |
222 | * to check if this interrupt is serviceable. | |
223 | */ | |
224 | if (controller->event != NULL) | |
225 | hw_event_queue_deschedule (me, controller->event); | |
226 | ||
227 | ||
228 | /* | |
229 | * Queue an immediate event to check if this interrupt must be serviced; | |
230 | * this will happen after the current instruction is complete. | |
231 | */ | |
232 | controller->event = hw_event_queue_schedule (me, | |
233 | 0, | |
234 | deliver_lm32cpu_interrupt, | |
235 | 0); | |
236 | } | |
237 | else | |
238 | { | |
239 | /* | |
240 | * save state of external interrupt. | |
241 | */ | |
242 | s_ui_ExtIntrs &= ~(1 << my_port); | |
243 | } | |
244 | } | |
245 | ||
246 | ||
247 | const struct hw_descriptor dv_lm32cpu_descriptor[] = { | |
248 | {"lm32cpu", lm32cpu_finish,}, | |
249 | {NULL}, | |
250 | }; |