]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
sim: switch config.h usage to defs.h
authorMike Frysinger <vapier@gentoo.org>
Sat, 1 May 2021 22:05:23 +0000 (18:05 -0400)
committerMike Frysinger <vapier@gentoo.org>
Mon, 17 May 2021 02:38:41 +0000 (22:38 -0400)
commit6df01ab8ab8509b04f86d7da069ec2d25eb31bf9
tree21a00924bc74b7d5ec239a133d223f9d52f1dd67
parent681eb80f1217f66c83dec4a3db83577a2a09f74a
sim: switch config.h usage to defs.h

The defs.h header will take care of including the various config.h
headers.  For now, it's just config.h, but we'll add more when we
integrate gnulib in.

This header should be used instead of config.h, and should be the
first include in every .c file.  We won't rely on the old behavior
where we expected files to include the port's sim-main.h which then
includes the common sim-basics.h which then includes config.h.  We
have a ton of code that includes things before sim-main.h, and it
sometimes needs to be that way.  Creating a dedicated header avoids
the ordering mess and implicit inclusion that shows up otherwise.
302 files changed:
sim/aarch64/ChangeLog
sim/aarch64/cpustate.c
sim/aarch64/cpustate.h
sim/aarch64/interp.c
sim/aarch64/memory.c
sim/aarch64/simulator.c
sim/aarch64/simulator.h
sim/arm/ChangeLog
sim/arm/armcopro.c
sim/arm/armdefs.h
sim/arm/armemu.c
sim/arm/arminit.c
sim/arm/armos.c
sim/arm/armsupp.c
sim/arm/armvirt.c
sim/arm/iwmmxt.c
sim/arm/maverick.c
sim/arm/thumbemu.c
sim/arm/wrapper.c
sim/avr/ChangeLog
sim/avr/interp.c
sim/bfin/ChangeLog
sim/bfin/bfin-sim.c
sim/bfin/devices.c
sim/bfin/dv-bfin_cec.c
sim/bfin/dv-bfin_ctimer.c
sim/bfin/dv-bfin_dma.c
sim/bfin/dv-bfin_dmac.c
sim/bfin/dv-bfin_ebiu_amc.c
sim/bfin/dv-bfin_ebiu_ddrc.c
sim/bfin/dv-bfin_ebiu_sdc.c
sim/bfin/dv-bfin_emac.c
sim/bfin/dv-bfin_eppi.c
sim/bfin/dv-bfin_evt.c
sim/bfin/dv-bfin_gpio.c
sim/bfin/dv-bfin_gpio2.c
sim/bfin/dv-bfin_gptimer.c
sim/bfin/dv-bfin_jtag.c
sim/bfin/dv-bfin_mmu.c
sim/bfin/dv-bfin_nfc.c
sim/bfin/dv-bfin_otp.c
sim/bfin/dv-bfin_pfmon.c
sim/bfin/dv-bfin_pint.c
sim/bfin/dv-bfin_pll.c
sim/bfin/dv-bfin_ppi.c
sim/bfin/dv-bfin_rtc.c
sim/bfin/dv-bfin_sic.c
sim/bfin/dv-bfin_spi.c
sim/bfin/dv-bfin_trace.c
sim/bfin/dv-bfin_twi.c
sim/bfin/dv-bfin_uart.c
sim/bfin/dv-bfin_uart2.c
sim/bfin/dv-bfin_wdog.c
sim/bfin/dv-bfin_wp.c
sim/bfin/dv-eth_phy.c
sim/bfin/gui.c
sim/bfin/interp.c
sim/bfin/machs.c
sim/bpf/ChangeLog
sim/bpf/bpf-helpers.c
sim/bpf/bpf.c
sim/bpf/sim-if.c
sim/bpf/traps.c
sim/common/ChangeLog
sim/common/callback.c
sim/common/cgen-accfp.c
sim/common/cgen-fpu.c
sim/common/cgen-par.c
sim/common/cgen-run.c
sim/common/cgen-scache.c
sim/common/cgen-trace.c
sim/common/cgen-utils.c
sim/common/defs.h [new file with mode: 0644]
sim/common/dv-cfi.c
sim/common/dv-core.c
sim/common/dv-glue.c
sim/common/dv-pal.c
sim/common/dv-sockser.c
sim/common/genmloop.sh
sim/common/gentmap.c
sim/common/hw-alloc.c
sim/common/hw-base.c
sim/common/hw-device.c
sim/common/hw-events.c
sim/common/hw-handles.c
sim/common/hw-instances.c
sim/common/hw-ports.c
sim/common/hw-properties.c
sim/common/hw-tree.c
sim/common/nrun.c
sim/common/sim-abort.c
sim/common/sim-arange.c
sim/common/sim-basics.h
sim/common/sim-bits.c
sim/common/sim-close.c
sim/common/sim-command.c
sim/common/sim-config.c
sim/common/sim-core.c
sim/common/sim-cpu.c
sim/common/sim-endian.c
sim/common/sim-engine.c
sim/common/sim-events.c
sim/common/sim-fpu.c
sim/common/sim-hload.c
sim/common/sim-hrw.c
sim/common/sim-hw.c
sim/common/sim-info.c
sim/common/sim-inline.c
sim/common/sim-io.c
sim/common/sim-load.c
sim/common/sim-memopt.c
sim/common/sim-model.c
sim/common/sim-module.c
sim/common/sim-options.c
sim/common/sim-profile.c
sim/common/sim-reason.c
sim/common/sim-reg.c
sim/common/sim-resume.c
sim/common/sim-run.c
sim/common/sim-signal.c
sim/common/sim-stop.c
sim/common/sim-syscall.c
sim/common/sim-trace.c
sim/common/sim-utils.c
sim/common/sim-watch.c
sim/common/syscall.c
sim/cr16/ChangeLog
sim/cr16/cr16_sim.h
sim/cr16/gencode.c
sim/cr16/interp.c
sim/cr16/simops.c
sim/cris/ChangeLog
sim/cris/cris-tmpl.c
sim/cris/crisv10f.c
sim/cris/crisv32f.c
sim/cris/dv-cris.c
sim/cris/dv-cris_900000xx.c
sim/cris/dv-rv.c
sim/cris/rvdummy.c
sim/cris/sim-if.c
sim/cris/traps.c
sim/d10v/ChangeLog
sim/d10v/d10v_sim.h
sim/d10v/endian.c
sim/d10v/gencode.c
sim/d10v/interp.c
sim/d10v/simops.c
sim/erc32/ChangeLog
sim/erc32/erc32.c
sim/erc32/exec.c
sim/erc32/float.c
sim/erc32/func.c
sim/erc32/help.c
sim/erc32/interf.c
sim/erc32/sis.c
sim/erc32/sis.h
sim/example-synacor/ChangeLog
sim/example-synacor/interp.c
sim/example-synacor/sim-main.c
sim/frv/ChangeLog
sim/frv/cache.c
sim/frv/frv.c
sim/frv/interrupts.c
sim/frv/memory.c
sim/frv/options.c
sim/frv/pipeline.c
sim/frv/profile-fr400.c
sim/frv/profile-fr450.c
sim/frv/profile-fr500.c
sim/frv/profile-fr550.c
sim/frv/profile.c
sim/frv/registers.c
sim/frv/reset.c
sim/frv/sim-if.c
sim/frv/sim-main.h
sim/frv/traps.c
sim/ft32/ChangeLog
sim/ft32/interp.c
sim/h8300/ChangeLog
sim/h8300/compile.c
sim/h8300/sim-main.h
sim/iq2000/ChangeLog
sim/iq2000/iq2000.c
sim/iq2000/sim-if.c
sim/iq2000/sim-main.h
sim/lm32/ChangeLog
sim/lm32/dv-lm32cpu.c
sim/lm32/dv-lm32timer.c
sim/lm32/dv-lm32uart.c
sim/lm32/lm32.c
sim/lm32/sim-if.c
sim/lm32/traps.c
sim/lm32/user.c
sim/m32c/ChangeLog
sim/m32c/gdb-if.c
sim/m32c/int.c
sim/m32c/load.c
sim/m32c/main.c
sim/m32c/mem.c
sim/m32c/misc.c
sim/m32c/opc2c.c
sim/m32c/reg.c
sim/m32c/srcdest.c
sim/m32c/syscalls.c
sim/m32c/trace.c
sim/m32r/ChangeLog
sim/m32r/dv-m32r_cache.c
sim/m32r/dv-m32r_uart.c
sim/m32r/m32r.c
sim/m32r/m32r2.c
sim/m32r/m32rx.c
sim/m32r/sim-if.c
sim/m32r/traps-linux.c
sim/m32r/traps.c
sim/m68hc11/ChangeLog
sim/m68hc11/dv-m68hc11.c
sim/m68hc11/dv-m68hc11eepr.c
sim/m68hc11/dv-m68hc11sio.c
sim/m68hc11/dv-m68hc11spi.c
sim/m68hc11/dv-m68hc11tim.c
sim/m68hc11/dv-nvram.c
sim/m68hc11/emulos.c
sim/m68hc11/gencode.c
sim/m68hc11/interp.c
sim/m68hc11/interrupts.c
sim/m68hc11/m68hc11_sim.c
sim/mcore/ChangeLog
sim/mcore/interp.c
sim/microblaze/ChangeLog
sim/microblaze/interp.c
sim/mips/ChangeLog
sim/mips/cp1.c
sim/mips/dsp.c
sim/mips/dv-tx3904cpu.c
sim/mips/dv-tx3904irc.c
sim/mips/dv-tx3904sio.c
sim/mips/dv-tx3904tmr.c
sim/mips/interp.c
sim/mips/m16run.c
sim/mips/mdmx.c
sim/mips/micromipsrun.c
sim/mips/sim-main.c
sim/mn10300/ChangeLog
sim/mn10300/dv-mn103cpu.c
sim/mn10300/dv-mn103int.c
sim/mn10300/dv-mn103iop.c
sim/mn10300/dv-mn103ser.c
sim/mn10300/dv-mn103tim.c
sim/mn10300/interp.c
sim/mn10300/op_utils.c
sim/moxie/ChangeLog
sim/moxie/interp.c
sim/msp430/ChangeLog
sim/msp430/msp430-sim.c
sim/or1k/ChangeLog
sim/or1k/or1k.c
sim/or1k/sim-if.c
sim/or1k/sim-main.h
sim/or1k/traps.c
sim/ppc/ChangeLog
sim/ppc/Makefile.in
sim/ppc/basics.h
sim/ppc/debug.c
sim/ppc/defs.h [new file with mode: 0644]
sim/ppc/filter_filename.c
sim/ppc/inline.c
sim/ppc/sim-endian.c
sim/ppc/words.h
sim/pru/ChangeLog
sim/pru/interp.c
sim/pru/pru.h
sim/pru/sim-main.h
sim/riscv/ChangeLog
sim/riscv/interp.c
sim/riscv/machs.c
sim/riscv/sim-main.c
sim/rl78/ChangeLog
sim/rl78/cpu.c
sim/rl78/gdb-if.c
sim/rl78/load.c
sim/rl78/main.c
sim/rl78/mem.c
sim/rl78/rl78.c
sim/rl78/trace.c
sim/rx/ChangeLog
sim/rx/err.c
sim/rx/fpu.c
sim/rx/gdb-if.c
sim/rx/load.c
sim/rx/main.c
sim/rx/mem.c
sim/rx/misc.c
sim/rx/reg.c
sim/rx/rx.c
sim/rx/syscalls.c
sim/rx/trace.c
sim/sh/ChangeLog
sim/sh/interp.c
sim/v850/ChangeLog
sim/v850/interp.c
sim/v850/sim-main.h
sim/v850/simops.c