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81e09ed8 | 1 | /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12 |
4a94e368 | 2 | Copyright (C) 1999-2022 Free Software Foundation, Inc. |
63f36def | 3 | Written by Stephane Carrez (stcarrez@nerim.fr) |
e0709f50 AC |
4 | |
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
e0709f50 AC |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
e0709f50 AC |
19 | |
20 | #ifndef _SIM_MAIN_H | |
21 | #define _SIM_MAIN_H | |
22 | ||
e0709f50 | 23 | #include "sim-basics.h" |
e0709f50 AC |
24 | #include "sim-base.h" |
25 | ||
e0709f50 AC |
26 | #include "opcode/m68hc11.h" |
27 | ||
df68e12b | 28 | #include "sim/sim.h" |
e0709f50 | 29 | #include "opcode/m68hc11.h" |
1fef66b0 | 30 | #include "sim-signal.h" |
e0709f50 AC |
31 | #include "sim-types.h" |
32 | ||
e0709f50 AC |
33 | #include "interrupts.h" |
34 | #include <setjmp.h> | |
35 | ||
63348d04 SC |
36 | /* Specifies the level of mapping for the IO, EEprom, nvram and external |
37 | RAM. IO registers are mapped over everything and the external RAM | |
38 | is last (ie, it can be hidden by everything above it in the list). */ | |
39 | enum m68hc11_map_level | |
40 | { | |
41 | M6811_IO_LEVEL, | |
42 | M6811_EEPROM_LEVEL, | |
43 | M6811_NVRAM_LEVEL, | |
44 | M6811_RAM_LEVEL | |
45 | }; | |
46 | ||
81e09ed8 SC |
47 | enum cpu_type |
48 | { | |
49 | CPU_M6811, | |
50 | CPU_M6812 | |
51 | }; | |
63348d04 | 52 | |
e0709f50 AC |
53 | #define X_REGNUM 0 |
54 | #define D_REGNUM 1 | |
55 | #define Y_REGNUM 2 | |
56 | #define SP_REGNUM 3 | |
57 | #define PC_REGNUM 4 | |
58 | #define A_REGNUM 5 | |
59 | #define B_REGNUM 6 | |
60 | #define PSW_REGNUM 7 | |
53b3cd22 SC |
61 | #define PAGE_REGNUM 8 |
62 | #define Z_REGNUM 9 | |
e0709f50 AC |
63 | |
64 | typedef struct m6811_regs { | |
65 | unsigned short d; | |
66 | unsigned short ix; | |
67 | unsigned short iy; | |
68 | unsigned short sp; | |
69 | unsigned short pc; | |
70 | unsigned char ccr; | |
63f36def | 71 | unsigned short page; |
e0709f50 AC |
72 | } m6811_regs; |
73 | ||
74 | ||
75 | /* Description of 68HC11 IO registers. Such description is only provided | |
76 | for the info command to display the current setting of IO registers | |
77 | from GDB. */ | |
78 | struct io_reg_desc | |
79 | { | |
80 | int mask; | |
81 | const char *short_name; | |
82 | const char *long_name; | |
83 | }; | |
84 | typedef struct io_reg_desc io_reg_desc; | |
85 | ||
86 | extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val, | |
87 | int mode); | |
88 | extern void print_io_byte (SIM_DESC sd, const char *name, | |
7606e1a3 | 89 | io_reg_desc *desc, uint8_t val, uint16_t addr); |
962e9d85 | 90 | extern void print_io_word (SIM_DESC sd, const char *name, |
7606e1a3 | 91 | io_reg_desc *desc, uint16_t val, uint16_t addr); |
e0709f50 AC |
92 | |
93 | ||
81e09ed8 | 94 | /* List of special 68HC11&68HC12 instructions that are not handled by the |
e0709f50 AC |
95 | 'gencode.c' generator. These complex instructions are implemented |
96 | by 'cpu_special'. */ | |
97 | enum M6811_Special | |
98 | { | |
81e09ed8 SC |
99 | /* 68HC11 instructions. */ |
100 | M6811_DAA, | |
101 | M6811_EMUL_SYSCALL, | |
102 | M6811_ILLEGAL, | |
e0709f50 | 103 | M6811_RTI, |
81e09ed8 | 104 | M6811_STOP, |
e0709f50 AC |
105 | M6811_SWI, |
106 | M6811_TEST, | |
81e09ed8 SC |
107 | M6811_WAI, |
108 | ||
109 | /* 68HC12 instructions. */ | |
110 | M6812_BGND, | |
111 | M6812_CALL, | |
63f36def | 112 | M6812_CALL_INDIRECT, |
81e09ed8 SC |
113 | M6812_IDIVS, |
114 | M6812_EDIV, | |
115 | M6812_EDIVS, | |
116 | M6812_EMACS, | |
117 | M6812_EMUL, | |
118 | M6812_EMULS, | |
119 | M6812_ETBL, | |
120 | M6812_MEM, | |
121 | M6812_REV, | |
122 | M6812_REVW, | |
123 | M6812_RTC, | |
124 | M6812_RTI, | |
125 | M6812_WAV | |
e0709f50 AC |
126 | }; |
127 | ||
81e09ed8 SC |
128 | #define M6811_MAX_PORTS (0x03f+1) |
129 | #define M6812_MAX_PORTS (0x3ff+1) | |
130 | #define MAX_PORTS (M6812_MAX_PORTS) | |
e0709f50 | 131 | |
79d784ae | 132 | typedef void (* cpu_interp) (sim_cpu *); |
81e09ed8 | 133 | |
79d784ae | 134 | struct m68hc11_sim_cpu { |
e0709f50 AC |
135 | /* CPU registers. */ |
136 | struct m6811_regs cpu_regs; | |
137 | ||
138 | /* CPU interrupts. */ | |
139 | struct interrupts cpu_interrupts; | |
140 | ||
81e09ed8 SC |
141 | /* Pointer to the interpretor routine. */ |
142 | cpu_interp cpu_interpretor; | |
143 | ||
144 | /* Pointer to the architecture currently configured in the simulator. */ | |
145 | const struct bfd_arch_info *cpu_configured_arch; | |
146 | ||
e0709f50 AC |
147 | /* CPU absolute cycle time. The cycle time is updated after |
148 | each instruction, by the number of cycles taken by the instruction. | |
149 | It is cleared only when reset occurs. */ | |
7606e1a3 | 150 | int64_t cpu_absolute_cycle; |
e0709f50 AC |
151 | |
152 | /* Number of cycles to increment after the current instruction. | |
153 | This is also the number of ticks for the generic event scheduler. */ | |
7606e1a3 | 154 | uint8_t cpu_current_cycle; |
e0709f50 AC |
155 | int cpu_emul_syscall; |
156 | int cpu_is_initialized; | |
157 | int cpu_running; | |
158 | int cpu_check_memory; | |
159 | int cpu_stop_on_interrupt; | |
160 | ||
161 | /* When this is set, start execution of program at address specified | |
162 | in the ELF header. This is used for testing some programs that do not | |
163 | have an interrupt table linked with them. Programs created during the | |
164 | GCC validation are like this. A normal 68HC11 does not behave like | |
165 | this (unless there is some OS or downloadable feature). */ | |
166 | int cpu_use_elf_start; | |
167 | ||
168 | /* The starting address specified in ELF header. */ | |
169 | int cpu_elf_start; | |
170 | ||
7606e1a3 | 171 | uint16_t cpu_insn_pc; |
e0709f50 AC |
172 | |
173 | /* CPU frequency. This is the quartz frequency. It is divided by 4 to | |
174 | get the cycle time. This is used for the timer rate and for the baud | |
175 | rate generation. */ | |
176 | unsigned long cpu_frequency; | |
177 | ||
178 | /* The mode in which the CPU is configured (MODA and MODB pins). */ | |
179 | unsigned int cpu_mode; | |
a685700c | 180 | const char* cpu_start_mode; |
e0709f50 | 181 | |
81e09ed8 SC |
182 | /* The cpu being configured. */ |
183 | enum cpu_type cpu_type; | |
184 | ||
e0709f50 | 185 | /* Initial value of the CONFIG register. */ |
7606e1a3 MF |
186 | uint8_t cpu_config; |
187 | uint8_t cpu_use_local_config; | |
e0709f50 | 188 | |
7606e1a3 | 189 | uint8_t ios[MAX_PORTS]; |
827ec39a | 190 | |
77342e5e SC |
191 | /* Memory bank parameters which describe how the memory bank window |
192 | is mapped in memory and how to convert it in virtual address. */ | |
7606e1a3 MF |
193 | uint16_t bank_start; |
194 | uint16_t bank_end; | |
77342e5e SC |
195 | address_word bank_virtual; |
196 | unsigned bank_shift; | |
197 | ||
198 | ||
827ec39a | 199 | struct hw *hw_cpu; |
e0709f50 | 200 | }; |
79d784ae | 201 | #define M68HC11_SIM_CPU(cpu) ((struct m68hc11_sim_cpu *) CPU_ARCH_DATA (cpu)) |
e0709f50 AC |
202 | |
203 | /* Returns the cpu absolute cycle time (A virtual counter incremented | |
204 | at each 68HC11 E clock). */ | |
79d784ae MF |
205 | #define cpu_current_cycle(cpu) (M68HC11_SIM_CPU (cpu)->cpu_absolute_cycle) |
206 | #define cpu_add_cycles(cpu, T) (M68HC11_SIM_CPU (cpu)->cpu_current_cycle += (int64_t) (T)) | |
207 | #define cpu_is_running(cpu) (M68HC11_SIM_CPU (cpu)->cpu_running) | |
e0709f50 AC |
208 | |
209 | /* Get the IO/RAM base addresses depending on the M6811_INIT register. */ | |
6f64fd48 | 210 | #define cpu_get_io_base(cpu) \ |
79d784ae | 211 | (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0x0F)) << 12) |
6f64fd48 | 212 | #define cpu_get_reg_base(cpu) \ |
79d784ae | 213 | (((uint16_t)((M68HC11_SIM_CPU (cpu)->ios[M6811_INIT]) & 0xF0)) << 8) |
e0709f50 AC |
214 | |
215 | /* Returns the different CPU registers. */ | |
79d784ae MF |
216 | #define cpu_get_ccr(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr) |
217 | #define cpu_get_pc(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.pc) | |
218 | #define cpu_get_d(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.d) | |
219 | #define cpu_get_x(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.ix) | |
220 | #define cpu_get_y(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.iy) | |
221 | #define cpu_get_sp(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.sp) | |
222 | #define cpu_get_a(cpu) ((M68HC11_SIM_CPU (cpu)->cpu_regs.d >> 8) & 0x0FF) | |
223 | #define cpu_get_b(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.d & 0x0FF) | |
224 | #define cpu_get_page(cpu) (M68HC11_SIM_CPU (cpu)->cpu_regs.page) | |
e0709f50 | 225 | |
81e09ed8 | 226 | /* 68HC12 specific and Motorola internal registers. */ |
6f64fd48 MF |
227 | #define cpu_get_tmp3(cpu) (0) |
228 | #define cpu_get_tmp2(cpu) (0) | |
81e09ed8 | 229 | |
79d784ae MF |
230 | #define cpu_set_d(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.d = (val)) |
231 | #define cpu_set_x(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.ix = (val)) | |
232 | #define cpu_set_y(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.iy = (val)) | |
233 | #define cpu_set_page(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.page = (val)) | |
e0709f50 | 234 | |
81e09ed8 | 235 | /* 68HC12 specific and Motorola internal registers. */ |
6f64fd48 MF |
236 | #define cpu_set_tmp3(cpu, val) (0) |
237 | #define cpu_set_tmp2(cpu, val) (void) (0) | |
81e09ed8 | 238 | |
e0709f50 AC |
239 | #if 0 |
240 | /* This is a function in m68hc11_sim.c to keep track of the frame. */ | |
79d784ae | 241 | #define cpu_set_sp(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.sp = (val)) |
e0709f50 AC |
242 | #endif |
243 | ||
79d784ae | 244 | #define cpu_set_pc(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.pc = (val)) |
6f64fd48 MF |
245 | |
246 | #define cpu_set_a(cpu, val) \ | |
247 | cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu)) | |
248 | #define cpu_set_b(cpu, val) \ | |
249 | cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF)) | |
250 | ||
79d784ae | 251 | #define cpu_set_ccr(cpu, val) (M68HC11_SIM_CPU (cpu)->cpu_regs.ccr = (val)) |
6f64fd48 MF |
252 | #define cpu_get_ccr_H(cpu) ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0) |
253 | #define cpu_get_ccr_X(cpu) ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0) | |
254 | #define cpu_get_ccr_S(cpu) ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0) | |
255 | #define cpu_get_ccr_N(cpu) ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0) | |
256 | #define cpu_get_ccr_V(cpu) ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0) | |
257 | #define cpu_get_ccr_C(cpu) ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0) | |
258 | #define cpu_get_ccr_Z(cpu) ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0) | |
259 | #define cpu_get_ccr_I(cpu) ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0) | |
260 | ||
261 | #define cpu_set_ccr_flag(S, B, V) \ | |
262 | cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0)) | |
263 | ||
264 | #define cpu_set_ccr_H(cpu, val) cpu_set_ccr_flag (cpu, M6811_H_BIT, val) | |
265 | #define cpu_set_ccr_X(cpu, val) cpu_set_ccr_flag (cpu, M6811_X_BIT, val) | |
266 | #define cpu_set_ccr_S(cpu, val) cpu_set_ccr_flag (cpu, M6811_S_BIT, val) | |
267 | #define cpu_set_ccr_N(cpu, val) cpu_set_ccr_flag (cpu, M6811_N_BIT, val) | |
268 | #define cpu_set_ccr_V(cpu, val) cpu_set_ccr_flag (cpu, M6811_V_BIT, val) | |
269 | #define cpu_set_ccr_C(cpu, val) cpu_set_ccr_flag (cpu, M6811_C_BIT, val) | |
270 | #define cpu_set_ccr_Z(cpu, val) cpu_set_ccr_flag (cpu, M6811_Z_BIT, val) | |
271 | #define cpu_set_ccr_I(cpu, val) cpu_set_ccr_flag (cpu, M6811_I_BIT, val) | |
e0709f50 | 272 | |
6f64fd48 | 273 | extern void cpu_memory_exception (sim_cpu *cpu, |
e0709f50 | 274 | SIM_SIGNAL excep, |
7606e1a3 | 275 | uint16_t addr, |
e0709f50 AC |
276 | const char *message); |
277 | ||
4ca8baee | 278 | STATIC_INLINE UNUSED address_word |
63f36def SC |
279 | phys_to_virt (sim_cpu *cpu, address_word addr) |
280 | { | |
79d784ae MF |
281 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
282 | ||
283 | if (addr >= m68hc11_cpu->bank_start && addr < m68hc11_cpu->bank_end) | |
284 | return ((address_word) (addr - m68hc11_cpu->bank_start) | |
285 | + (((address_word) m68hc11_cpu->cpu_regs.page) << m68hc11_cpu->bank_shift) | |
286 | + m68hc11_cpu->bank_virtual); | |
63f36def SC |
287 | else |
288 | return (address_word) (addr); | |
289 | } | |
290 | ||
7606e1a3 MF |
291 | STATIC_INLINE UNUSED uint8_t |
292 | memory_read8 (sim_cpu *cpu, uint16_t addr) | |
e0709f50 | 293 | { |
7606e1a3 | 294 | uint8_t val; |
63f36def | 295 | |
e0709f50 AC |
296 | if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1) |
297 | { | |
298 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
299 | "Read error"); | |
300 | } | |
301 | return val; | |
302 | } | |
303 | ||
4ca8baee | 304 | STATIC_INLINE UNUSED void |
7606e1a3 | 305 | memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val) |
e0709f50 AC |
306 | { |
307 | if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1) | |
308 | { | |
309 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
310 | "Write error"); | |
311 | } | |
312 | } | |
313 | ||
7606e1a3 MF |
314 | STATIC_INLINE UNUSED uint16_t |
315 | memory_read16 (sim_cpu *cpu, uint16_t addr) | |
e0709f50 | 316 | { |
7606e1a3 | 317 | uint8_t b[2]; |
63f36def | 318 | |
e0709f50 AC |
319 | if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2) |
320 | { | |
321 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
322 | "Read error"); | |
323 | } | |
7606e1a3 | 324 | return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]); |
e0709f50 AC |
325 | } |
326 | ||
4ca8baee | 327 | STATIC_INLINE UNUSED void |
7606e1a3 | 328 | memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val) |
e0709f50 | 329 | { |
7606e1a3 | 330 | uint8_t b[2]; |
e0709f50 AC |
331 | |
332 | b[0] = val >> 8; | |
333 | b[1] = val; | |
334 | if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2) | |
335 | { | |
336 | cpu_memory_exception (cpu, SIM_SIGSEGV, addr, | |
337 | "Write error"); | |
338 | } | |
339 | } | |
340 | extern void | |
7606e1a3 | 341 | cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val); |
e0709f50 | 342 | |
4ca8baee | 343 | STATIC_INLINE UNUSED void |
7606e1a3 | 344 | cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val) |
e0709f50 | 345 | { |
6f64fd48 MF |
346 | cpu_set_ccr_V (cpu, 0); |
347 | cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0); | |
348 | cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0); | |
e0709f50 AC |
349 | } |
350 | ||
4ca8baee | 351 | STATIC_INLINE UNUSED void |
7606e1a3 | 352 | cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val) |
e0709f50 | 353 | { |
6f64fd48 MF |
354 | cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0); |
355 | cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0); | |
356 | cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu)); | |
e0709f50 AC |
357 | } |
358 | ||
4ca8baee | 359 | STATIC_INLINE UNUSED void |
7606e1a3 | 360 | cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val) |
e0709f50 | 361 | { |
6f64fd48 MF |
362 | cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0); |
363 | cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0); | |
364 | cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu)); | |
e0709f50 AC |
365 | } |
366 | ||
4ca8baee | 367 | STATIC_INLINE UNUSED void |
7606e1a3 | 368 | cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b) |
e0709f50 | 369 | { |
6f64fd48 MF |
370 | cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0); |
371 | cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0); | |
372 | cpu_set_ccr_Z (cpu, r == 0); | |
373 | cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0); | |
e0709f50 AC |
374 | } |
375 | ||
376 | ||
4ca8baee | 377 | STATIC_INLINE UNUSED void |
7606e1a3 | 378 | cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b) |
e0709f50 | 379 | { |
6f64fd48 MF |
380 | cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0); |
381 | cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0); | |
382 | cpu_set_ccr_Z (cpu, r == 0); | |
383 | cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0); | |
e0709f50 AC |
384 | } |
385 | ||
4ca8baee | 386 | STATIC_INLINE UNUSED void |
7606e1a3 | 387 | cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b) |
e0709f50 | 388 | { |
6f64fd48 MF |
389 | cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0); |
390 | cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0); | |
391 | cpu_set_ccr_Z (cpu, r == 0); | |
392 | cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0); | |
e0709f50 AC |
393 | } |
394 | ||
4ca8baee | 395 | STATIC_INLINE UNUSED void |
7606e1a3 | 396 | cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b) |
e0709f50 | 397 | { |
6f64fd48 MF |
398 | cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0); |
399 | cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0); | |
400 | cpu_set_ccr_Z (cpu, r == 0); | |
401 | cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0); | |
e0709f50 AC |
402 | } |
403 | ||
81e09ed8 | 404 | /* Push and pop instructions for 68HC11 (next-available stack mode). */ |
4ca8baee | 405 | STATIC_INLINE UNUSED void |
7606e1a3 | 406 | cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val) |
e0709f50 | 407 | { |
79d784ae MF |
408 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
409 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
e0709f50 | 410 | |
6f64fd48 | 411 | memory_write8 (cpu, addr, val); |
79d784ae | 412 | m68hc11_cpu->cpu_regs.sp = addr - 1; |
e0709f50 AC |
413 | } |
414 | ||
4ca8baee | 415 | STATIC_INLINE UNUSED void |
7606e1a3 | 416 | cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val) |
e0709f50 | 417 | { |
79d784ae MF |
418 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
419 | uint16_t addr = m68hc11_cpu->cpu_regs.sp - 1; | |
e0709f50 | 420 | |
6f64fd48 | 421 | memory_write16 (cpu, addr, val); |
79d784ae | 422 | m68hc11_cpu->cpu_regs.sp = addr - 1; |
e0709f50 AC |
423 | } |
424 | ||
7606e1a3 | 425 | STATIC_INLINE UNUSED uint8_t |
6f64fd48 | 426 | cpu_m68hc11_pop_uint8 (sim_cpu *cpu) |
e0709f50 | 427 | { |
79d784ae MF |
428 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
429 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
7606e1a3 | 430 | uint8_t val; |
e0709f50 | 431 | |
6f64fd48 | 432 | val = memory_read8 (cpu, addr + 1); |
79d784ae | 433 | m68hc11_cpu->cpu_regs.sp = addr + 1; |
e0709f50 AC |
434 | return val; |
435 | } | |
436 | ||
7606e1a3 | 437 | STATIC_INLINE UNUSED uint16_t |
6f64fd48 | 438 | cpu_m68hc11_pop_uint16 (sim_cpu *cpu) |
e0709f50 | 439 | { |
79d784ae MF |
440 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
441 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
7606e1a3 | 442 | uint16_t val; |
e0709f50 | 443 | |
6f64fd48 | 444 | val = memory_read16 (cpu, addr + 1); |
79d784ae | 445 | m68hc11_cpu->cpu_regs.sp = addr + 2; |
e0709f50 AC |
446 | return val; |
447 | } | |
448 | ||
81e09ed8 | 449 | /* Push and pop instructions for 68HC12 (last-used stack mode). */ |
4ca8baee | 450 | STATIC_INLINE UNUSED void |
7606e1a3 | 451 | cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val) |
81e09ed8 | 452 | { |
79d784ae MF |
453 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
454 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
81e09ed8 SC |
455 | |
456 | addr --; | |
6f64fd48 | 457 | memory_write8 (cpu, addr, val); |
79d784ae | 458 | m68hc11_cpu->cpu_regs.sp = addr; |
81e09ed8 SC |
459 | } |
460 | ||
4ca8baee | 461 | STATIC_INLINE UNUSED void |
7606e1a3 | 462 | cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val) |
81e09ed8 | 463 | { |
79d784ae MF |
464 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
465 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
81e09ed8 SC |
466 | |
467 | addr -= 2; | |
6f64fd48 | 468 | memory_write16 (cpu, addr, val); |
79d784ae | 469 | m68hc11_cpu->cpu_regs.sp = addr; |
81e09ed8 SC |
470 | } |
471 | ||
7606e1a3 | 472 | STATIC_INLINE UNUSED uint8_t |
6f64fd48 | 473 | cpu_m68hc12_pop_uint8 (sim_cpu *cpu) |
81e09ed8 | 474 | { |
79d784ae MF |
475 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
476 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
7606e1a3 | 477 | uint8_t val; |
81e09ed8 | 478 | |
6f64fd48 | 479 | val = memory_read8 (cpu, addr); |
79d784ae | 480 | m68hc11_cpu->cpu_regs.sp = addr + 1; |
81e09ed8 SC |
481 | return val; |
482 | } | |
483 | ||
7606e1a3 | 484 | STATIC_INLINE UNUSED uint16_t |
6f64fd48 | 485 | cpu_m68hc12_pop_uint16 (sim_cpu *cpu) |
81e09ed8 | 486 | { |
79d784ae MF |
487 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
488 | uint16_t addr = m68hc11_cpu->cpu_regs.sp; | |
7606e1a3 | 489 | uint16_t val; |
81e09ed8 | 490 | |
6f64fd48 | 491 | val = memory_read16 (cpu, addr); |
79d784ae | 492 | m68hc11_cpu->cpu_regs.sp = addr + 2; |
81e09ed8 SC |
493 | return val; |
494 | } | |
495 | ||
496 | /* Fetch a 8/16 bit value and update the PC. */ | |
7606e1a3 | 497 | STATIC_INLINE UNUSED uint8_t |
6f64fd48 | 498 | cpu_fetch8 (sim_cpu *cpu) |
e0709f50 | 499 | { |
79d784ae MF |
500 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
501 | uint16_t addr = m68hc11_cpu->cpu_regs.pc; | |
7606e1a3 | 502 | uint8_t val; |
e0709f50 | 503 | |
6f64fd48 | 504 | val = memory_read8 (cpu, addr); |
79d784ae | 505 | m68hc11_cpu->cpu_regs.pc = addr + 1; |
e0709f50 AC |
506 | return val; |
507 | } | |
508 | ||
7606e1a3 | 509 | STATIC_INLINE UNUSED uint16_t |
6f64fd48 | 510 | cpu_fetch16 (sim_cpu *cpu) |
e0709f50 | 511 | { |
79d784ae MF |
512 | struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu); |
513 | uint16_t addr = m68hc11_cpu->cpu_regs.pc; | |
7606e1a3 | 514 | uint16_t val; |
e0709f50 | 515 | |
6f64fd48 | 516 | val = memory_read16 (cpu, addr); |
79d784ae | 517 | m68hc11_cpu->cpu_regs.pc = addr + 2; |
e0709f50 AC |
518 | return val; |
519 | } | |
520 | ||
7606e1a3 MF |
521 | extern void cpu_call (sim_cpu *cpu, uint16_t addr); |
522 | extern void cpu_exg (sim_cpu *cpu, uint8_t code); | |
6f64fd48 MF |
523 | extern void cpu_dbcc (sim_cpu *cpu); |
524 | extern void cpu_special (sim_cpu *cpu, enum M6811_Special special); | |
7606e1a3 MF |
525 | extern void cpu_move8 (sim_cpu *cpu, uint8_t op); |
526 | extern void cpu_move16 (sim_cpu *cpu, uint8_t op); | |
e0709f50 | 527 | |
7606e1a3 MF |
528 | extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu); |
529 | extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu); | |
6f64fd48 MF |
530 | extern void cpu_push_all (sim_cpu *cpu); |
531 | extern void cpu_single_step (sim_cpu *cpu); | |
e0709f50 | 532 | |
6f64fd48 | 533 | extern void cpu_info (SIM_DESC sd, sim_cpu *cpu); |
e0709f50 AC |
534 | |
535 | extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu); | |
536 | ||
63f36def SC |
537 | /* Returns the address of a 68HC12 indexed operand. |
538 | Pre and post modifications are handled on the source register. */ | |
7606e1a3 | 539 | extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted); |
63f36def SC |
540 | |
541 | extern void cpu_return (sim_cpu *cpu); | |
7606e1a3 | 542 | extern void cpu_set_sp (sim_cpu *cpu, uint16_t val); |
e0709f50 AC |
543 | extern int cpu_reset (sim_cpu *cpu); |
544 | extern int cpu_restart (sim_cpu *cpu); | |
545 | extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep, | |
7f9495b2 TO |
546 | uint16_t addr, const char *message, ...) |
547 | ATTRIBUTE_PRINTF (4, 5); | |
e0709f50 | 548 | extern void emul_os (int op, sim_cpu *cpu); |
81e09ed8 SC |
549 | extern void cpu_interp_m6811 (sim_cpu *cpu); |
550 | extern void cpu_interp_m6812 (sim_cpu *cpu); | |
e0709f50 | 551 | |
827ec39a SC |
552 | extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port, |
553 | double ton, double toff, | |
7606e1a3 | 554 | int64_t repeat); |
827ec39a SC |
555 | extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port); |
556 | extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu, | |
7606e1a3 | 557 | unsigned addr, uint8_t val); |
827ec39a | 558 | |
e0709f50 AC |
559 | extern void sim_board_reset (SIM_DESC sd); |
560 | ||
a685700c SC |
561 | #define PRINT_TIME 0x01 |
562 | #define PRINT_CYCLE 0x02 | |
7606e1a3 | 563 | extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags); |
2990a9f4 | 564 | |
e0709f50 AC |
565 | #endif |
566 | ||
567 |