[thirdparty/binutils-gdb.git] / sim / m68hc11 / sim-main.h

/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
   Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   Written by Stephane Carrez (stcarrez@nerim.fr)

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef _SIM_MAIN_H
#define _SIM_MAIN_H

#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1
#define SIM_HANDLES_LMA 1

#include "sim-basics.h"

typedef address_word sim_cia;

#include "sim-signal.h"
#include "sim-base.h"

#include "bfd.h"

#include "opcode/m68hc11.h"

#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "opcode/m68hc11.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

struct _sim_cpu;

#include "interrupts.h"
#include <setjmp.h>

/* Specifies the level of mapping for the IO, EEprom, nvram and external
   RAM.  IO registers are mapped over everything and the external RAM
   is last (ie, it can be hidden by everything above it in the list).  */
enum m68hc11_map_level
{
  M6811_IO_LEVEL,
  M6811_EEPROM_LEVEL,
  M6811_NVRAM_LEVEL,
  M6811_RAM_LEVEL
};

enum cpu_type
{
  CPU_M6811,
  CPU_M6812
};

#define X_REGNUM 	0
#define D_REGNUM	1
#define Y_REGNUM        2
#define SP_REGNUM 	3
#define PC_REGNUM 	4
#define A_REGNUM        5
#define B_REGNUM        6
#define PSW_REGNUM 	7
#define Z_REGNUM        8
#define PAGE_REGNUM     9

typedef struct m6811_regs {
    unsigned short      d;
    unsigned short      ix;
    unsigned short      iy;
    unsigned short      sp;
    unsigned short      pc;
    unsigned char       ccr;
  unsigned short      page;
} m6811_regs;


/* Description of 68HC11 IO registers.  Such description is only provided
   for the info command to display the current setting of IO registers
   from GDB.  */
struct io_reg_desc
{
  int        mask;
  const char *short_name;
  const char *long_name;
};
typedef struct io_reg_desc io_reg_desc;

extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
			       int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
			   io_reg_desc *desc, uint8 val, uint16 addr);


/* List of special 68HC11&68HC12 instructions that are not handled by the
   'gencode.c' generator.  These complex instructions are implemented
   by 'cpu_special'.  */
enum M6811_Special
{
  /* 68HC11 instructions.  */
  M6811_DAA,
  M6811_EMUL_SYSCALL,
  M6811_ILLEGAL,
  M6811_RTI,
  M6811_STOP,
  M6811_SWI,
  M6811_TEST,
  M6811_WAI,

  /* 68HC12 instructions.  */
  M6812_BGND,
  M6812_CALL,
  M6812_CALL_INDIRECT,
  M6812_IDIVS,
  M6812_EDIV,
  M6812_EDIVS,
  M6812_EMACS,
  M6812_EMUL,
  M6812_EMULS,
  M6812_ETBL,
  M6812_MEM,
  M6812_REV,
  M6812_REVW,
  M6812_RTC,
  M6812_RTI,
  M6812_WAV
};

#define M6811_MAX_PORTS (0x03f+1)
#define M6812_MAX_PORTS (0x3ff+1)
#define MAX_PORTS       (M6812_MAX_PORTS)

struct _sim_cpu;

typedef void (* cpu_interp) (struct _sim_cpu*);

struct _sim_cpu {
  /* CPU registers.  */
  struct m6811_regs     cpu_regs;

  /* CPU interrupts.  */
  struct interrupts     cpu_interrupts;

  /* Pointer to the interpretor routine.  */
  cpu_interp            cpu_interpretor;

  /* Pointer to the architecture currently configured in the simulator.  */
  const struct bfd_arch_info  *cpu_configured_arch;
  
  /* CPU absolute cycle time.  The cycle time is updated after
     each instruction, by the number of cycles taken by the instruction.
     It is cleared only when reset occurs.  */
  signed64              cpu_absolute_cycle;

  /* Number of cycles to increment after the current instruction.
     This is also the number of ticks for the generic event scheduler.  */
  uint8                 cpu_current_cycle;
  int                   cpu_emul_syscall;
  int                   cpu_is_initialized;
  int                   cpu_running;
  int                   cpu_check_memory;
  int                   cpu_stop_on_interrupt;

  /* When this is set, start execution of program at address specified
     in the ELF header.  This is used for testing some programs that do not
     have an interrupt table linked with them.  Programs created during the
     GCC validation are like this. A normal 68HC11 does not behave like
     this (unless there is some OS or downloadable feature).  */
  int                   cpu_use_elf_start;

  /* The starting address specified in ELF header.  */
  int                   cpu_elf_start;
  
  uint16                cpu_insn_pc;

  /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
     get the cycle time.  This is used for the timer rate and for the baud
     rate generation.  */
  unsigned long         cpu_frequency;

  /* The mode in which the CPU is configured (MODA and MODB pins).  */
  unsigned int          cpu_mode;

  /* The cpu being configured.  */
  enum cpu_type         cpu_type;
  
  /* Initial value of the CONFIG register.  */
  uint8                 cpu_config;
  uint8                 cpu_use_local_config;
  
  uint8                 ios[MAX_PORTS];

  struct hw            *hw_cpu;

  /* ... base type ... */
  sim_cpu_base base;
};

/* Returns the cpu absolute cycle time (A virtual counter incremented
   at each 68HC11 E clock).  */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC)    ((PROC)->cpu_running)

/* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
#define cpu_get_io_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
        (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)

/* Returns the different CPU registers.  */
#define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
#define cpu_get_page(PROC)         (PROC->cpu_regs.page)

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_get_tmp3(PROC)         (0)
#define cpu_get_tmp2(PROC)         (0)

#define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
#define cpu_set_page(PROC,VAL)     ((PROC->cpu_regs.page) = (VAL))

/* 68HC12 specific and Motorola internal registers.  */
#define cpu_set_tmp3(PROC,VAL)     (0)
#define cpu_set_tmp2(PROC,VAL)     (void) (0)

#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame.  */
#define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
#endif

#define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))

#define cpu_set_a(PROC,VAL)  \
      cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL)  \
      cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))

#define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)

#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))

#define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)

#undef inline
#define inline static __inline__

extern void cpu_memory_exception (struct _sim_cpu *proc,
                                  SIM_SIGNAL excep,
                                  uint16 addr,
                                  const char *message);

inline address_word
phys_to_virt (sim_cpu *cpu, address_word addr)
{
  if (addr >= 0x8000 && addr < 0xc000)
    return ((address_word) (addr) - 0x8000)
      + (((address_word) cpu->cpu_regs.page) << 14) + 0x01000000;
  else
    return (address_word) (addr);
}

inline uint8
memory_read8 (sim_cpu *cpu, uint16 addr)
{
  uint8 val;

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return val;
}

inline void
memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
{
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}

inline uint16
memory_read16 (sim_cpu *cpu, uint16 addr)
{
  uint8 b[2];

  if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Read error");
    }
  return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
}

inline void
memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
{
  uint8 b[2];

  b[0] = val >> 8;
  b[1] = val;
  if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
    {
      cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
                            "Write error");
    }
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);

     inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_V (proc, 0);
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
}

     inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
{
  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

     inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
{
  cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
  cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
}

inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}


inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
}

inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
{
  cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
  cpu_set_ccr_Z (proc, r == 0);
  cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
}

/* Push and pop instructions for 68HC11 (next-available stack mode).  */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp - 1;

  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr - 1;
}

inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr + 1);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Push and pop instructions for 68HC12 (last-used stack mode).  */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr --;
  memory_write8 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
{
  uint16 addr = proc->cpu_regs.sp;

  addr -= 2;
  memory_write16 (proc, addr, val);
  proc->cpu_regs.sp = addr;
}

inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.sp = addr + 1;
  return val;
}

inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.sp;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.sp = addr + 2;
  return val;
}

/* Fetch a 8/16 bit value and update the PC.  */
inline uint8
cpu_fetch8 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint8 val;
  
  val = memory_read8 (proc, addr);
  proc->cpu_regs.pc = addr + 1;
  return val;
}

inline uint16
cpu_fetch16 (sim_cpu *proc)
{
  uint16 addr = proc->cpu_regs.pc;
  uint16 val;
  
  val = memory_read16 (proc, addr);
  proc->cpu_regs.pc = addr + 2;
  return val;
}

extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);

extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);

extern void cpu_info (SIM_DESC sd, sim_cpu *proc);

extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);

/* Returns the address of a 68HC12 indexed operand.
   Pre and post modifications are handled on the source register.  */
extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict);

extern void cpu_return (sim_cpu *cpu);
extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
                              uint16 addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);

extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
				      double ton, double toff,
				      signed64 repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
				 unsigned addr, uint8 val);

/* The current state of the processor; registers, memory, etc.  */

#define CIA_GET(CPU)      (cpu_get_pc (CPU))
#define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))

#if (WITH_SMP)
#define STATE_CPU(sd,n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd,n) (&(sd)->cpu[0])
#endif

struct sim_state {
  sim_cpu        cpu[MAX_NR_PROCESSORS];
  device         *devices;
  sim_state_base base;
};

extern void sim_set_profile (int n);
extern void sim_set_profile_size (int n);
extern void sim_board_reset (SIM_DESC sd);

extern const char *cycle_to_string (sim_cpu *cpu, signed64 t);

#endif
Commit	Line	Data
81e09ed8	1	/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
5abb9efa	2	Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
63f36def	3	Written by Stephane Carrez (stcarrez@nerim.fr)
e0709f50 AC	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef _SIM_MAIN_H
	22	#define _SIM_MAIN_H
	23
	24	#define WITH_MODULO_MEMORY 1
	25	#define WITH_WATCHPOINTS 1
	26	#define SIM_HANDLES_LMA 1
	27
	28	#include "sim-basics.h"
	29
	30	typedef address_word sim_cia;
	31
	32	#include "sim-signal.h"
	33	#include "sim-base.h"
	34
	35	#include "bfd.h"
	36
	37	#include "opcode/m68hc11.h"
	38
3c25f8c7 AC	39	#include "gdb/callback.h"
3c25f8c7 AC	40	#include "gdb/remote-sim.h"
e0709f50 AC	41	#include "opcode/m68hc11.h"
	42	#include "sim-types.h"
	43
	44	typedef unsigned8 uint8;
	45	typedef unsigned16 uint16;
	46	typedef signed16 int16;
	47	typedef unsigned32 uint32;
	48	typedef signed32 int32;
	49	typedef unsigned64 uint64;
	50	typedef signed64 int64;
	51
	52	struct _sim_cpu;
	53
	54	#include "interrupts.h"
	55	#include <setjmp.h>
	56
63348d04 SC	57	/* Specifies the level of mapping for the IO, EEprom, nvram and external
	58	RAM. IO registers are mapped over everything and the external RAM
	59	is last (ie, it can be hidden by everything above it in the list). */
	60	enum m68hc11_map_level
	61	{
	62	M6811_IO_LEVEL,
	63	M6811_EEPROM_LEVEL,
	64	M6811_NVRAM_LEVEL,
	65	M6811_RAM_LEVEL
	66	};
	67
81e09ed8 SC	68	enum cpu_type
	69	{
	70	CPU_M6811,
	71	CPU_M6812
	72	};
63348d04	73
e0709f50 AC	74	#define X_REGNUM 0
	75	#define D_REGNUM 1
	76	#define Y_REGNUM 2
	77	#define SP_REGNUM 3
	78	#define PC_REGNUM 4
	79	#define A_REGNUM 5
	80	#define B_REGNUM 6
	81	#define PSW_REGNUM 7
	82	#define Z_REGNUM 8
63f36def	83	#define PAGE_REGNUM 9
e0709f50 AC	84
	85	typedef struct m6811_regs {
	86	unsigned short d;
	87	unsigned short ix;
	88	unsigned short iy;
	89	unsigned short sp;
	90	unsigned short pc;
	91	unsigned char ccr;
63f36def	92	unsigned short page;
e0709f50 AC	93	} m6811_regs;
	94
	95
	96	/* Description of 68HC11 IO registers. Such description is only provided
	97	for the info command to display the current setting of IO registers
	98	from GDB. */
	99	struct io_reg_desc
	100	{
	101	int mask;
	102	const char *short_name;
	103	const char *long_name;
	104	};
	105	typedef struct io_reg_desc io_reg_desc;
	106
	107	extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
	108	int mode);
	109	extern void print_io_byte (SIM_DESC sd, const char *name,
	110	io_reg_desc *desc, uint8 val, uint16 addr);
	111
	112
81e09ed8	113	/* List of special 68HC11&68HC12 instructions that are not handled by the
e0709f50 AC	114	'gencode.c' generator. These complex instructions are implemented
	115	by 'cpu_special'. */
	116	enum M6811_Special
	117	{
81e09ed8 SC	118	/* 68HC11 instructions. */
	119	M6811_DAA,
	120	M6811_EMUL_SYSCALL,
	121	M6811_ILLEGAL,
e0709f50	122	M6811_RTI,
81e09ed8	123	M6811_STOP,
e0709f50 AC	124	M6811_SWI,
e0709f50 AC	125	M6811_TEST,
81e09ed8 SC	126	M6811_WAI,
	127
	128	/* 68HC12 instructions. */
	129	M6812_BGND,
	130	M6812_CALL,
63f36def	131	M6812_CALL_INDIRECT,
81e09ed8 SC	132	M6812_IDIVS,
	133	M6812_EDIV,
	134	M6812_EDIVS,
	135	M6812_EMACS,
	136	M6812_EMUL,
	137	M6812_EMULS,
	138	M6812_ETBL,
	139	M6812_MEM,
	140	M6812_REV,
	141	M6812_REVW,
	142	M6812_RTC,
	143	M6812_RTI,
	144	M6812_WAV
e0709f50 AC	145	};
e0709f50 AC	146
81e09ed8 SC	147	#define M6811_MAX_PORTS (0x03f+1)
	148	#define M6812_MAX_PORTS (0x3ff+1)
	149	#define MAX_PORTS (M6812_MAX_PORTS)
e0709f50	150
81e09ed8 SC	151	struct _sim_cpu;
	152
	153	typedef void (* cpu_interp) (struct _sim_cpu*);
	154
e0709f50 AC	155	struct _sim_cpu {
	156	/* CPU registers. */
	157	struct m6811_regs cpu_regs;
	158
	159	/* CPU interrupts. */
	160	struct interrupts cpu_interrupts;
	161
81e09ed8 SC	162	/* Pointer to the interpretor routine. */
	163	cpu_interp cpu_interpretor;
	164
	165	/* Pointer to the architecture currently configured in the simulator. */
	166	const struct bfd_arch_info *cpu_configured_arch;
	167
e0709f50 AC	168	/* CPU absolute cycle time. The cycle time is updated after
	169	each instruction, by the number of cycles taken by the instruction.
	170	It is cleared only when reset occurs. */
	171	signed64 cpu_absolute_cycle;
	172
	173	/* Number of cycles to increment after the current instruction.
	174	This is also the number of ticks for the generic event scheduler. */
	175	uint8 cpu_current_cycle;
	176	int cpu_emul_syscall;
	177	int cpu_is_initialized;
	178	int cpu_running;
	179	int cpu_check_memory;
	180	int cpu_stop_on_interrupt;
	181
	182	/* When this is set, start execution of program at address specified
	183	in the ELF header. This is used for testing some programs that do not
	184	have an interrupt table linked with them. Programs created during the
	185	GCC validation are like this. A normal 68HC11 does not behave like
	186	this (unless there is some OS or downloadable feature). */
	187	int cpu_use_elf_start;
	188
	189	/* The starting address specified in ELF header. */
	190	int cpu_elf_start;
	191
	192	uint16 cpu_insn_pc;
e0709f50 AC	193
	194	/* CPU frequency. This is the quartz frequency. It is divided by 4 to
	195	get the cycle time. This is used for the timer rate and for the baud
	196	rate generation. */
	197	unsigned long cpu_frequency;
	198
	199	/* The mode in which the CPU is configured (MODA and MODB pins). */
	200	unsigned int cpu_mode;
	201
81e09ed8 SC	202	/* The cpu being configured. */
	203	enum cpu_type cpu_type;
	204
e0709f50 AC	205	/* Initial value of the CONFIG register. */
	206	uint8 cpu_config;
	207	uint8 cpu_use_local_config;
	208
81e09ed8	209	uint8 ios[MAX_PORTS];
827ec39a SC	210
	211	struct hw *hw_cpu;
	212
e0709f50 AC	213	/* ... base type ... */
	214	sim_cpu_base base;
	215	};
	216
	217	/* Returns the cpu absolute cycle time (A virtual counter incremented
	218	at each 68HC11 E clock). */
	219	#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
	220	#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
	221	#define cpu_is_running(PROC) ((PROC)->cpu_running)
	222
	223	/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
	224	#define cpu_get_io_base(PROC) \
	225	(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
	226	#define cpu_get_reg_base(PROC) \
	227	(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
	228
	229	/* Returns the different CPU registers. */
	230	#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
	231	#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
	232	#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
	233	#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
	234	#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
	235	#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
	236	#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
	237	#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
63f36def	238	#define cpu_get_page(PROC) (PROC->cpu_regs.page)
e0709f50	239
81e09ed8 SC	240	/* 68HC12 specific and Motorola internal registers. */
	241	#define cpu_get_tmp3(PROC) (0)
	242	#define cpu_get_tmp2(PROC) (0)
	243
e0709f50 AC	244	#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
	245	#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
	246	#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
63f36def	247	#define cpu_set_page(PROC,VAL) ((PROC->cpu_regs.page) = (VAL))
e0709f50	248
81e09ed8 SC	249	/* 68HC12 specific and Motorola internal registers. */
81e09ed8 SC	250	#define cpu_set_tmp3(PROC,VAL) (0)
63f36def	251	#define cpu_set_tmp2(PROC,VAL) (void) (0)
81e09ed8	252
e0709f50 AC	253	#if 0
	254	/* This is a function in m68hc11_sim.c to keep track of the frame. */
	255	#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
	256	#endif
	257
	258	#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
	259
	260	#define cpu_set_a(PROC,VAL) \
	261	cpu_set_d(PROC,((VAL) << 8) \| cpu_get_b(PROC))
	262	#define cpu_set_b(PROC,VAL) \
	263	cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)\|(VAL & 0x0FF))
	264
	265	#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
	266	#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
	267	#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
	268	#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
	269	#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
	270	#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
	271	#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
	272	#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
	273	#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
	274
	275	#define cpu_set_ccr_flag(S,B,V) \
	276	cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) \| ((V) ? B : 0))
	277
	278	#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
	279	#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
	280	#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
	281	#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
	282	#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
	283	#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
	284	#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
	285	#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
	286
	287	#undef inline
	288	#define inline static __inline__
	289
	290	extern void cpu_memory_exception (struct _sim_cpu *proc,
	291	SIM_SIGNAL excep,
	292	uint16 addr,
	293	const char *message);
	294
63f36def SC	295	inline address_word
	296	phys_to_virt (sim_cpu *cpu, address_word addr)
	297	{
	298	if (addr >= 0x8000 && addr < 0xc000)
	299	return ((address_word) (addr) - 0x8000)
	300	+ (((address_word) cpu->cpu_regs.page) << 14) + 0x01000000;
	301	else
	302	return (address_word) (addr);
	303	}
	304
e0709f50 AC	305	inline uint8
	306	memory_read8 (sim_cpu *cpu, uint16 addr)
	307	{
	308	uint8 val;
63f36def	309
e0709f50 AC	310	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	311	{
	312	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	313	"Read error");
	314	}
	315	return val;
	316	}
	317
	318	inline void
	319	memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
	320	{
	321	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
	322	{
	323	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	324	"Write error");
	325	}
	326	}
	327
	328	inline uint16
	329	memory_read16 (sim_cpu *cpu, uint16 addr)
	330	{
	331	uint8 b[2];
63f36def	332
e0709f50 AC	333	if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	334	{
	335	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	336	"Read error");
	337	}
	338	return (((uint16) (b[0])) << 8) \| ((uint16) b[1]);
	339	}
	340
	341	inline void
	342	memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
	343	{
	344	uint8 b[2];
	345
	346	b[0] = val >> 8;
	347	b[1] = val;
	348	if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
	349	{
	350	cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
	351	"Write error");
	352	}
	353	}
	354	extern void
	355	cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
	356
	357	inline void
	358	cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
	359	{
	360	cpu_set_ccr_V (proc, 0);
	361	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	362	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	363	}
	364
	365	inline void
	366	cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
	367	{
	368	cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
	369	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	370	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	371	}
	372
	373	inline void
	374	cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
	375	{
	376	cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
	377	cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
	378	cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
	379	}
	380
	381	inline void
	382	cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	383	{
	384	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x80 ? 1 : 0);
	385	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x80 ? 1 : 0);
	386	cpu_set_ccr_Z (proc, r == 0);
	387	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
	388	}
	389
	390
	391	inline void
	392	cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
	393	{
	394	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x80 ? 1 : 0);
	395	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x80 ? 1 : 0);
	396	cpu_set_ccr_Z (proc, r == 0);
397	cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
398	}
399
400	inline void
401	cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
402	{
403	cpu_set_ccr_C (proc, ((a & b) \| (b & ~r) \| (a & ~r)) & 0x8000 ? 1 : 0);
404	cpu_set_ccr_V (proc, ((a & b & ~r) \| (~a & ~b & r)) & 0x8000 ? 1 : 0);
405	cpu_set_ccr_Z (proc, r == 0);
406	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
407	}
408
409	inline void
410	cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
411	{
412	cpu_set_ccr_C (proc, ((~a & b) \| (b & r) \| (~a & r)) & 0x8000 ? 1 : 0);
413	cpu_set_ccr_V (proc, ((a & ~b & ~r) \| (~a & b & r)) & 0x8000 ? 1 : 0);
414	cpu_set_ccr_Z (proc, r == 0);
415	cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
416	}
417
81e09ed8	418	/* Push and pop instructions for 68HC11 (next-available stack mode). */
e0709f50	419	inline void
81e09ed8	420	cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
e0709f50 AC	421	{
	422	uint16 addr = proc->cpu_regs.sp;
	423
	424	memory_write8 (proc, addr, val);
	425	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	426	}
	427
	428	inline void
81e09ed8	429	cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
e0709f50 AC	430	{
	431	uint16 addr = proc->cpu_regs.sp - 1;
	432
	433	memory_write16 (proc, addr, val);
	434	proc->cpu_regs.sp = addr - 1;
e0709f50 AC	435	}
	436
	437	inline uint8
81e09ed8	438	cpu_m68hc11_pop_uint8 (sim_cpu *proc)
e0709f50 AC	439	{
	440	uint16 addr = proc->cpu_regs.sp;
	441	uint8 val;
	442
	443	val = memory_read8 (proc, addr + 1);
	444	proc->cpu_regs.sp = addr + 1;
e0709f50 AC	445	return val;
	446	}
	447
	448	inline uint16
81e09ed8	449	cpu_m68hc11_pop_uint16 (sim_cpu *proc)
e0709f50 AC	450	{
	451	uint16 addr = proc->cpu_regs.sp;
	452	uint16 val;
	453
	454	val = memory_read16 (proc, addr + 1);
	455	proc->cpu_regs.sp = addr + 2;
e0709f50 AC	456	return val;
	457	}
	458
81e09ed8 SC	459	/* Push and pop instructions for 68HC12 (last-used stack mode). */
	460	inline void
	461	cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
	462	{
	463	uint16 addr = proc->cpu_regs.sp;
	464
	465	addr --;
	466	memory_write8 (proc, addr, val);
	467	proc->cpu_regs.sp = addr;
81e09ed8 SC	468	}
	469
	470	inline void
	471	cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
	472	{
	473	uint16 addr = proc->cpu_regs.sp;
	474
	475	addr -= 2;
	476	memory_write16 (proc, addr, val);
	477	proc->cpu_regs.sp = addr;
81e09ed8 SC	478	}
	479
	480	inline uint8
	481	cpu_m68hc12_pop_uint8 (sim_cpu *proc)
	482	{
	483	uint16 addr = proc->cpu_regs.sp;
	484	uint8 val;
	485
	486	val = memory_read8 (proc, addr);
	487	proc->cpu_regs.sp = addr + 1;
81e09ed8 SC	488	return val;
	489	}
	490
	491	inline uint16
	492	cpu_m68hc12_pop_uint16 (sim_cpu *proc)
	493	{
	494	uint16 addr = proc->cpu_regs.sp;
	495	uint16 val;
	496
	497	val = memory_read16 (proc, addr);
	498	proc->cpu_regs.sp = addr + 2;
81e09ed8 SC	499	return val;
	500	}
	501
	502	/* Fetch a 8/16 bit value and update the PC. */
e0709f50 AC	503	inline uint8
	504	cpu_fetch8 (sim_cpu *proc)
	505	{
	506	uint16 addr = proc->cpu_regs.pc;
	507	uint8 val;
	508
	509	val = memory_read8 (proc, addr);
	510	proc->cpu_regs.pc = addr + 1;
	511	return val;
	512	}
	513
	514	inline uint16
	515	cpu_fetch16 (sim_cpu *proc)
	516	{
	517	uint16 addr = proc->cpu_regs.pc;
	518	uint16 val;
	519
	520	val = memory_read16 (proc, addr);
	521	proc->cpu_regs.pc = addr + 2;
	522	return val;
	523	}
	524
	525	extern void cpu_call (sim_cpu* proc, uint16 addr);
81e09ed8 SC	526	extern void cpu_exg (sim_cpu* proc, uint8 code);
81e09ed8 SC	527	extern void cpu_dbcc (sim_cpu* proc);
e0709f50	528	extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
81e09ed8 SC	529	extern void cpu_move8 (sim_cpu *proc, uint8 op);
81e09ed8 SC	530	extern void cpu_move16 (sim_cpu *proc, uint8 op);
e0709f50 AC	531
e0709f50 AC	532	extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
81e09ed8	533	extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
e0709f50 AC	534	extern void cpu_push_all (sim_cpu *proc);
	535	extern void cpu_single_step (sim_cpu *proc);
	536
	537	extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
	538
	539	extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
	540
63f36def SC	541	/* Returns the address of a 68HC12 indexed operand.
	542	Pre and post modifications are handled on the source register. */
	543	extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict);
	544
	545	extern void cpu_return (sim_cpu *cpu);
e0709f50	546	extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
e0709f50 AC	547	extern int cpu_reset (sim_cpu *cpu);
	548	extern int cpu_restart (sim_cpu *cpu);
	549	extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
	550	uint16 addr, const char *message, ...);
	551	extern void emul_os (int op, sim_cpu *cpu);
81e09ed8 SC	552	extern void cpu_interp_m6811 (sim_cpu *cpu);
81e09ed8 SC	553	extern void cpu_interp_m6812 (sim_cpu *cpu);
e0709f50	554
827ec39a SC	555	extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
	556	double ton, double toff,
	557	signed64 repeat);
	558	extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
	559	extern void m68hc11cpu_set_port (struct hw me, sim_cpu cpu,
	560	unsigned addr, uint8 val);
	561
e0709f50 AC	562	/* The current state of the processor; registers, memory, etc. */
	563
	564	#define CIA_GET(CPU) (cpu_get_pc (CPU))
	565	#define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL)))
	566
	567	#if (WITH_SMP)
	568	#define STATE_CPU(sd,n) (&(sd)->cpu[n])
	569	#else
	570	#define STATE_CPU(sd,n) (&(sd)->cpu[0])
	571	#endif
	572
	573	struct sim_state {
	574	sim_cpu cpu[MAX_NR_PROCESSORS];
	575	device *devices;
	576	sim_state_base base;
	577	};
	578
	579	extern void sim_set_profile (int n);
	580	extern void sim_set_profile_size (int n);
	581	extern void sim_board_reset (SIM_DESC sd);
	582
2990a9f4 SC	583	extern const char cycle_to_string (sim_cpu cpu, signed64 t);
2990a9f4 SC	584
e0709f50 AC	585	#endif
	586
	587