2 * Copyright (C) 2004 Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
23 #include <asm/arch/imx-regs.h>
30 /* Change PERCLK1DIV to 14 ie 14+1 */
32 ldr r1, =CONFIG_SYS_PCDR_VAL
35 /* set MCU PLL Control Register 0 */
38 ldr r1, =CONFIG_SYS_MPCTL0_VAL
41 /* set MCU PLL Control Register 1 */
44 ldr r1, =CONFIG_SYS_MPCTL1_VAL
47 /* set mpll restart bit */
63 /* set System PLL Control Register 0 */
66 ldr r1, =CONFIG_SYS_SPCTL0_VAL
69 /* set System PLL Control Register 1 */
72 ldr r1, =CONFIG_SYS_SPCTL1_VAL
75 /* set spll restart bit */
92 ldr r1, =CONFIG_SYS_CSCR_VAL
96 ldr r1, =CONFIG_SYS_GPCR_VAL
100 * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
103 * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
104 * register 1, this stops it using the output of the PLL and thus runs at the
105 * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
106 * use the value set in the CM_OSC registers...regardless of what you set it
107 * too! Thus, although i thought i was running at 140MHz, i'm actually running
110 * Slapping this into my bootloader does the trick...
112 * MRC p15,0,r0,c1,c0,0 ; read core configuration register
113 * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
114 * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
119 /* ORR r0,r0,#0xC0000000 async mode */
120 /* ORR r0,r0,#0x40000000 sync mode */
121 ORR r0,r0,#0xC0000000
125 ldr r1, =CONFIG_SYS_GIUS_A_VAL
129 ldr r1, =CONFIG_SYS_FMCR_VAL
133 ldr r1, =CONFIG_SYS_CS0U_VAL
137 ldr r1, =CONFIG_SYS_CS0L_VAL
141 ldr r1, =CONFIG_SYS_CS1U_VAL
145 ldr r1, =CONFIG_SYS_CS1L_VAL
149 ldr r1, =CONFIG_SYS_CS4U_VAL
153 ldr r1, =CONFIG_SYS_CS4L_VAL
157 ldr r1, =CONFIG_SYS_CS5U_VAL
161 ldr r1, =CONFIG_SYS_CS5L_VAL
166 ldr r1,=0x00221000 /* adr of SDCTRL0 */
168 str r0,[r1,#0] /* put in precharge command mode */
169 ldr r2,=0x08200000 /* adr for precharge cmd */
170 ldr r0,[r2,#0] /* precharge */
172 ldr r2,=0x08000000 /* start of SDRAM */
173 str r0,[r1,#0] /* put in auto-refresh mode */
174 ldr r0,[r2,#0] /* auto-refresh */
175 ldr r0,[r2,#0] /* auto-refresh */
176 ldr r0,[r2,#0] /* auto-refresh */
177 ldr r0,[r2,#0] /* auto-refresh */
178 ldr r0,[r2,#0] /* auto-refresh */
179 ldr r0,[r2,#0] /* auto-refresh */
180 ldr r0,[r2,#0] /* auto-refresh */
183 str r0,[r1,#0] /* setup for mode register of SDRAM */
184 ldr r0,[r2,#0] /* program mode register */
186 str r0,[r1,#0] /* back to normal operation */