2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/sizes.h>
15 #include <asm/arch/at91sam9_smc.h>
16 #include <asm/arch/at91_common.h>
17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/at91_matrix.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/gpio.h>
23 #include <atmel_lcdc.h>
24 #include <dataflash.h>
25 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
30 DECLARE_GLOBAL_DATA_PTR
;
32 /* ------------------------------------------------------------------------- */
34 * Miscelaneous platform dependent initialisations
37 #ifdef CONFIG_CMD_NAND
38 static void pm9263_nand_hw_init(void)
41 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC0
;
42 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
45 csa
= readl(&matrix
->csa
[0]) | AT91_MATRIX_CSA_EBI_CS3A
;
46 writel(csa
, &matrix
->csa
[0]);
48 /* Configure SMC CS3 for NAND/SmartMedia */
49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
60 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
61 AT91_SMC_MODE_EXNW_DISABLE
|
62 #ifdef CONFIG_SYS_NAND_DBW_16
63 AT91_SMC_MODE_DBW_16
|
64 #else /* CONFIG_SYS_NAND_DBW_8 */
67 AT91_SMC_MODE_TDF_CYCLE(2),
70 /* Configure RDY/BSY */
71 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN
);
73 /* Enable NandFlash */
74 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
79 static void pm9263_macb_hw_init(void)
81 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
84 * PB27 enables the 50MHz oscillator for Ethernet PHY
88 at91_set_pio_output(AT91_PIO_PORTB
, 27, 1);
89 at91_set_pio_value(AT91_PIO_PORTB
, 27, 1); /* 1- enable, 0 - disable */
92 writel(1 << ATMEL_ID_EMAC
, &pmc
->pcer
);
96 * RXDV (PC25) => PHY normal mode (not Test mode)
97 * ERX0 (PE25) => PHY ADDR0
98 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
100 * PHY has internal pull-down
103 at91_set_pio_pullup(AT91_PIO_PORTC
, 25, 0);
104 at91_set_pio_pullup(AT91_PIO_PORTE
, 25, 0);
105 at91_set_pio_pullup(AT91_PIO_PORTE
, 26, 0);
107 /* Re-enable pull-up */
108 at91_set_pio_pullup(AT91_PIO_PORTC
, 25, 1);
109 at91_set_pio_pullup(AT91_PIO_PORTE
, 25, 1);
110 at91_set_pio_pullup(AT91_PIO_PORTE
, 26, 1);
117 vidinfo_t panel_info
= {
121 vl_sync
: ATMEL_LCDC_INVLINE_INVERTED
|
122 ATMEL_LCDC_INVFRAME_INVERTED
,
131 mmio
: ATMEL_BASE_LCDC
,
134 void lcd_enable(void)
136 at91_set_pio_value(AT91_PIO_PORTA
, 22, 1); /* power up */
139 void lcd_disable(void)
141 at91_set_pio_value(AT91_PIO_PORTA
, 22, 0); /* power down */
144 #ifdef CONFIG_LCD_IN_PSRAM
146 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
147 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
149 /* Initialize the PSRAM memory */
150 static int pm9263_lcd_hw_psram_init(void)
153 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC1
;
154 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
156 /* Enable CS3 3.3v, no pull-ups */
157 csa
= readl(&matrix
->csa
[1]) | AT91_MATRIX_CSA_DBPUC
|
158 AT91_MATRIX_CSA_VDDIOMSEL_3_3V
;
160 writel(csa
, &matrix
->csa
[1]);
162 /* Configure SMC1 CS0 for PSRAM - 16-bit */
163 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
164 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
167 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
168 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
171 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
174 writel(AT91_SMC_MODE_DBW_16
| AT91_SMC_MODE_PMEN
| AT91_SMC_MODE_PS_32
,
177 /* setup PB29 as output */
178 at91_set_pio_output(PSRAM_CRE_PIN
, 1);
180 at91_set_pio_value(PSRAM_CRE_PIN
, 0); /* set PSRAM_CRE_PIN to '0' */
182 /* PSRAM: write BCR */
183 readw(PSRAM_CTRL_REG
);
184 readw(PSRAM_CTRL_REG
);
185 writew(1, PSRAM_CTRL_REG
); /* 0 - RCR,1 - BCR */
186 writew(0x9d4f, PSRAM_CTRL_REG
); /* write the BCR */
188 /* write RCR of the PSRAM */
189 readw(PSRAM_CTRL_REG
);
190 readw(PSRAM_CTRL_REG
);
191 writew(0, PSRAM_CTRL_REG
); /* 0 - RCR,1 - BCR */
192 /* set RCR; 0x10-async mode,0x90-page mode */
193 writew(0x90, PSRAM_CTRL_REG
);
196 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
197 * MT45W2M16B - CRE must be 0
198 * MT45W2M16A - CRE must be 1
200 writew(0x1234, PHYS_PSRAM
);
201 writew(0x5678, PHYS_PSRAM
+ 2);
203 /* test if the chip is MT45W2M16B */
204 if ((readw(PHYS_PSRAM
) != 0x1234) || (readw(PHYS_PSRAM
+2) != 0x5678)) {
205 /* try with CRE=1 (MT45W2M16A) */
206 at91_set_pio_value(PSRAM_CRE_PIN
, 1); /* set PSRAM_CRE_PIN to '1' */
208 /* write RCR of the PSRAM */
209 readw(PSRAM_CTRL_REG
);
210 readw(PSRAM_CTRL_REG
);
211 writew(0, PSRAM_CTRL_REG
); /* 0 - RCR,1 - BCR */
212 /* set RCR;0x10-async mode,0x90-page mode */
213 writew(0x90, PSRAM_CTRL_REG
);
216 writew(0x1234, PHYS_PSRAM
);
217 writew(0x5678, PHYS_PSRAM
+2);
218 if ((readw(PHYS_PSRAM
) != 0x1234)
219 || (readw(PHYS_PSRAM
+ 2) != 0x5678))
225 writel(AT91_MATRIX_PRA_M5(3), &matrix
->pr
[5].a
);
226 writel(CONFIG_PSRAM_SCFG
, &matrix
->scfg
[5]);
232 static void pm9263_lcd_hw_init(void)
234 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
236 at91_set_a_periph(AT91_PIO_PORTC
, 0, 0); /* LCDVSYNC */
237 at91_set_a_periph(AT91_PIO_PORTC
, 1, 0); /* LCDHSYNC */
238 at91_set_a_periph(AT91_PIO_PORTC
, 2, 0); /* LCDDOTCK */
239 at91_set_a_periph(AT91_PIO_PORTC
, 3, 0); /* LCDDEN */
240 at91_set_b_periph(AT91_PIO_PORTB
, 9, 0); /* LCDCC */
241 at91_set_a_periph(AT91_PIO_PORTC
, 6, 0); /* LCDD2 */
242 at91_set_a_periph(AT91_PIO_PORTC
, 7, 0); /* LCDD3 */
243 at91_set_a_periph(AT91_PIO_PORTC
, 8, 0); /* LCDD4 */
244 at91_set_a_periph(AT91_PIO_PORTC
, 9, 0); /* LCDD5 */
245 at91_set_a_periph(AT91_PIO_PORTC
, 10, 0); /* LCDD6 */
246 at91_set_a_periph(AT91_PIO_PORTC
, 11, 0); /* LCDD7 */
247 at91_set_a_periph(AT91_PIO_PORTC
, 14, 0); /* LCDD10 */
248 at91_set_a_periph(AT91_PIO_PORTC
, 15, 0); /* LCDD11 */
249 at91_set_a_periph(AT91_PIO_PORTC
, 16, 0); /* LCDD12 */
250 at91_set_b_periph(AT91_PIO_PORTC
, 12, 0); /* LCDD13 */
251 at91_set_a_periph(AT91_PIO_PORTC
, 18, 0); /* LCDD14 */
252 at91_set_a_periph(AT91_PIO_PORTC
, 19, 0); /* LCDD15 */
253 at91_set_a_periph(AT91_PIO_PORTC
, 22, 0); /* LCDD18 */
254 at91_set_a_periph(AT91_PIO_PORTC
, 23, 0); /* LCDD19 */
255 at91_set_a_periph(AT91_PIO_PORTC
, 24, 0); /* LCDD20 */
256 at91_set_b_periph(AT91_PIO_PORTC
, 17, 0); /* LCDD21 */
257 at91_set_a_periph(AT91_PIO_PORTC
, 26, 0); /* LCDD22 */
258 at91_set_a_periph(AT91_PIO_PORTC
, 27, 0); /* LCDD23 */
260 writel(1 << ATMEL_ID_LCDC
, &pmc
->pcer
);
263 at91_set_pio_output(AT91_PIO_PORTA
, 22, 1);
264 at91_set_pio_value(AT91_PIO_PORTA
, 22, 0); /* power down */
266 #ifdef CONFIG_LCD_IN_PSRAM
267 /* initialize te PSRAM */
268 int stat
= pm9263_lcd_hw_psram_init();
270 gd
->fb_base
= (stat
== 0) ? PHYS_PSRAM
: ATMEL_BASE_SRAM0
;
272 gd
->fb_base
= ATMEL_BASE_SRAM0
;
277 #ifdef CONFIG_LCD_INFO
281 extern flash_info_t flash_info
[];
283 void lcd_show_board_info(void)
285 ulong dram_size
, nand_size
, flash_size
, dataflash_size
;
289 lcd_printf ("%s\n", U_BOOT_VERSION
);
290 lcd_printf ("(C) 2009 Ronetix GmbH\n");
291 lcd_printf ("support@ronetix.at\n");
292 lcd_printf ("%s CPU at %s MHz",
293 CONFIG_SYS_AT91_CPU_NAME
,
294 strmhz(temp
, get_cpu_clk_rate()));
297 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
298 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
301 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
302 nand_size
+= nand_info
[i
].size
;
305 for (i
= 0; i
< CONFIG_SYS_MAX_FLASH_BANKS
; i
++)
306 flash_size
+= flash_info
[i
].size
;
309 for (i
= 0; i
< CONFIG_SYS_MAX_DATAFLASH_BANKS
; i
++)
310 dataflash_size
+= (unsigned int) dataflash_info
[i
].Device
.pages_number
*
311 dataflash_info
[i
].Device
.pages_size
;
313 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
314 "4 MB PSRAM, %ld MB DataFlash\n",
318 dataflash_size
>> 20);
320 #endif /* CONFIG_LCD_INFO */
322 #endif /* CONFIG_LCD */
324 int board_early_init_f(void)
326 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
328 /* Enable clocks for all PIOs */
329 writel((1 << ATMEL_ID_PIOA
) | (1 << ATMEL_ID_PIOB
) |
330 (1 << ATMEL_ID_PIOCDE
),
333 at91_seriald_hw_init();
340 /* arch number of AT91SAM9263EK-Board */
341 gd
->bd
->bi_arch_number
= MACH_TYPE_PM9263
;
343 /* adress of boot parameters */
344 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
346 #ifdef CONFIG_CMD_NAND
347 pm9263_nand_hw_init();
349 #ifdef CONFIG_HAS_DATAFLASH
350 at91_spi0_hw_init(1 << 0);
353 pm9263_macb_hw_init();
355 #ifdef CONFIG_USB_OHCI_NEW
359 pm9263_lcd_hw_init();
366 /* dram_init must store complete ramsize in gd->ram_size */
367 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
,
372 void dram_init_banksize(void)
374 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM
;
375 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_SIZE
;
378 #ifdef CONFIG_RESET_PHY_R
384 int board_eth_init(bd_t
*bis
)
388 rc
= macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC
, 0x01);
393 #ifdef CONFIG_DISPLAY_BOARDINFO
394 int checkboard (void)
398 printf ("Board : Ronetix PM9263\n");
400 switch (gd
->fb_base
) {
405 case ATMEL_BASE_SRAM0
:
406 ss
= "(Internal SRAM)";
413 printf("Video memory : 0x%08lX %s\n", gd
->fb_base
, ss
);