hw/arm/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qemu/units.h"
  20 #include "qapi/error.h"
  21 #include "cpu.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/boot.h"
  24 #include "net/net.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/boards.h"
  28 #include "hw/block/flash.h"
  29 #include "hw/loader.h"
  30 #include "hw/misc/zynq-xadc.h"
  31 #include "hw/ssi/ssi.h"
  32 #include "hw/usb/chipidea.h"
  33 #include "qemu/error-report.h"
  34 #include "hw/sd/sdhci.h"
  35 #include "hw/char/cadence_uart.h"
  36 #include "hw/net/cadence_gem.h"
  37 #include "hw/cpu/a9mpcore.h"
  38 #include "hw/qdev-clock.h"
  39 #include "sysemu/reset.h"
  40 #include "qom/object.h"
  41
  42 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
  43 typedef struct ZynqMachineState ZynqMachineState;
  44 DECLARE_INSTANCE_CHECKER(ZynqMachineState, ZYNQ_MACHINE,
  45                          TYPE_ZYNQ_MACHINE)
  46
  47 /* board base frequency: 33.333333 MHz */
  48 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
  49
  50 #define NUM_SPI_FLASHES 4
  51 #define NUM_QSPI_FLASHES 2
  52 #define NUM_QSPI_BUSSES 2
  53
  54 #define FLASH_SIZE (64 * 1024 * 1024)
  55 #define FLASH_SECTOR_SIZE (128 * 1024)
  56
  57 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  58
  59 #define MPCORE_PERIPHBASE 0xF8F00000
  60 #define ZYNQ_BOARD_MIDR 0x413FC090
  61
  62 static const int dma_irqs[8] = {
  63     46, 47, 48, 49, 72, 73, 74, 75
  64 };
  65
  66 #define BOARD_SETUP_ADDR        0x100
  67
  68 #define SLCR_LOCK_OFFSET        0x004
  69 #define SLCR_UNLOCK_OFFSET      0x008
  70 #define SLCR_ARM_PLL_OFFSET     0x100
  71
  72 #define SLCR_XILINX_UNLOCK_KEY  0xdf0d
  73 #define SLCR_XILINX_LOCK_KEY    0x767b
  74
  75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080  /* Datasheet: UG585 (v1.12.1) */
  76
  77 #define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
  78                         extract32((x), 12,  4) << 16)
  79
  80 /* Write immediate val to address r0 + addr. r0 should contain base offset
  81  * of the SLCR block. Clobbers r1.
  82  */
  83
  84 #define SLCR_WRITE(addr, val) \
  85     0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
  86     0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
  87     0xe5801000 + (addr)
  88
  89 struct ZynqMachineState {
  90     MachineState parent;
  91     Clock *ps_clk;
  92 };
  93
  94 static void zynq_write_board_setup(ARMCPU *cpu,
  95                                    const struct arm_boot_info *info)
  96 {
  97     int n;
  98     uint32_t board_setup_blob[] = {
  99         0xe3a004f8, /* mov r0, #0xf8000000 */
 100         SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
 101         SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
 102         SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
 103         0xe12fff1e, /* bx lr */
 104     };
 105     for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
 106         board_setup_blob[n] = tswap32(board_setup_blob[n]);
 107     }
 108     rom_add_blob_fixed("board-setup", board_setup_blob,
 109                        sizeof(board_setup_blob), BOARD_SETUP_ADDR);
 110 }
 111
 112 static struct arm_boot_info zynq_binfo = {};
 113
 114 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 115 {
 116     DeviceState *dev;
 117     SysBusDevice *s;
 118
 119     dev = qdev_new(TYPE_CADENCE_GEM);
 120     if (nd->used) {
 121         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 122         qdev_set_nic_properties(dev, nd);
 123     }
 124     object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
 125     s = SYS_BUS_DEVICE(dev);
 126     sysbus_realize_and_unref(s, &error_fatal);
 127     sysbus_mmio_map(s, 0, base);
 128     sysbus_connect_irq(s, 0, irq);
 129 }
 130
 131 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
 132                                          bool is_qspi)
 133 {
 134     DeviceState *dev;
 135     SysBusDevice *busdev;
 136     SSIBus *spi;
 137     DeviceState *flash_dev;
 138     int i, j;
 139     int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
 140     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
 141
 142     dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
 143     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
 144     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
 145     qdev_prop_set_uint8(dev, "num-busses", num_busses);
 146     busdev = SYS_BUS_DEVICE(dev);
 147     sysbus_realize_and_unref(busdev, &error_fatal);
 148     sysbus_mmio_map(busdev, 0, base_addr);
 149     if (is_qspi) {
 150         sysbus_mmio_map(busdev, 1, 0xFC000000);
 151     }
 152     sysbus_connect_irq(busdev, 0, irq);
 153
 154     for (i = 0; i < num_busses; ++i) {
 155         char bus_name[16];
 156         qemu_irq cs_line;
 157
 158         snprintf(bus_name, 16, "spi%d", i);
 159         spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
 160
 161         for (j = 0; j < num_ss; ++j) {
 162             DriveInfo *dinfo = drive_get_next(IF_MTD);
 163             flash_dev = qdev_new("n25q128");
 164             if (dinfo) {
 165                 qdev_prop_set_drive_err(flash_dev, "drive",
 166                                         blk_by_legacy_dinfo(dinfo),
 167                                         &error_fatal);
 168             }
 169             qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
 170
 171             cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 172             sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
 173         }
 174     }
 175
 176 }
 177
 178 static void zynq_init(MachineState *machine)
 179 {
 180     ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
 181     ARMCPU *cpu;
 182     MemoryRegion *address_space_mem = get_system_memory();
 183     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
 184     DeviceState *dev, *slcr;
 185     SysBusDevice *busdev;
 186     qemu_irq pic[64];
 187     int n;
 188
 189     /* max 2GB ram */
 190     if (machine->ram_size > 2 * GiB) {
 191         error_report("RAM size more than 2 GiB is not supported");
 192         exit(EXIT_FAILURE);
 193     }
 194
 195     cpu = ARM_CPU(object_new(machine->cpu_type));
 196
 197     /* By default A9 CPUs have EL3 enabled.  This board does not
 198      * currently support EL3 so the CPU EL3 property is disabled before
 199      * realization.
 200      */
 201     if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
 202         object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal);
 203     }
 204
 205     object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR,
 206                             &error_fatal);
 207     object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE,
 208                             &error_fatal);
 209     qdev_realize(DEVICE(cpu), NULL, &error_fatal);
 210
 211     /* DDR remapped to address zero.  */
 212     memory_region_add_subregion(address_space_mem, 0, machine->ram);
 213
 214     /* 256K of on-chip memory */
 215     memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
 216                            &error_fatal);
 217     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 218
 219     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 220
 221     /* AMD */
 222     pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
 223                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 224                           FLASH_SECTOR_SIZE, 1,
 225                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 226                           0);
 227
 228     /* Create the main clock source, and feed slcr with it */
 229     zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
 230     object_property_add_child(OBJECT(zynq_machine), "ps_clk",
 231                               OBJECT(zynq_machine->ps_clk));
 232     object_unref(OBJECT(zynq_machine->ps_clk));
 233     clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
 234
 235     /* Create slcr, keep a pointer to connect clocks */
 236     slcr = qdev_new("xilinx,zynq_slcr");
 237     qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
 238     sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
 239     sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
 240
 241     dev = qdev_new(TYPE_A9MPCORE_PRIV);
 242     qdev_prop_set_uint32(dev, "num-cpu", 1);
 243     busdev = SYS_BUS_DEVICE(dev);
 244     sysbus_realize_and_unref(busdev, &error_fatal);
 245     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 246     sysbus_connect_irq(busdev, 0,
 247                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 248
 249     for (n = 0; n < 64; n++) {
 250         pic[n] = qdev_get_gpio_in(dev, n);
 251     }
 252
 253     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
 254     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
 255     zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
 256
 257     sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
 258     sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
 259
 260     dev = qdev_new(TYPE_CADENCE_UART);
 261     busdev = SYS_BUS_DEVICE(dev);
 262     qdev_prop_set_chr(dev, "chardev", serial_hd(0));
 263     qdev_connect_clock_in(dev, "refclk",
 264                           qdev_get_clock_out(slcr, "uart0_ref_clk"));
 265     sysbus_realize_and_unref(busdev, &error_fatal);
 266     sysbus_mmio_map(busdev, 0, 0xE0000000);
 267     sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
 268     dev = qdev_new(TYPE_CADENCE_UART);
 269     busdev = SYS_BUS_DEVICE(dev);
 270     qdev_prop_set_chr(dev, "chardev", serial_hd(1));
 271     qdev_connect_clock_in(dev, "refclk",
 272                           qdev_get_clock_out(slcr, "uart1_ref_clk"));
 273     sysbus_realize_and_unref(busdev, &error_fatal);
 274     sysbus_mmio_map(busdev, 0, 0xE0001000);
 275     sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
 276
 277     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 278             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 279     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 280             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 281
 282     gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
 283     gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
 284
 285     for (n = 0; n < 2; n++) {
 286         int hci_irq = n ? 79 : 56;
 287         hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
 288         DriveInfo *di;
 289         BlockBackend *blk;
 290         DeviceState *carddev;
 291
 292         /* Compatible with:
 293          * - SD Host Controller Specification Version 2.0 Part A2
 294          * - SDIO Specification Version 2.0
 295          * - MMC Specification Version 3.31
 296          */
 297         dev = qdev_new(TYPE_SYSBUS_SDHCI);
 298         qdev_prop_set_uint8(dev, "sd-spec-version", 2);
 299         qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
 300         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 301         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
 302         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
 303
 304         di = drive_get_next(IF_SD);
 305         blk = di ? blk_by_legacy_dinfo(di) : NULL;
 306         carddev = qdev_new(TYPE_SD_CARD);
 307         qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
 308         qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
 309                                &error_fatal);
 310     }
 311
 312     dev = qdev_new(TYPE_ZYNQ_XADC);
 313     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 314     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
 315     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
 316
 317     dev = qdev_new("pl330");
 318     qdev_prop_set_uint8(dev, "num_chnls",  8);
 319     qdev_prop_set_uint8(dev, "num_periph_req",  4);
 320     qdev_prop_set_uint8(dev, "num_events",  16);
 321
 322     qdev_prop_set_uint8(dev, "data_width",  64);
 323     qdev_prop_set_uint8(dev, "wr_cap",  8);
 324     qdev_prop_set_uint8(dev, "wr_q_dep",  16);
 325     qdev_prop_set_uint8(dev, "rd_cap",  8);
 326     qdev_prop_set_uint8(dev, "rd_q_dep",  16);
 327     qdev_prop_set_uint16(dev, "data_buffer_dep",  256);
 328
 329     busdev = SYS_BUS_DEVICE(dev);
 330     sysbus_realize_and_unref(busdev, &error_fatal);
 331     sysbus_mmio_map(busdev, 0, 0xF8003000);
 332     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
 333     for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
 334         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
 335     }
 336
 337     dev = qdev_new("xlnx.ps7-dev-cfg");
 338     busdev = SYS_BUS_DEVICE(dev);
 339     sysbus_realize_and_unref(busdev, &error_fatal);
 340     sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
 341     sysbus_mmio_map(busdev, 0, 0xF8007000);
 342
 343     zynq_binfo.ram_size = machine->ram_size;
 344     zynq_binfo.nb_cpus = 1;
 345     zynq_binfo.board_id = 0xd32;
 346     zynq_binfo.loader_start = 0;
 347     zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 348     zynq_binfo.write_board_setup = zynq_write_board_setup;
 349
 350     arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
 351 }
 352
 353 static void zynq_machine_class_init(ObjectClass *oc, void *data)
 354 {
 355     MachineClass *mc = MACHINE_CLASS(oc);
 356     mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
 357     mc->init = zynq_init;
 358     mc->max_cpus = 1;
 359     mc->no_sdcard = 1;
 360     mc->ignore_memory_transaction_failures = true;
 361     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 362     mc->default_ram_id = "zynq.ext_ram";
 363 }
 364
 365 static const TypeInfo zynq_machine_type = {
 366     .name = TYPE_ZYNQ_MACHINE,
 367     .parent = TYPE_MACHINE,
 368     .class_init = zynq_machine_class_init,
 369     .instance_size = sizeof(ZynqMachineState),
 370 };
 371
 372 static void zynq_machine_register_types(void)
 373 {
 374     type_register_static(&zynq_machine_type);
 375 }
 376
 377 type_init(zynq_machine_register_types)