Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910...

This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
  hw/riscv: Sort the Kconfig options in alphabetical order
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: sifive_u: Connect a DMA controller
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/dma: Add SiFive platform DMA controller emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
#	hw/riscv/trace-events

diff --cc MAINTAINERS
Simple merge

diff --cc hw/arm/xilinx_zynq.c
Simple merge

diff --cc include/hw/net/cadence_gem.h
Simple merge

diff --cc include/hw/riscv/riscv_hart.h
index 9be1fd80ed8bdd6827f7fad409927096627d3b10,77aa4bc948b38eba2e183bcd51be58022cb71ec9..ac2cb62e1bbe7521b0494d6626d632da2d3fd3a0
--- 1/include/hw/riscv/riscv_hart.h
--- 2/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@@ -39,7 -37,8 +39,8 @@@ struct RISCVHartArrayState 
      uint32_t num_harts;
      uint32_t hartid_base;
      char *cpu_type;
+     uint64_t resetvec;
      RISCVCPU *harts;
 -} RISCVHartArrayState;
 +};
  
  #endif

diff --cc meson.build
index bd84a1e7770de9badf359f9e906d139c44c7a87e,bc869c676af6752d8662ff71d4891c6683bd4c72..690723b470894b292cbb83ef3ff7eee64be524b1
--- 1/meson.build
--- 2/meson.build
+++ b/meson.build
@@@ -773,10 -773,8 +773,9 @@@ if have_syste
      'hw/watchdog',
      'hw/xen',
      'hw/gpio',
-     'hw/riscv',
      'migration',
      'net',
 +    'softmmu',
      'ui',
    ]
  endif

diff --cc target/riscv/cpu.h
index ca75fc761ef9b79ea02385dcbe30bd08f26964fd,65daa7367535c7634f3b4321f74405b47d130142..4c00d35ccddeff24cbd67d0be6e4c2912093d109
--- 1/target/riscv/cpu.h
--- 2/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@@ -288,8 -292,9 +289,9 @@@ struct RISCVCPU 
          uint16_t elen;
          bool mmu;
          bool pmp;
+         uint64_t resetvec;
      } cfg;
 -} RISCVCPU;
 +};
  
  static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
  {