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qdev: set properties with device_class_set_props()
[thirdparty/qemu.git] / hw / ppc / pnv_psi.c
1 /*
2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
3 *
4 * Copyright (c) 2015-2017, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "target/ppc/cpu.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "sysemu/reset.h"
26 #include "qapi/error.h"
27 #include "monitor/monitor.h"
28
29 #include "exec/address-spaces.h"
30
31 #include "hw/ppc/fdt.h"
32 #include "hw/ppc/pnv.h"
33 #include "hw/ppc/pnv_xscom.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/ppc/pnv_psi.h"
36
37 #include <libfdt.h>
38
39 #define PSIHB_XSCOM_FIR_RW 0x00
40 #define PSIHB_XSCOM_FIR_AND 0x01
41 #define PSIHB_XSCOM_FIR_OR 0x02
42 #define PSIHB_XSCOM_FIRMASK_RW 0x03
43 #define PSIHB_XSCOM_FIRMASK_AND 0x04
44 #define PSIHB_XSCOM_FIRMASK_OR 0x05
45 #define PSIHB_XSCOM_FIRACT0 0x06
46 #define PSIHB_XSCOM_FIRACT1 0x07
47
48 /* Host Bridge Base Address Register */
49 #define PSIHB_XSCOM_BAR 0x0a
50 #define PSIHB_BAR_EN 0x0000000000000001ull
51
52 /* FSP Base Address Register */
53 #define PSIHB_XSCOM_FSPBAR 0x0b
54
55 /* PSI Host Bridge Control/Status Register */
56 #define PSIHB_XSCOM_CR 0x0e
57 #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull
58 #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull
59 #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull
60 #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull
61 #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull
62 #define PSIHB_CR_FSP_RESET 0x0200000000000000ull
63 #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull
64 #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull
65 #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull
66 #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull
67 #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull
68 /* and more ... */
69
70 /* PSIHB Status / Error Mask Register */
71 #define PSIHB_XSCOM_SEMR 0x0f
72
73 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
74 #define PSIHB_XSCOM_XIVR_FSP 0x10
75 #define PSIHB_XIVR_SERVER_SH 40
76 #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH)
77 #define PSIHB_XIVR_PRIO_SH 32
78 #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH)
79 #define PSIHB_XIVR_SRC_SH 29
80 #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH)
81 #define PSIHB_XIVR_PENDING 0x01000000ull
82
83 /* PSI Host Bridge Set Control/ Status Register */
84 #define PSIHB_XSCOM_SCR 0x12
85
86 /* PSI Host Bridge Clear Control/ Status Register */
87 #define PSIHB_XSCOM_CCR 0x13
88
89 /* DMA Upper Address Register */
90 #define PSIHB_XSCOM_DMA_UPADD 0x14
91
92 /* Interrupt Status */
93 #define PSIHB_XSCOM_IRQ_STAT 0x15
94 #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull
95 #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull
96 #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull
97 #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull
98 #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull
99
100 /* remaining XIVR */
101 #define PSIHB_XSCOM_XIVR_OCC 0x16
102 #define PSIHB_XSCOM_XIVR_FSI 0x17
103 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
104 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
105 #define PSIHB_XSCOM_XIVR_EXT 0x1a
106
107 /* Interrupt Requester Source Compare Register */
108 #define PSIHB_XSCOM_IRSN 0x1b
109 #define PSIHB_IRSN_COMP_SH 45
110 #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH)
111 #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull
112 #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull
113 #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull
114 #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull
115 #define PSIHB_IRSN_COMPMASK_SH 13
116 #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
117
118 #define PSIHB_BAR_MASK 0x0003fffffff00000ull
119 #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull
120
121 #define PSIHB9_BAR_MASK 0x00fffffffff00000ull
122 #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull
123
124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
125
126 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
127 {
128 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
129 MemoryRegion *sysmem = get_system_memory();
130 uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
131
132 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
133
134 /* Update MR, always remove it first */
135 if (old & PSIHB_BAR_EN) {
136 memory_region_del_subregion(sysmem, &psi->regs_mr);
137 }
138
139 /* Then add it back if needed */
140 if (bar & PSIHB_BAR_EN) {
141 uint64_t addr = bar & ppc->bar_mask;
142 memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
143 }
144 }
145
146 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
147 {
148 /* TODO: Update FSP MR if/when we support FSP BAR */
149 }
150
151 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
152 {
153 uint64_t old = psi->regs[PSIHB_XSCOM_CR];
154
155 psi->regs[PSIHB_XSCOM_CR] = cr;
156
157 /* Check some bit changes */
158 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
159 pnv_psi_update_fsp_mr(psi);
160 }
161 }
162
163 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
164 {
165 ICSState *ics = &PNV8_PSI(psi)->ics;
166
167 /* In this model we ignore the up/down enable bits for now
168 * as SW doesn't use them (other than setting them at boot).
169 * We ignore IRQ_MUX, its meaning isn't clear and we don't use
170 * it and finally we ignore reset (XXX fix that ?)
171 */
172 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
173 PSIHB_IRSN_IRQ_MUX |
174 PSIHB_IRSN_IRQ_RESET |
175 PSIHB_IRSN_DOWNSTREAM_EN |
176 PSIHB_IRSN_UPSTREAM_EN);
177
178 /* We ignore the compare mask as well, our ICS emulation is too
179 * simplistic to make any use if it, and we extract the offset
180 * from the compare value
181 */
182 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
183 }
184
185 /*
186 * FSP and PSI interrupts are muxed under the same number.
187 */
188 static const uint32_t xivr_regs[] = {
189 [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
190 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
191 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
192 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
193 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C,
194 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
195 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
196 };
197
198 static const uint32_t stat_regs[] = {
199 [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
200 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
201 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
202 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
203 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT,
204 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
205 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
206 };
207
208 static const uint64_t stat_bits[] = {
209 [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
210 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
211 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
212 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
213 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C,
214 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
215 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
216 };
217
218 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
219 {
220 PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
221 }
222
223 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
224 {
225 uint32_t xivr_reg;
226 uint32_t stat_reg;
227 uint32_t src;
228 bool masked;
229
230 if (irq > PSIHB_IRQ_EXTERNAL) {
231 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
232 return;
233 }
234
235 xivr_reg = xivr_regs[irq];
236 stat_reg = stat_regs[irq];
237
238 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
239 if (state) {
240 psi->regs[stat_reg] |= stat_bits[irq];
241 /* TODO: optimization, check mask here. That means
242 * re-evaluating when unmasking
243 */
244 qemu_irq_raise(psi->qirqs[src]);
245 } else {
246 psi->regs[stat_reg] &= ~stat_bits[irq];
247
248 /* FSP and PSI are muxed so don't lower if either is still set */
249 if (stat_reg != PSIHB_XSCOM_CR ||
250 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
251 qemu_irq_lower(psi->qirqs[src]);
252 } else {
253 state = true;
254 }
255 }
256
257 /* Note about the emulation of the pending bit: This isn't
258 * entirely correct. The pending bit should be cleared when the
259 * EOI has been received. However, we don't have callbacks on EOI
260 * (especially not under KVM) so no way to emulate that properly,
261 * so instead we just set that bit as the logical "output" of the
262 * XIVR (ie pending & !masked)
263 *
264 * CLG: We could define a new ICS object with a custom eoi()
265 * handler to clear the pending bit. But I am not sure this would
266 * be useful for the software anyhow.
267 */
268 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
269 if (state && !masked) {
270 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
271 } else {
272 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
273 }
274 }
275
276 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
277 {
278 ICSState *ics = &PNV8_PSI(psi)->ics;
279 uint16_t server;
280 uint8_t prio;
281 uint8_t src;
282
283 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
284 (val & (PSIHB_XIVR_SERVER_MSK |
285 PSIHB_XIVR_PRIO_MSK |
286 PSIHB_XIVR_SRC_MSK));
287 val = psi->regs[reg];
288 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
289 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
290 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
291
292 if (src >= PSI_NUM_INTERRUPTS) {
293 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
294 return;
295 }
296
297 /* Remove pending bit if the IRQ is masked */
298 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
299 psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
300 }
301
302 /* The low order 2 bits are the link pointer (Type II interrupts).
303 * Shift back to get a valid IRQ server.
304 */
305 server >>= 2;
306
307 /* Now because of source remapping, weird things can happen
308 * if you change the source number dynamically, our simple ICS
309 * doesn't deal with remapping. So we just poke a different
310 * ICS entry based on what source number was written. This will
311 * do for now but a more accurate implementation would instead
312 * use a fixed server/prio and a remapper of the generated irq.
313 */
314 ics_write_xive(ics, src, server, prio, prio);
315 }
316
317 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
318 {
319 uint64_t val = 0xffffffffffffffffull;
320
321 switch (offset) {
322 case PSIHB_XSCOM_FIR_RW:
323 case PSIHB_XSCOM_FIRACT0:
324 case PSIHB_XSCOM_FIRACT1:
325 case PSIHB_XSCOM_BAR:
326 case PSIHB_XSCOM_FSPBAR:
327 case PSIHB_XSCOM_CR:
328 case PSIHB_XSCOM_XIVR_FSP:
329 case PSIHB_XSCOM_XIVR_OCC:
330 case PSIHB_XSCOM_XIVR_FSI:
331 case PSIHB_XSCOM_XIVR_LPCI2C:
332 case PSIHB_XSCOM_XIVR_LOCERR:
333 case PSIHB_XSCOM_XIVR_EXT:
334 case PSIHB_XSCOM_IRQ_STAT:
335 case PSIHB_XSCOM_SEMR:
336 case PSIHB_XSCOM_DMA_UPADD:
337 case PSIHB_XSCOM_IRSN:
338 val = psi->regs[offset];
339 break;
340 default:
341 qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
342 }
343 return val;
344 }
345
346 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
347 bool mmio)
348 {
349 switch (offset) {
350 case PSIHB_XSCOM_FIR_RW:
351 case PSIHB_XSCOM_FIRACT0:
352 case PSIHB_XSCOM_FIRACT1:
353 case PSIHB_XSCOM_SEMR:
354 case PSIHB_XSCOM_DMA_UPADD:
355 psi->regs[offset] = val;
356 break;
357 case PSIHB_XSCOM_FIR_OR:
358 psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
359 break;
360 case PSIHB_XSCOM_FIR_AND:
361 psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
362 break;
363 case PSIHB_XSCOM_BAR:
364 /* Only XSCOM can write this one */
365 if (!mmio) {
366 pnv_psi_set_bar(psi, val);
367 } else {
368 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
369 }
370 break;
371 case PSIHB_XSCOM_FSPBAR:
372 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
373 pnv_psi_update_fsp_mr(psi);
374 break;
375 case PSIHB_XSCOM_CR:
376 pnv_psi_set_cr(psi, val);
377 break;
378 case PSIHB_XSCOM_SCR:
379 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
380 break;
381 case PSIHB_XSCOM_CCR:
382 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
383 break;
384 case PSIHB_XSCOM_XIVR_FSP:
385 case PSIHB_XSCOM_XIVR_OCC:
386 case PSIHB_XSCOM_XIVR_FSI:
387 case PSIHB_XSCOM_XIVR_LPCI2C:
388 case PSIHB_XSCOM_XIVR_LOCERR:
389 case PSIHB_XSCOM_XIVR_EXT:
390 pnv_psi_set_xivr(psi, offset, val);
391 break;
392 case PSIHB_XSCOM_IRQ_STAT:
393 /* Read only */
394 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
395 break;
396 case PSIHB_XSCOM_IRSN:
397 pnv_psi_set_irsn(psi, val);
398 break;
399 default:
400 qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
401 }
402 }
403
404 /*
405 * The values of the registers when accessed through the MMIO region
406 * follow the relation : xscom = (mmio + 0x50) >> 3
407 */
408 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
409 {
410 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
411 }
412
413 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
414 uint64_t val, unsigned size)
415 {
416 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
417 }
418
419 static const MemoryRegionOps psi_mmio_ops = {
420 .read = pnv_psi_mmio_read,
421 .write = pnv_psi_mmio_write,
422 .endianness = DEVICE_BIG_ENDIAN,
423 .valid = {
424 .min_access_size = 8,
425 .max_access_size = 8,
426 },
427 .impl = {
428 .min_access_size = 8,
429 .max_access_size = 8,
430 },
431 };
432
433 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
434 {
435 return pnv_psi_reg_read(opaque, addr >> 3, false);
436 }
437
438 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
439 uint64_t val, unsigned size)
440 {
441 pnv_psi_reg_write(opaque, addr >> 3, val, false);
442 }
443
444 static const MemoryRegionOps pnv_psi_xscom_ops = {
445 .read = pnv_psi_xscom_read,
446 .write = pnv_psi_xscom_write,
447 .endianness = DEVICE_BIG_ENDIAN,
448 .valid = {
449 .min_access_size = 8,
450 .max_access_size = 8,
451 },
452 .impl = {
453 .min_access_size = 8,
454 .max_access_size = 8,
455 }
456 };
457
458 static void pnv_psi_reset(DeviceState *dev)
459 {
460 PnvPsi *psi = PNV_PSI(dev);
461
462 memset(psi->regs, 0x0, sizeof(psi->regs));
463
464 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
465 }
466
467 static void pnv_psi_reset_handler(void *dev)
468 {
469 device_reset(DEVICE(dev));
470 }
471
472 static void pnv_psi_realize(DeviceState *dev, Error **errp)
473 {
474 PnvPsi *psi = PNV_PSI(dev);
475
476 /* Default BAR for MMIO region */
477 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
478
479 qemu_register_reset(pnv_psi_reset_handler, dev);
480 }
481
482 static void pnv_psi_power8_instance_init(Object *obj)
483 {
484 Pnv8Psi *psi8 = PNV8_PSI(obj);
485
486 object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics),
487 TYPE_ICS, &error_abort, NULL);
488 object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),
489 ICS_PROP_XICS, &error_abort);
490 }
491
492 static const uint8_t irq_to_xivr[] = {
493 PSIHB_XSCOM_XIVR_FSP,
494 PSIHB_XSCOM_XIVR_OCC,
495 PSIHB_XSCOM_XIVR_FSI,
496 PSIHB_XSCOM_XIVR_LPCI2C,
497 PSIHB_XSCOM_XIVR_LOCERR,
498 PSIHB_XSCOM_XIVR_EXT,
499 };
500
501 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
502 {
503 PnvPsi *psi = PNV_PSI(dev);
504 ICSState *ics = &PNV8_PSI(psi)->ics;
505 Error *err = NULL;
506 unsigned int i;
507
508 /* Create PSI interrupt control source */
509 object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
510 if (err) {
511 error_propagate(errp, err);
512 return;
513 }
514 object_property_set_bool(OBJECT(ics), true, "realized", &err);
515 if (err) {
516 error_propagate(errp, err);
517 return;
518 }
519
520 for (i = 0; i < ics->nr_irqs; i++) {
521 ics_set_irq_type(ics, i, true);
522 }
523
524 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
525
526 /* XSCOM region for PSI registers */
527 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
528 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
529
530 /* Initialize MMIO region */
531 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
532 "psihb", PNV_PSIHB_SIZE);
533
534 /* Default sources in XIVR */
535 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
536 uint8_t xivr = irq_to_xivr[i];
537 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
538 ((uint64_t) i << PSIHB_XIVR_SRC_SH);
539 }
540
541 pnv_psi_realize(dev, errp);
542 }
543
544 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
545 {
546 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
547 char *name;
548 int offset;
549 uint32_t reg[] = {
550 cpu_to_be32(ppc->xscom_pcba),
551 cpu_to_be32(ppc->xscom_size)
552 };
553
554 name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
555 offset = fdt_add_subnode(fdt, xscom_offset, name);
556 _FDT(offset);
557 g_free(name);
558
559 _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
560 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
561 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
562 _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat,
563 ppc->compat_size));
564 return 0;
565 }
566
567 static Property pnv_psi_properties[] = {
568 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
569 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
570 DEFINE_PROP_END_OF_LIST(),
571 };
572
573 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
574 {
575 DeviceClass *dc = DEVICE_CLASS(klass);
576 PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
577 static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
578
579 dc->desc = "PowerNV PSI Controller POWER8";
580 dc->realize = pnv_psi_power8_realize;
581
582 ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
583 ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
584 ppc->bar_mask = PSIHB_BAR_MASK;
585 ppc->irq_set = pnv_psi_power8_irq_set;
586 ppc->compat = compat;
587 ppc->compat_size = sizeof(compat);
588 }
589
590 static const TypeInfo pnv_psi_power8_info = {
591 .name = TYPE_PNV8_PSI,
592 .parent = TYPE_PNV_PSI,
593 .instance_size = sizeof(Pnv8Psi),
594 .instance_init = pnv_psi_power8_instance_init,
595 .class_init = pnv_psi_power8_class_init,
596 };
597
598
599 /* Common registers */
600
601 #define PSIHB9_CR 0x20
602 #define PSIHB9_SEMR 0x28
603
604 /* P9 registers */
605
606 #define PSIHB9_INTERRUPT_CONTROL 0x58
607 #define PSIHB9_IRQ_METHOD PPC_BIT(0)
608 #define PSIHB9_IRQ_RESET PPC_BIT(1)
609 #define PSIHB9_ESB_CI_BASE 0x60
610 #define PSIHB9_ESB_CI_64K PPC_BIT(1)
611 #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47)
612 #define PSIHB9_ESB_CI_VALID PPC_BIT(63)
613 #define PSIHB9_ESB_NOTIF_ADDR 0x68
614 #define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60)
615 #define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63)
616 #define PSIHB9_IVT_OFFSET 0x70
617 #define PSIHB9_IVT_OFF_SHIFT 32
618
619 #define PSIHB9_IRQ_LEVEL 0x78 /* assertion */
620 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0)
621 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1)
622 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2)
623 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3)
624 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4)
625 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5)
626 #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6)
627 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7)
628 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8)
629 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9)
630 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10)
631 #define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11)
632 #define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12)
633 #define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13)
634 #define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14)
635 #define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15)
636 #define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16)
637 #define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19)
638
639 #define PSIHB9_IRQ_STAT 0x80 /* P bit */
640 #define PSIHB9_IRQ_STAT_PSI PPC_BIT(0)
641 #define PSIHB9_IRQ_STAT_OCC PPC_BIT(1)
642 #define PSIHB9_IRQ_STAT_FSI PPC_BIT(2)
643 #define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3)
644 #define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4)
645 #define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5)
646 #define PSIHB9_IRQ_STAT_TPM PPC_BIT(6)
647 #define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7)
648 #define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8)
649 #define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9)
650 #define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10)
651 #define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11)
652 #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12)
653 #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13)
654
655 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
656 {
657 PnvPsi *psi = PNV_PSI(xf);
658 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
659 bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
660 uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
661
662 uint32_t offset =
663 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
664 uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
665 MemTxResult result;
666
667 if (!valid) {
668 return;
669 }
670
671 address_space_stq_be(&address_space_memory, notify_addr, data,
672 MEMTXATTRS_UNSPECIFIED, &result);
673 if (result != MEMTX_OK) {
674 qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
675 HWADDR_PRIx "\n", __func__, notif_port);
676 return;
677 }
678 }
679
680 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
681 {
682 PnvPsi *psi = PNV_PSI(opaque);
683 uint32_t reg = PSIHB_REG(addr);
684 uint64_t val = -1;
685
686 switch (addr) {
687 case PSIHB9_CR:
688 case PSIHB9_SEMR:
689 /* FSP stuff */
690 case PSIHB9_INTERRUPT_CONTROL:
691 case PSIHB9_ESB_CI_BASE:
692 case PSIHB9_ESB_NOTIF_ADDR:
693 case PSIHB9_IVT_OFFSET:
694 val = psi->regs[reg];
695 break;
696 default:
697 qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
698 }
699
700 return val;
701 }
702
703 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
704 uint64_t val, unsigned size)
705 {
706 PnvPsi *psi = PNV_PSI(opaque);
707 Pnv9Psi *psi9 = PNV9_PSI(psi);
708 uint32_t reg = PSIHB_REG(addr);
709 MemoryRegion *sysmem = get_system_memory();
710
711 switch (addr) {
712 case PSIHB9_CR:
713 case PSIHB9_SEMR:
714 /* FSP stuff */
715 break;
716 case PSIHB9_INTERRUPT_CONTROL:
717 if (val & PSIHB9_IRQ_RESET) {
718 device_reset(DEVICE(&psi9->source));
719 }
720 psi->regs[reg] = val;
721 break;
722
723 case PSIHB9_ESB_CI_BASE:
724 if (!(val & PSIHB9_ESB_CI_VALID)) {
725 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
726 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
727 }
728 } else {
729 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
730 memory_region_add_subregion(sysmem,
731 val & ~PSIHB9_ESB_CI_VALID,
732 &psi9->source.esb_mmio);
733 }
734 }
735 psi->regs[reg] = val;
736 break;
737
738 case PSIHB9_ESB_NOTIF_ADDR:
739 psi->regs[reg] = val;
740 break;
741 case PSIHB9_IVT_OFFSET:
742 psi->regs[reg] = val;
743 break;
744 default:
745 qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
746 }
747 }
748
749 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
750 .read = pnv_psi_p9_mmio_read,
751 .write = pnv_psi_p9_mmio_write,
752 .endianness = DEVICE_BIG_ENDIAN,
753 .valid = {
754 .min_access_size = 8,
755 .max_access_size = 8,
756 },
757 .impl = {
758 .min_access_size = 8,
759 .max_access_size = 8,
760 },
761 };
762
763 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
764 {
765 /* No read are expected */
766 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
767 return -1;
768 }
769
770 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
771 uint64_t val, unsigned size)
772 {
773 PnvPsi *psi = PNV_PSI(opaque);
774
775 /* XSCOM is only used to set the PSIHB MMIO region */
776 switch (addr >> 3) {
777 case PSIHB_XSCOM_BAR:
778 pnv_psi_set_bar(psi, val);
779 break;
780 default:
781 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
782 addr);
783 }
784 }
785
786 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
787 .read = pnv_psi_p9_xscom_read,
788 .write = pnv_psi_p9_xscom_write,
789 .endianness = DEVICE_BIG_ENDIAN,
790 .valid = {
791 .min_access_size = 8,
792 .max_access_size = 8,
793 },
794 .impl = {
795 .min_access_size = 8,
796 .max_access_size = 8,
797 }
798 };
799
800 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
801 {
802 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
803
804 if (irq > PSIHB9_NUM_IRQS) {
805 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
806 return;
807 }
808
809 if (irq_method & PSIHB9_IRQ_METHOD) {
810 qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
811 return;
812 }
813
814 /* Update LSI levels */
815 if (state) {
816 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
817 } else {
818 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
819 }
820
821 qemu_set_irq(psi->qirqs[irq], state);
822 }
823
824 static void pnv_psi_power9_reset(DeviceState *dev)
825 {
826 Pnv9Psi *psi = PNV9_PSI(dev);
827
828 pnv_psi_reset(dev);
829
830 if (memory_region_is_mapped(&psi->source.esb_mmio)) {
831 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
832 }
833 }
834
835 static void pnv_psi_power9_instance_init(Object *obj)
836 {
837 Pnv9Psi *psi = PNV9_PSI(obj);
838
839 object_initialize_child(obj, "source", &psi->source, sizeof(psi->source),
840 TYPE_XIVE_SOURCE, &error_abort, NULL);
841 }
842
843 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
844 {
845 PnvPsi *psi = PNV_PSI(dev);
846 XiveSource *xsrc = &PNV9_PSI(psi)->source;
847 Error *local_err = NULL;
848 int i;
849
850 /* This is the only device with 4k ESB pages */
851 object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
852 &error_fatal);
853 object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
854 &error_fatal);
855 object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort);
856 object_property_set_bool(OBJECT(xsrc), true, "realized", &local_err);
857 if (local_err) {
858 error_propagate(errp, local_err);
859 return;
860 }
861
862 for (i = 0; i < xsrc->nr_irqs; i++) {
863 xive_source_irq_set_lsi(xsrc, i);
864 }
865
866 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
867
868 /* XSCOM region for PSI registers */
869 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
870 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
871
872 /* MMIO region for PSI registers */
873 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
874 "psihb", PNV9_PSIHB_SIZE);
875
876 pnv_psi_realize(dev, errp);
877 }
878
879 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
880 {
881 DeviceClass *dc = DEVICE_CLASS(klass);
882 PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
883 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
884 static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x";
885
886 dc->desc = "PowerNV PSI Controller POWER9";
887 dc->realize = pnv_psi_power9_realize;
888 dc->reset = pnv_psi_power9_reset;
889
890 ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
891 ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
892 ppc->bar_mask = PSIHB9_BAR_MASK;
893 ppc->irq_set = pnv_psi_power9_irq_set;
894 ppc->compat = compat;
895 ppc->compat_size = sizeof(compat);
896
897 xfc->notify = pnv_psi_notify;
898 }
899
900 static const TypeInfo pnv_psi_power9_info = {
901 .name = TYPE_PNV9_PSI,
902 .parent = TYPE_PNV_PSI,
903 .instance_size = sizeof(Pnv9Psi),
904 .instance_init = pnv_psi_power9_instance_init,
905 .class_init = pnv_psi_power9_class_init,
906 .interfaces = (InterfaceInfo[]) {
907 { TYPE_XIVE_NOTIFIER },
908 { },
909 },
910 };
911
912 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
913 {
914 DeviceClass *dc = DEVICE_CLASS(klass);
915 PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
916 static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x";
917
918 dc->desc = "PowerNV PSI Controller POWER10";
919
920 ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
921 ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
922 ppc->compat = compat;
923 ppc->compat_size = sizeof(compat);
924 }
925
926 static const TypeInfo pnv_psi_power10_info = {
927 .name = TYPE_PNV10_PSI,
928 .parent = TYPE_PNV9_PSI,
929 .class_init = pnv_psi_power10_class_init,
930 };
931
932 static void pnv_psi_class_init(ObjectClass *klass, void *data)
933 {
934 DeviceClass *dc = DEVICE_CLASS(klass);
935 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
936
937 xdc->dt_xscom = pnv_psi_dt_xscom;
938
939 dc->desc = "PowerNV PSI Controller";
940 device_class_set_props(dc, pnv_psi_properties);
941 dc->reset = pnv_psi_reset;
942 }
943
944 static const TypeInfo pnv_psi_info = {
945 .name = TYPE_PNV_PSI,
946 .parent = TYPE_SYS_BUS_DEVICE,
947 .instance_size = sizeof(PnvPsi),
948 .class_init = pnv_psi_class_init,
949 .class_size = sizeof(PnvPsiClass),
950 .abstract = true,
951 .interfaces = (InterfaceInfo[]) {
952 { TYPE_PNV_XSCOM_INTERFACE },
953 { }
954 }
955 };
956
957 static void pnv_psi_register_types(void)
958 {
959 type_register_static(&pnv_psi_info);
960 type_register_static(&pnv_psi_power8_info);
961 type_register_static(&pnv_psi_power9_info);
962 type_register_static(&pnv_psi_power10_info);
963 }
964
965 type_init(pnv_psi_register_types);
966
967 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
968 {
969 PnvPsi *psi = PNV_PSI(psi9);
970
971 uint32_t offset =
972 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
973
974 monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
975 offset, offset + psi9->source.nr_irqs - 1);
976 xive_source_pic_print_info(&psi9->source, offset, mon);
977 }
Mirror of https://git.qemu.org/git/qemu.git