sim/bfin/dv-bfin_pll.c

   1 /* Blackfin Phase Lock Loop (PLL) model.
   2
   3    Copyright (C) 2010-2021 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "machs.h"
  26 #include "devices.h"
  27 #include "dv-bfin_pll.h"
  28
  29 struct bfin_pll
  30 {
  31   bu32 base;
  32
  33   /* Order after here is important -- matches hardware MMR layout.  */
  34   bu16 BFIN_MMR_16(pll_ctl);
  35   bu16 BFIN_MMR_16(pll_div);
  36   bu16 BFIN_MMR_16(vr_ctl);
  37   bu16 BFIN_MMR_16(pll_stat);
  38   bu16 BFIN_MMR_16(pll_lockcnt);
  39
  40   /* XXX: Not really the best place for this ...  */
  41   bu32 chipid;
  42 };
  43 #define mmr_base()      offsetof(struct bfin_pll, pll_ctl)
  44 #define mmr_offset(mmr) (offsetof(struct bfin_pll, mmr) - mmr_base())
  45
  46 static const char * const mmr_names[] =
  47 {
  48   "PLL_CTL", "PLL_DIV", "VR_CTL", "PLL_STAT", "PLL_LOCKCNT", "CHIPID",
  49 };
  50 #define mmr_name(off) mmr_names[(off) / 4]
  51
  52 static unsigned
  53 bfin_pll_io_write_buffer (struct hw *me, const void *source,
  54                           int space, address_word addr, unsigned nr_bytes)
  55 {
  56   struct bfin_pll *pll = hw_data (me);
  57   bu32 mmr_off;
  58   bu32 value;
  59   bu16 *value16p;
  60   bu32 *value32p;
  61   void *valuep;
  62
  63   /* Invalid access mode is higher priority than missing register.  */
  64   if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
  65     return 0;
  66
  67   if (nr_bytes == 4)
  68     value = dv_load_4 (source);
  69   else
  70     value = dv_load_2 (source);
  71
  72   mmr_off = addr - pll->base;
  73   valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
  74   value16p = valuep;
  75   value32p = valuep;
  76
  77   HW_TRACE_WRITE ();
  78
  79   switch (mmr_off)
  80     {
  81     case mmr_offset(pll_stat):
  82       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
  83         return 0;
  84     case mmr_offset(chipid):
  85       /* Discard writes.  */
  86       break;
  87     default:
  88       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
  89         return 0;
  90       *value16p = value;
  91       break;
  92     }
  93
  94   return nr_bytes;
  95 }
  96
  97 static unsigned
  98 bfin_pll_io_read_buffer (struct hw *me, void *dest,
  99                          int space, address_word addr, unsigned nr_bytes)
 100 {
 101   struct bfin_pll *pll = hw_data (me);
 102   bu32 mmr_off;
 103   bu32 *value32p;
 104   bu16 *value16p;
 105   void *valuep;
 106
 107   /* Invalid access mode is higher priority than missing register.  */
 108   if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
 109     return 0;
 110
 111   mmr_off = addr - pll->base;
 112   valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
 113   value16p = valuep;
 114   value32p = valuep;
 115
 116   HW_TRACE_READ ();
 117
 118   switch (mmr_off)
 119     {
 120     case mmr_offset(chipid):
 121       dv_store_4 (dest, *value32p);
 122       break;
 123     default:
 124       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
 125         return 0;
 126       dv_store_2 (dest, *value16p);
 127       break;
 128     }
 129
 130   return nr_bytes;
 131 }
 132
 133 static const struct hw_port_descriptor bfin_pll_ports[] =
 134 {
 135   { "pll", 0, 0, output_port, },
 136   { NULL, 0, 0, 0, },
 137 };
 138
 139 static void
 140 attach_bfin_pll_regs (struct hw *me, struct bfin_pll *pll)
 141 {
 142   address_word attach_address;
 143   int attach_space;
 144   unsigned attach_size;
 145   reg_property_spec reg;
 146
 147   if (hw_find_property (me, "reg") == NULL)
 148     hw_abort (me, "Missing \"reg\" property");
 149
 150   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 151     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 152
 153   hw_unit_address_to_attach_address (hw_parent (me),
 154                                      &reg.address,
 155                                      &attach_space, &attach_address, me);
 156   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 157
 158   if (attach_size != BFIN_MMR_PLL_SIZE)
 159     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_PLL_SIZE);
 160
 161   hw_attach_address (hw_parent (me),
 162                      0, attach_space, attach_address, attach_size, me);
 163
 164   pll->base = attach_address;
 165 }
 166
 167 static void
 168 bfin_pll_finish (struct hw *me)
 169 {
 170   struct bfin_pll *pll;
 171
 172   pll = HW_ZALLOC (me, struct bfin_pll);
 173
 174   set_hw_data (me, pll);
 175   set_hw_io_read_buffer (me, bfin_pll_io_read_buffer);
 176   set_hw_io_write_buffer (me, bfin_pll_io_write_buffer);
 177   set_hw_ports (me, bfin_pll_ports);
 178
 179   attach_bfin_pll_regs (me, pll);
 180
 181   /* Initialize the PLL.  */
 182   /* XXX: Depends on part ?  */
 183   pll->pll_ctl = 0x1400;
 184   pll->pll_div = 0x0005;
 185   pll->vr_ctl = 0x40DB;
 186   pll->pll_stat = 0x00A2;
 187   pll->pll_lockcnt = 0x0200;
 188   pll->chipid = bfin_model_get_chipid (hw_system (me));
 189
 190   /* XXX: slow it down!  */
 191   pll->pll_ctl = 0xa800;
 192   pll->pll_div = 0x4;
 193   pll->vr_ctl = 0x40fb;
 194   pll->pll_stat = 0xa2;
 195   pll->pll_lockcnt = 0x300;
 196 }
 197
 198 const struct hw_descriptor dv_bfin_pll_descriptor[] =
 199 {
 200   {"bfin_pll", bfin_pll_finish,},
 201   {NULL, NULL},
 202 };