]>
git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/d10v/interp.c
1 /* This must come before any other includes. */
7 #include "sim/callback.h"
11 #include "sim-options.h"
13 #include "gdb/sim-d10v.h"
14 #include "gdb/signals.h"
20 enum _leftright
{ LEFT_FIRST
, RIGHT_FIRST
};
26 /* Set this to true to get the previous segment layout. */
28 int old_segment_mapping
;
30 unsigned long ins_type_counters
[ (int)INS_MAX
];
34 static long hash (long insn
, int format
);
35 static struct hash_entry
*lookup_hash (SIM_DESC
, SIM_CPU
*, uint32 ins
, int size
);
36 static void get_operands (struct simops
*s
, uint32 ins
);
37 static void do_long (SIM_DESC
, SIM_CPU
*, uint32 ins
);
38 static void do_2_short (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
, enum _leftright leftright
);
39 static void do_parallel (SIM_DESC
, SIM_CPU
*, uint16 ins1
, uint16 ins2
);
40 static char *add_commas (char *buf
, int sizeof_buf
, unsigned long value
);
41 static INLINE uint8
*map_memory (SIM_DESC
, SIM_CPU
*, unsigned phys_addr
);
46 struct hash_entry
*next
;
53 struct hash_entry hash_table
[MAX_HASH
+1];
56 hash (long insn
, int format
)
58 if (format
& LONG_OPCODE
)
59 return ((insn
& 0x3F000000) >> 24);
61 return((insn
& 0x7E00) >> 9);
64 INLINE
static struct hash_entry
*
65 lookup_hash (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
, int size
)
70 h
= &hash_table
[(ins
& 0x3F000000) >> 24];
72 h
= &hash_table
[(ins
& 0x7E00) >> 9];
74 while ((ins
& h
->mask
) != h
->opcode
|| h
->size
!= size
)
77 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGILL
);
84 get_operands (struct simops
*s
, uint32 ins
)
86 int i
, shift
, bits
, flags
;
88 for (i
=0; i
< s
->numops
; i
++)
90 shift
= s
->operands
[3*i
];
91 bits
= s
->operands
[3*i
+1];
92 flags
= s
->operands
[3*i
+2];
93 mask
= 0x7FFFFFFF >> (31 - bits
);
94 OP
[i
] = (ins
>> shift
) & mask
;
96 /* FIXME: for tracing, update values that need to be updated each
97 instruction decode cycle */
98 State
.trace
.psw
= PSW
;
102 do_long (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 ins
)
104 struct hash_entry
*h
;
106 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
107 sim_io_printf (sd
, "do_long 0x%x\n", ins
);
109 h
= lookup_hash (sd
, cpu
, ins
, 1);
112 get_operands (h
->ops
, ins
);
113 State
.ins_type
= INS_LONG
;
114 ins_type_counters
[ (int)State
.ins_type
]++;
115 (h
->ops
->func
) (sd
, cpu
);
119 do_2_short (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
, enum _leftright leftright
)
121 struct hash_entry
*h
;
122 enum _ins_type first
, second
;
125 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
126 sim_io_printf (sd
, "do_2_short 0x%x (%s) -> 0x%x\n", ins1
,
127 leftright
? "left" : "right", ins2
);
130 if (leftright
== LEFT_FIRST
)
134 ins_type_counters
[ (int)INS_LEFTRIGHT
]++;
140 ins_type_counters
[ (int)INS_RIGHTLEFT
]++;
143 /* Issue the first instruction */
144 h
= lookup_hash (sd
, cpu
, ins1
, 0);
147 get_operands (h
->ops
, ins1
);
148 State
.ins_type
= first
;
149 ins_type_counters
[ (int)State
.ins_type
]++;
150 (h
->ops
->func
) (sd
, cpu
);
152 /* Issue the second instruction (if the PC hasn't changed) */
153 if (!State
.pc_changed
)
155 /* finish any existing instructions */
157 h
= lookup_hash (sd
, cpu
, ins2
, 0);
160 get_operands (h
->ops
, ins2
);
161 State
.ins_type
= second
;
162 ins_type_counters
[ (int)State
.ins_type
]++;
163 ins_type_counters
[ (int)INS_CYCLES
]++;
164 (h
->ops
->func
) (sd
, cpu
);
167 ins_type_counters
[ (int)INS_COND_JUMP
]++;
171 do_parallel (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 ins1
, uint16 ins2
)
173 struct hash_entry
*h1
, *h2
;
175 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
176 sim_io_printf (sd
, "do_parallel 0x%x || 0x%x\n", ins1
, ins2
);
178 ins_type_counters
[ (int)INS_PARALLEL
]++;
179 h1
= lookup_hash (sd
, cpu
, ins1
, 0);
182 h2
= lookup_hash (sd
, cpu
, ins2
, 0);
186 if (h1
->ops
->exec_type
== PARONLY
)
188 get_operands (h1
->ops
, ins1
);
189 State
.ins_type
= INS_LEFT_COND_TEST
;
190 ins_type_counters
[ (int)State
.ins_type
]++;
191 (h1
->ops
->func
) (sd
, cpu
);
194 ins_type_counters
[ (int)INS_COND_TRUE
]++;
195 get_operands (h2
->ops
, ins2
);
196 State
.ins_type
= INS_RIGHT_COND_EXE
;
197 ins_type_counters
[ (int)State
.ins_type
]++;
198 (h2
->ops
->func
) (sd
, cpu
);
201 ins_type_counters
[ (int)INS_COND_FALSE
]++;
203 else if (h2
->ops
->exec_type
== PARONLY
)
205 get_operands (h2
->ops
, ins2
);
206 State
.ins_type
= INS_RIGHT_COND_TEST
;
207 ins_type_counters
[ (int)State
.ins_type
]++;
208 (h2
->ops
->func
) (sd
, cpu
);
211 ins_type_counters
[ (int)INS_COND_TRUE
]++;
212 get_operands (h1
->ops
, ins1
);
213 State
.ins_type
= INS_LEFT_COND_EXE
;
214 ins_type_counters
[ (int)State
.ins_type
]++;
215 (h1
->ops
->func
) (sd
, cpu
);
218 ins_type_counters
[ (int)INS_COND_FALSE
]++;
222 get_operands (h1
->ops
, ins1
);
223 State
.ins_type
= INS_LEFT_PARALLEL
;
224 ins_type_counters
[ (int)State
.ins_type
]++;
225 (h1
->ops
->func
) (sd
, cpu
);
226 get_operands (h2
->ops
, ins2
);
227 State
.ins_type
= INS_RIGHT_PARALLEL
;
228 ins_type_counters
[ (int)State
.ins_type
]++;
229 (h2
->ops
->func
) (sd
, cpu
);
234 add_commas (char *buf
, int sizeof_buf
, unsigned long value
)
237 char *endbuf
= buf
+ sizeof_buf
- 1;
247 *--endbuf
= (value
% 10) + '0';
248 } while ((value
/= 10) != 0);
257 for (i
= 0; i
< IMEM_SEGMENTS
; i
++)
259 if (State
.mem
.insn
[i
])
260 free (State
.mem
.insn
[i
]);
262 for (i
= 0; i
< DMEM_SEGMENTS
; i
++)
264 if (State
.mem
.data
[i
])
265 free (State
.mem
.data
[i
]);
267 for (i
= 0; i
< UMEM_SEGMENTS
; i
++)
269 if (State
.mem
.unif
[i
])
270 free (State
.mem
.unif
[i
]);
272 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
274 State
.mem
.data
[0] = calloc (1, SEGMENT_SIZE
);
277 /* For tracing - leave info on last access around. */
278 static char *last_segname
= "invalid";
279 static char *last_from
= "invalid";
280 static char *last_to
= "invalid";
284 IMAP0_OFFSET
= 0xff00,
285 DMAP0_OFFSET
= 0xff08,
286 DMAP2_SHADDOW
= 0xff04,
287 DMAP2_OFFSET
= 0xff0c
291 set_dmap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
293 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
294 + DMAP0_OFFSET
+ 2 * reg_nr
);
295 WRITE_16 (raw
, value
);
297 if ((d10v_debug
& DEBUG_MEMORY
))
299 sim_io_printf (sd
, "mem: dmap%d=0x%04lx\n", reg_nr
, value
);
305 dmap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
307 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
308 + DMAP0_OFFSET
+ 2 * reg_nr
);
309 return READ_16 (raw
);
313 set_imap_register (SIM_DESC sd
, int reg_nr
, unsigned long value
)
315 uint8
*raw
= map_memory (sd
, NULL
, SIM_D10V_MEMORY_DATA
316 + IMAP0_OFFSET
+ 2 * reg_nr
);
317 WRITE_16 (raw
, value
);
319 if ((d10v_debug
& DEBUG_MEMORY
))
321 sim_io_printf (sd
, "mem: imap%d=0x%04lx\n", reg_nr
, value
);
327 imap_register (SIM_DESC sd
, SIM_CPU
*cpu
, void *regcache
, int reg_nr
)
329 uint8
*raw
= map_memory (sd
, cpu
, SIM_D10V_MEMORY_DATA
330 + IMAP0_OFFSET
+ 2 * reg_nr
);
331 return READ_16 (raw
);
346 return HELD_SP (HELD_SPU_IDX
);
355 return HELD_SP (HELD_SPI_IDX
);
359 set_spi_register (unsigned long value
)
362 SET_GPR (SP_IDX
, value
);
363 SET_HELD_SP (HELD_SPI_IDX
, value
);
367 set_spu_register (unsigned long value
)
370 SET_GPR (SP_IDX
, value
);
371 SET_HELD_SP (HELD_SPU_IDX
, value
);
374 /* Given a virtual address in the DMAP address space, translate it
375 into a physical address. */
378 sim_d10v_translate_dmap_addr (SIM_DESC sd
,
380 unsigned long offset
,
384 unsigned long (*dmap_register
) (SIM_DESC
,
391 last_from
= "logical-data";
392 if (offset
>= DMAP_BLOCK_SIZE
* SIM_D10V_NR_DMAP_REGS
)
394 /* Logical address out side of data segments, not supported */
397 regno
= (offset
/ DMAP_BLOCK_SIZE
);
398 offset
= (offset
% DMAP_BLOCK_SIZE
);
399 if ((offset
% DMAP_BLOCK_SIZE
) + nr_bytes
> DMAP_BLOCK_SIZE
)
401 /* Don't cross a BLOCK boundary */
402 nr_bytes
= DMAP_BLOCK_SIZE
- (offset
% DMAP_BLOCK_SIZE
);
404 map
= dmap_register (sd
, cpu
, regcache
, regno
);
407 /* Always maps to data memory */
408 int iospi
= (offset
/ 0x1000) % 4;
409 int iosp
= (map
>> (4 * (3 - iospi
))) % 0x10;
410 last_to
= "io-space";
411 *phys
= (SIM_D10V_MEMORY_DATA
+ (iosp
* 0x10000) + 0xc000 + offset
);
415 int sp
= ((map
& 0x3000) >> 12);
416 int segno
= (map
& 0x3ff);
419 case 0: /* 00: Unified memory */
420 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
423 case 1: /* 01: Instruction Memory */
424 *phys
= SIM_D10V_MEMORY_INSN
+ (segno
* DMAP_BLOCK_SIZE
) + offset
;
425 last_to
= "chip-insn";
427 case 2: /* 10: Internal data memory */
428 *phys
= SIM_D10V_MEMORY_DATA
+ (segno
<< 16) + (regno
* DMAP_BLOCK_SIZE
) + offset
;
429 last_to
= "chip-data";
431 case 3: /* 11: Reserved */
438 /* Given a virtual address in the IMAP address space, translate it
439 into a physical address. */
442 sim_d10v_translate_imap_addr (SIM_DESC sd
,
444 unsigned long offset
,
448 unsigned long (*imap_register
) (SIM_DESC
,
457 last_from
= "logical-insn";
458 if (offset
>= (IMAP_BLOCK_SIZE
* SIM_D10V_NR_IMAP_REGS
))
460 /* Logical address outside of IMAP segments, not supported */
463 regno
= (offset
/ IMAP_BLOCK_SIZE
);
464 offset
= (offset
% IMAP_BLOCK_SIZE
);
465 if (offset
+ nr_bytes
> IMAP_BLOCK_SIZE
)
467 /* Don't cross a BLOCK boundary */
468 nr_bytes
= IMAP_BLOCK_SIZE
- offset
;
470 map
= imap_register (sd
, cpu
, regcache
, regno
);
471 sp
= (map
& 0x3000) >> 12;
472 segno
= (map
& 0x007f);
475 case 0: /* 00: unified memory */
476 *phys
= SIM_D10V_MEMORY_UNIFIED
+ (segno
<< 17) + offset
;
479 case 1: /* 01: instruction memory */
480 *phys
= SIM_D10V_MEMORY_INSN
+ (IMAP_BLOCK_SIZE
* regno
) + offset
;
481 last_to
= "chip-insn";
486 case 3: /* 11: for testing - instruction memory */
487 offset
= (offset
% 0x800);
488 *phys
= SIM_D10V_MEMORY_INSN
+ offset
;
489 if (offset
+ nr_bytes
> 0x800)
490 /* don't cross VM boundary */
491 nr_bytes
= 0x800 - offset
;
492 last_to
= "test-insn";
499 sim_d10v_translate_addr (SIM_DESC sd
,
501 unsigned long memaddr
,
503 unsigned long *targ_addr
,
505 unsigned long (*dmap_register
) (SIM_DESC
,
509 unsigned long (*imap_register
) (SIM_DESC
,
518 last_from
= "unknown";
521 seg
= (memaddr
>> 24);
522 off
= (memaddr
& 0xffffffL
);
524 /* However, if we've asked to use the previous generation of segment
525 mapping, rearrange the segments as follows. */
527 if (old_segment_mapping
)
531 case 0x00: /* DMAP translated memory */
534 case 0x01: /* IMAP translated memory */
537 case 0x10: /* On-chip data memory */
540 case 0x11: /* On-chip insn memory */
543 case 0x12: /* Unified memory */
551 case 0x00: /* Physical unified memory */
552 last_from
= "phys-unified";
554 phys
= SIM_D10V_MEMORY_UNIFIED
+ off
;
555 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
556 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
559 case 0x01: /* Physical instruction memory */
560 last_from
= "phys-insn";
561 last_to
= "chip-insn";
562 phys
= SIM_D10V_MEMORY_INSN
+ off
;
563 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
564 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
567 case 0x02: /* Physical data memory segment */
568 last_from
= "phys-data";
569 last_to
= "chip-data";
570 phys
= SIM_D10V_MEMORY_DATA
+ off
;
571 if ((off
% SEGMENT_SIZE
) + nr_bytes
> SEGMENT_SIZE
)
572 nr_bytes
= SEGMENT_SIZE
- (off
% SEGMENT_SIZE
);
575 case 0x10: /* in logical data address segment */
576 nr_bytes
= sim_d10v_translate_dmap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
577 regcache
, dmap_register
);
580 case 0x11: /* in logical instruction address segment */
581 nr_bytes
= sim_d10v_translate_imap_addr (sd
, cpu
, off
, nr_bytes
, &phys
,
582 regcache
, imap_register
);
593 /* Return a pointer into the raw buffer designated by phys_addr. It
594 is assumed that the client has already ensured that the access
595 isn't going to cross a segment boundary. */
598 map_memory (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned phys_addr
)
603 int segment
= ((phys_addr
>> 24) & 0xff);
608 case 0x00: /* Unified memory */
610 memory
= &State
.mem
.unif
[(phys_addr
/ SEGMENT_SIZE
) % UMEM_SEGMENTS
];
611 last_segname
= "umem";
615 case 0x01: /* On-chip insn memory */
617 memory
= &State
.mem
.insn
[(phys_addr
/ SEGMENT_SIZE
) % IMEM_SEGMENTS
];
618 last_segname
= "imem";
622 case 0x02: /* On-chip data memory */
624 if ((phys_addr
& 0xff00) == 0xff00)
626 phys_addr
= (phys_addr
& 0xffff);
627 if (phys_addr
== DMAP2_SHADDOW
)
629 phys_addr
= DMAP2_OFFSET
;
630 last_segname
= "dmap";
633 last_segname
= "reg";
636 last_segname
= "dmem";
637 memory
= &State
.mem
.data
[(phys_addr
/ SEGMENT_SIZE
) % DMEM_SEGMENTS
];
643 last_segname
= "scrap";
644 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
648 *memory
= xcalloc (1, SEGMENT_SIZE
);
650 offset
= (phys_addr
% SEGMENT_SIZE
);
651 raw
= *memory
+ offset
;
655 /* Transfer data to/from simulated memory. Since a bug in either the
656 simulated program or in gdb or the simulator itself may cause a
657 bogus address to be passed in, we need to do some sanity checking
658 on addresses to make sure they are within bounds. When an address
659 fails the bounds check, treat it as a zero length read/write rather
660 than aborting the entire run. */
663 xfer_mem (SIM_DESC sd
,
665 unsigned char *buffer
,
672 phys_size
= sim_d10v_translate_addr (sd
, NULL
, virt
, size
, &phys
, NULL
,
673 dmap_register
, imap_register
);
677 memory
= map_memory (sd
, NULL
, phys
);
680 if ((d10v_debug
& DEBUG_INSTRUCTION
) != 0)
684 "sim_%s %d bytes: 0x%08" PRIxTA
" (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
685 write_p
? "write" : "read",
686 phys_size
, virt
, last_from
,
688 (long) memory
, last_segname
);
694 memcpy (memory
, buffer
, phys_size
);
698 memcpy (buffer
, memory
, phys_size
);
706 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
708 /* FIXME: this should be performing a virtual transfer */
709 /* FIXME: We cast the const away, but it's safe because xfer_mem only reads
710 when write_p==1. This is still ugly. */
711 return xfer_mem (sd
, addr
, (void *) buffer
, size
, 1);
715 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
717 /* FIXME: this should be performing a virtual transfer */
718 return xfer_mem (sd
, addr
, buffer
, size
, 0);
722 d10v_pc_get (sim_cpu
*cpu
)
728 d10v_pc_set (sim_cpu
*cpu
, sim_cia pc
)
730 SIM_DESC sd
= CPU_STATE (cpu
);
735 free_state (SIM_DESC sd
)
737 if (STATE_MODULES (sd
) != NULL
)
738 sim_module_uninstall (sd
);
739 sim_cpu_free_all (sd
);
743 static int d10v_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
744 static int d10v_reg_store (SIM_CPU
*, int, unsigned char *, int);
747 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
748 struct bfd
*abfd
, char * const *argv
)
751 struct hash_entry
*h
;
752 static int init_p
= 0;
755 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
756 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
758 /* The cpu data is kept in a separately allocated chunk of memory. */
759 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
765 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
771 /* The parser will print an error message for us, so we silently return. */
772 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
778 /* Check for/establish the a reference program image. */
779 if (sim_analyze_program (sd
,
780 (STATE_PROG_ARGV (sd
) != NULL
781 ? *STATE_PROG_ARGV (sd
)
782 : NULL
), abfd
) != SIM_RC_OK
)
788 /* Configure/verify the target byte order and other runtime
789 configuration options. */
790 if (sim_config (sd
) != SIM_RC_OK
)
792 sim_module_uninstall (sd
);
796 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
798 /* Uninstall the modules to avoid memory leaks,
799 file descriptor leaks, etc. */
800 sim_module_uninstall (sd
);
804 /* CPU specific initialization. */
805 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
807 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
809 CPU_REG_FETCH (cpu
) = d10v_reg_fetch
;
810 CPU_REG_STORE (cpu
) = d10v_reg_store
;
811 CPU_PC_FETCH (cpu
) = d10v_pc_get
;
812 CPU_PC_STORE (cpu
) = d10v_pc_set
;
815 old_segment_mapping
= 0;
817 /* NOTE: This argument parsing is only effective when this function
818 is called by GDB. Standalone argument parsing is handled by
820 for (p
= argv
+ 1; *p
; ++p
)
822 if (strcmp (*p
, "-oldseg") == 0)
823 old_segment_mapping
= 1;
825 else if (strcmp (*p
, "-t") == 0)
827 else if (strncmp (*p
, "-t", 2) == 0)
828 d10v_debug
= atoi (*p
+ 2);
832 /* put all the opcodes in the hash table */
835 for (s
= Simops
; s
->func
; s
++)
837 h
= &hash_table
[hash(s
->opcode
,s
->format
)];
839 /* go to the last entry in the chain */
845 h
->next
= (struct hash_entry
*) calloc(1,sizeof(struct hash_entry
));
847 perror ("malloc failure");
853 h
->opcode
= s
->opcode
;
854 h
->size
= s
->is_long
;
858 /* reset the processor state */
859 if (!State
.mem
.data
[0])
866 dmem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint16 offset
)
872 /* Note: DMEM address range is 0..0x10000. Calling code can compute
873 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
874 is uint16 this is modulo'ed onto 0x0e5d. */
876 phys_size
= sim_d10v_translate_dmap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
879 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
880 mem
= map_memory (sd
, cpu
, phys
);
882 if ((d10v_debug
& DEBUG_MEMORY
))
886 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
888 phys
, phys_size
, last_to
,
889 (long) mem
, last_segname
);
896 imem_addr (SIM_DESC sd
, SIM_CPU
*cpu
, uint32 offset
)
900 int phys_size
= sim_d10v_translate_imap_addr (sd
, cpu
, offset
, 1, &phys
, NULL
,
903 sim_engine_halt (sd
, cpu
, NULL
, PC
, sim_stopped
, SIM_SIGBUS
);
904 mem
= map_memory (sd
, cpu
, phys
);
906 if ((d10v_debug
& DEBUG_MEMORY
))
910 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
912 phys
, phys_size
, last_to
,
913 (long) mem
, last_segname
);
920 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
925 /* TODO: Unindent this block. */
927 iaddr
= imem_addr (sd
, cpu
, (uint32
)PC
<< 2);
929 inst
= get_longword( iaddr
);
931 State
.pc_changed
= 0;
932 ins_type_counters
[ (int)INS_CYCLES
]++;
934 switch (inst
& 0xC0000000)
937 /* long instruction */
938 do_long (sd
, cpu
, inst
& 0x3FFFFFFF);
942 do_2_short (sd
, cpu
, inst
& 0x7FFF, (inst
& 0x3FFF8000) >> 15, RIGHT_FIRST
);
946 do_2_short (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF, LEFT_FIRST
);
949 do_parallel (sd
, cpu
, (inst
& 0x3FFF8000) >> 15, inst
& 0x7FFF);
953 /* If the PC of the current instruction matches RPT_E then
954 schedule a branch to the loop start. If one of those
955 instructions happens to be a branch, than that instruction
957 if (!State
.pc_changed
)
959 if (PSW_RP
&& PC
== RPT_E
)
961 /* Note: The behavour of a branch instruction at RPT_E
962 is implementation dependant, this simulator takes the
963 branch. Branching to RPT_E is valid, the instruction
964 must be executed before the loop is taken. */
973 SET_RPT_C (RPT_C
- 1);
981 /* Check for a breakpoint trap on this instruction. This
982 overrides any pending branches or loops */
983 if (PSW_DB
&& PC
== IBA
)
987 SET_PSW (PSW
& PSW_SM_BIT
);
988 SET_PC (SDBT_VECTOR_START
);
991 /* Writeback all the DATA / PC changes */
997 sim_engine_run (SIM_DESC sd
,
998 int next_cpu_nr
, /* ignore */
999 int nr_cpus
, /* ignore */
1004 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1006 cpu
= STATE_CPU (sd
, 0);
1012 case GDB_SIGNAL_BUS
:
1015 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1016 JMP (AE_VECTOR_START
);
1019 case GDB_SIGNAL_ILL
:
1022 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1023 JMP (RIE_VECTOR_START
);
1027 /* just ignore it */
1033 step_once (sd
, cpu
);
1034 if (sim_events_tick (sd
))
1035 sim_events_process (sd
);
1040 sim_info (SIM_DESC sd
, int verbose
)
1047 unsigned long left
= ins_type_counters
[ (int)INS_LEFT
] + ins_type_counters
[ (int)INS_LEFT_COND_EXE
];
1048 unsigned long left_nops
= ins_type_counters
[ (int)INS_LEFT_NOPS
];
1049 unsigned long left_parallel
= ins_type_counters
[ (int)INS_LEFT_PARALLEL
];
1050 unsigned long left_cond
= ins_type_counters
[ (int)INS_LEFT_COND_TEST
];
1051 unsigned long left_total
= left
+ left_parallel
+ left_cond
+ left_nops
;
1053 unsigned long right
= ins_type_counters
[ (int)INS_RIGHT
] + ins_type_counters
[ (int)INS_RIGHT_COND_EXE
];
1054 unsigned long right_nops
= ins_type_counters
[ (int)INS_RIGHT_NOPS
];
1055 unsigned long right_parallel
= ins_type_counters
[ (int)INS_RIGHT_PARALLEL
];
1056 unsigned long right_cond
= ins_type_counters
[ (int)INS_RIGHT_COND_TEST
];
1057 unsigned long right_total
= right
+ right_parallel
+ right_cond
+ right_nops
;
1059 unsigned long unknown
= ins_type_counters
[ (int)INS_UNKNOWN
];
1060 unsigned long ins_long
= ins_type_counters
[ (int)INS_LONG
];
1061 unsigned long parallel
= ins_type_counters
[ (int)INS_PARALLEL
];
1062 unsigned long leftright
= ins_type_counters
[ (int)INS_LEFTRIGHT
];
1063 unsigned long rightleft
= ins_type_counters
[ (int)INS_RIGHTLEFT
];
1064 unsigned long cond_true
= ins_type_counters
[ (int)INS_COND_TRUE
];
1065 unsigned long cond_false
= ins_type_counters
[ (int)INS_COND_FALSE
];
1066 unsigned long cond_jump
= ins_type_counters
[ (int)INS_COND_JUMP
];
1067 unsigned long cycles
= ins_type_counters
[ (int)INS_CYCLES
];
1068 unsigned long total
= (unknown
+ left_total
+ right_total
+ ins_long
);
1070 int size
= strlen (add_commas (buf1
, sizeof (buf1
), total
));
1071 int parallel_size
= strlen (add_commas (buf1
, sizeof (buf1
),
1072 (left_parallel
> right_parallel
) ? left_parallel
: right_parallel
));
1073 int cond_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_cond
> right_cond
) ? left_cond
: right_cond
));
1074 int nop_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left_nops
> right_nops
) ? left_nops
: right_nops
));
1075 int normal_size
= strlen (add_commas (buf1
, sizeof (buf1
), (left
> right
) ? left
: right
));
1078 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1079 size
, add_commas (buf1
, sizeof (buf1
), left_total
),
1080 normal_size
, add_commas (buf2
, sizeof (buf2
), left
),
1081 parallel_size
, add_commas (buf3
, sizeof (buf3
), left_parallel
),
1082 cond_size
, add_commas (buf4
, sizeof (buf4
), left_cond
),
1083 nop_size
, add_commas (buf5
, sizeof (buf5
), left_nops
));
1086 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1087 size
, add_commas (buf1
, sizeof (buf1
), right_total
),
1088 normal_size
, add_commas (buf2
, sizeof (buf2
), right
),
1089 parallel_size
, add_commas (buf3
, sizeof (buf3
), right_parallel
),
1090 cond_size
, add_commas (buf4
, sizeof (buf4
), right_cond
),
1091 nop_size
, add_commas (buf5
, sizeof (buf5
), right_nops
));
1095 "executed %*s long instruction(s)\n",
1096 size
, add_commas (buf1
, sizeof (buf1
), ins_long
));
1100 "executed %*s parallel instruction(s)\n",
1101 size
, add_commas (buf1
, sizeof (buf1
), parallel
));
1105 "executed %*s instruction(s) encoded L->R\n",
1106 size
, add_commas (buf1
, sizeof (buf1
), leftright
));
1110 "executed %*s instruction(s) encoded R->L\n",
1111 size
, add_commas (buf1
, sizeof (buf1
), rightleft
));
1115 "executed %*s unknown instruction(s)\n",
1116 size
, add_commas (buf1
, sizeof (buf1
), unknown
));
1120 "executed %*s instruction(s) due to EXExxx condition being true\n",
1121 size
, add_commas (buf1
, sizeof (buf1
), cond_true
));
1125 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1126 size
, add_commas (buf1
, sizeof (buf1
), cond_false
));
1130 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1131 size
, add_commas (buf1
, sizeof (buf1
), cond_jump
));
1134 "executed %*s cycle(s)\n",
1135 size
, add_commas (buf1
, sizeof (buf1
), cycles
));
1138 "executed %*s total instructions\n",
1139 size
, add_commas (buf1
, sizeof (buf1
), total
));
1143 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
1144 char * const *argv
, char * const *env
)
1146 bfd_vma start_address
;
1148 /* Make sure we have the right structure for the following memset. */
1149 static_assert ((uintptr_t) &State
== (uintptr_t) &State
.regs
,
1150 "&State != &State.regs");
1152 /* Reset state from the regs field until the mem field. */
1153 memset (&State
, 0, (uintptr_t) &State
.mem
- (uintptr_t) &State
.regs
);
1155 /* There was a hack here to copy the values of argc and argv into r0
1156 and r1. The values were also saved into some high memory that
1157 won't be overwritten by the stack (0x7C00). The reason for doing
1158 this was to allow the 'run' program to accept arguments. Without
1159 the hack, this is not possible anymore. If the simulator is run
1160 from the debugger, arguments cannot be passed in, so this makes
1165 start_address
= bfd_get_start_address (abfd
);
1167 start_address
= 0xffc0 << 2;
1170 sim_io_printf (sd
, "sim_create_inferior: PC=0x%" BFD_VMA_FMT
"x\n",
1174 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1175 SET_CREG (PC_CR
, start_address
>> 2);
1178 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1179 initializes imap0 and imap1 to 0x1000 as part of its ROM
1181 if (old_segment_mapping
)
1183 /* External memory startup. This is the HARD reset state. */
1184 set_imap_register (sd
, 0, 0x0000);
1185 set_imap_register (sd
, 1, 0x007f);
1186 set_dmap_register (sd
, 0, 0x2000);
1187 set_dmap_register (sd
, 1, 0x2000);
1188 set_dmap_register (sd
, 2, 0x0000); /* Old DMAP */
1189 set_dmap_register (sd
, 3, 0x0000);
1193 /* Internal memory startup. This is the ROM intialized state. */
1194 set_imap_register (sd
, 0, 0x1000);
1195 set_imap_register (sd
, 1, 0x1000);
1196 set_dmap_register (sd
, 0, 0x2000);
1197 set_dmap_register (sd
, 1, 0x2000);
1198 set_dmap_register (sd
, 2, 0x2000); /* DMAP2 initial internal value is
1199 0x2000 on the new board. */
1200 set_dmap_register (sd
, 3, 0x0000);
1208 d10v_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1210 SIM_DESC sd
= CPU_STATE (cpu
);
1212 switch ((enum sim_d10v_regs
) rn
)
1214 case SIM_D10V_R0_REGNUM
:
1215 case SIM_D10V_R1_REGNUM
:
1216 case SIM_D10V_R2_REGNUM
:
1217 case SIM_D10V_R3_REGNUM
:
1218 case SIM_D10V_R4_REGNUM
:
1219 case SIM_D10V_R5_REGNUM
:
1220 case SIM_D10V_R6_REGNUM
:
1221 case SIM_D10V_R7_REGNUM
:
1222 case SIM_D10V_R8_REGNUM
:
1223 case SIM_D10V_R9_REGNUM
:
1224 case SIM_D10V_R10_REGNUM
:
1225 case SIM_D10V_R11_REGNUM
:
1226 case SIM_D10V_R12_REGNUM
:
1227 case SIM_D10V_R13_REGNUM
:
1228 case SIM_D10V_R14_REGNUM
:
1229 case SIM_D10V_R15_REGNUM
:
1230 WRITE_16 (memory
, GPR (rn
- SIM_D10V_R0_REGNUM
));
1233 case SIM_D10V_CR0_REGNUM
:
1234 case SIM_D10V_CR1_REGNUM
:
1235 case SIM_D10V_CR2_REGNUM
:
1236 case SIM_D10V_CR3_REGNUM
:
1237 case SIM_D10V_CR4_REGNUM
:
1238 case SIM_D10V_CR5_REGNUM
:
1239 case SIM_D10V_CR6_REGNUM
:
1240 case SIM_D10V_CR7_REGNUM
:
1241 case SIM_D10V_CR8_REGNUM
:
1242 case SIM_D10V_CR9_REGNUM
:
1243 case SIM_D10V_CR10_REGNUM
:
1244 case SIM_D10V_CR11_REGNUM
:
1245 case SIM_D10V_CR12_REGNUM
:
1246 case SIM_D10V_CR13_REGNUM
:
1247 case SIM_D10V_CR14_REGNUM
:
1248 case SIM_D10V_CR15_REGNUM
:
1249 WRITE_16 (memory
, CREG (rn
- SIM_D10V_CR0_REGNUM
));
1252 case SIM_D10V_A0_REGNUM
:
1253 case SIM_D10V_A1_REGNUM
:
1254 WRITE_64 (memory
, ACC (rn
- SIM_D10V_A0_REGNUM
));
1257 case SIM_D10V_SPI_REGNUM
:
1258 /* PSW_SM indicates that the current SP is the USER
1260 WRITE_16 (memory
, spi_register ());
1263 case SIM_D10V_SPU_REGNUM
:
1264 /* PSW_SM indicates that the current SP is the USER
1266 WRITE_16 (memory
, spu_register ());
1269 case SIM_D10V_IMAP0_REGNUM
:
1270 case SIM_D10V_IMAP1_REGNUM
:
1271 WRITE_16 (memory
, imap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_IMAP0_REGNUM
));
1274 case SIM_D10V_DMAP0_REGNUM
:
1275 case SIM_D10V_DMAP1_REGNUM
:
1276 case SIM_D10V_DMAP2_REGNUM
:
1277 case SIM_D10V_DMAP3_REGNUM
:
1278 WRITE_16 (memory
, dmap_register (sd
, cpu
, NULL
, rn
- SIM_D10V_DMAP0_REGNUM
));
1281 case SIM_D10V_TS2_DMAP_REGNUM
:
1292 d10v_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1294 SIM_DESC sd
= CPU_STATE (cpu
);
1296 switch ((enum sim_d10v_regs
) rn
)
1298 case SIM_D10V_R0_REGNUM
:
1299 case SIM_D10V_R1_REGNUM
:
1300 case SIM_D10V_R2_REGNUM
:
1301 case SIM_D10V_R3_REGNUM
:
1302 case SIM_D10V_R4_REGNUM
:
1303 case SIM_D10V_R5_REGNUM
:
1304 case SIM_D10V_R6_REGNUM
:
1305 case SIM_D10V_R7_REGNUM
:
1306 case SIM_D10V_R8_REGNUM
:
1307 case SIM_D10V_R9_REGNUM
:
1308 case SIM_D10V_R10_REGNUM
:
1309 case SIM_D10V_R11_REGNUM
:
1310 case SIM_D10V_R12_REGNUM
:
1311 case SIM_D10V_R13_REGNUM
:
1312 case SIM_D10V_R14_REGNUM
:
1313 case SIM_D10V_R15_REGNUM
:
1314 SET_GPR (rn
- SIM_D10V_R0_REGNUM
, READ_16 (memory
));
1317 case SIM_D10V_CR0_REGNUM
:
1318 case SIM_D10V_CR1_REGNUM
:
1319 case SIM_D10V_CR2_REGNUM
:
1320 case SIM_D10V_CR3_REGNUM
:
1321 case SIM_D10V_CR4_REGNUM
:
1322 case SIM_D10V_CR5_REGNUM
:
1323 case SIM_D10V_CR6_REGNUM
:
1324 case SIM_D10V_CR7_REGNUM
:
1325 case SIM_D10V_CR8_REGNUM
:
1326 case SIM_D10V_CR9_REGNUM
:
1327 case SIM_D10V_CR10_REGNUM
:
1328 case SIM_D10V_CR11_REGNUM
:
1329 case SIM_D10V_CR12_REGNUM
:
1330 case SIM_D10V_CR13_REGNUM
:
1331 case SIM_D10V_CR14_REGNUM
:
1332 case SIM_D10V_CR15_REGNUM
:
1333 SET_CREG (rn
- SIM_D10V_CR0_REGNUM
, READ_16 (memory
));
1336 case SIM_D10V_A0_REGNUM
:
1337 case SIM_D10V_A1_REGNUM
:
1338 SET_ACC (rn
- SIM_D10V_A0_REGNUM
, READ_64 (memory
) & MASK40
);
1341 case SIM_D10V_SPI_REGNUM
:
1342 /* PSW_SM indicates that the current SP is the USER
1344 set_spi_register (READ_16 (memory
));
1347 case SIM_D10V_SPU_REGNUM
:
1348 set_spu_register (READ_16 (memory
));
1351 case SIM_D10V_IMAP0_REGNUM
:
1352 case SIM_D10V_IMAP1_REGNUM
:
1353 set_imap_register (sd
, rn
- SIM_D10V_IMAP0_REGNUM
, READ_16(memory
));
1356 case SIM_D10V_DMAP0_REGNUM
:
1357 case SIM_D10V_DMAP1_REGNUM
:
1358 case SIM_D10V_DMAP2_REGNUM
:
1359 case SIM_D10V_DMAP3_REGNUM
:
1360 set_dmap_register (sd
, rn
- SIM_D10V_DMAP0_REGNUM
, READ_16(memory
));
1363 case SIM_D10V_TS2_DMAP_REGNUM
: