2 Copyright (C) 1999-2021 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
23 #define WANT_CPU frvbf
24 #define WANT_CPU_FRVBF
27 #include "targ-vals.h"
28 #include "cgen-engine.h"
33 #include "libiberty.h"
37 CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot
;
39 /* The semantic code invokes this for invalid (unrecognized) instructions. */
42 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
44 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
48 /* Process an address exception. */
51 frv_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
52 unsigned int map
, int nr_bytes
, address_word addr
,
53 transfer_type transfer
, sim_core_signals sig
)
55 if (sig
== sim_core_unaligned_signal
)
57 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
58 || STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr450
)
59 frv_queue_data_access_error_interrupt (current_cpu
, addr
);
61 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, addr
);
65 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
, transfer
, sig
);
69 frv_sim_engine_halt_hook (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
)
72 if (current_cpu
!= NULL
)
73 CPU_PC_SET (current_cpu
, cia
);
75 /* Invalidate the insn and data caches of all cpus. */
76 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
78 current_cpu
= STATE_CPU (sd
, i
);
79 frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu
), 0);
80 frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu
), 1);
85 /* Read/write functions for system call interface. */
88 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
89 unsigned long taddr
, char *buf
, int bytes
)
91 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
92 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
94 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
95 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
99 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
100 unsigned long taddr
, const char *buf
, int bytes
)
102 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
103 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
105 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0);
106 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
107 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
110 /* Handle TRA and TIRA insns. */
112 frv_itrap (SIM_CPU
*current_cpu
, PCADDR pc
, USI base
, SI offset
)
114 SIM_DESC sd
= CPU_STATE (current_cpu
);
115 host_callback
*cb
= STATE_CALLBACK (sd
);
116 USI num
= ((base
+ offset
) & 0x7f) + 0x80;
118 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
120 frv_queue_software_interrupt (current_cpu
, num
);
129 CB_SYSCALL_INIT (&s
);
130 s
.func
= GET_H_GR (7);
131 s
.arg1
= GET_H_GR (8);
132 s
.arg2
= GET_H_GR (9);
133 s
.arg3
= GET_H_GR (10);
135 if (s
.func
== TARGET_SYS_exit
)
137 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
141 s
.p2
= (PTR
) current_cpu
;
142 s
.read_mem
= syscall_read_mem
;
143 s
.write_mem
= syscall_write_mem
;
145 SET_H_GR (8, s
.result
);
146 SET_H_GR (9, s
.result2
);
147 SET_H_GR (10, s
.errcode
);
151 case TRAP_BREAKPOINT
:
152 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
155 /* Add support for dumping registers, either at fixed traps, or all
156 unknown traps if configured with --enable-sim-trapdump. */
159 frv_queue_software_interrupt (current_cpu
, num
);
171 #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
177 if (STATE_TEXT_SECTION (sd
)
178 && pc
>= STATE_TEXT_START (sd
)
179 && pc
< STATE_TEXT_END (sd
))
181 const char *pc_filename
= (const char *)0;
182 const char *pc_function
= (const char *)0;
183 unsigned int pc_linenum
= 0;
185 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
186 STATE_TEXT_SECTION (sd
),
187 (struct bfd_symbol
**) 0,
188 pc
- STATE_TEXT_START (sd
),
189 &pc_filename
, &pc_function
, &pc_linenum
)
190 && (pc_function
|| pc_filename
))
197 strcpy (p
, pc_function
);
202 char *q
= (char *) strrchr (pc_filename
, '/');
203 strcpy (p
, (q
) ? q
+1 : pc_filename
);
209 sprintf (p
, " line %d", pc_linenum
);
215 if ((p
+1) - buf
> sizeof (buf
))
221 "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
222 (unsigned)pc
, buf
, (unsigned)base
, (int)offset
);
224 for (i
= 0; i
< 64; i
+= 8)
226 long g0
= (long)GET_H_GR (i
);
227 long g1
= (long)GET_H_GR (i
+1);
228 long g2
= (long)GET_H_GR (i
+2);
229 long g3
= (long)GET_H_GR (i
+3);
230 long g4
= (long)GET_H_GR (i
+4);
231 long g5
= (long)GET_H_GR (i
+5);
232 long g6
= (long)GET_H_GR (i
+6);
233 long g7
= (long)GET_H_GR (i
+7);
235 if ((g0
| g1
| g2
| g3
| g4
| g5
| g6
| g7
) != 0)
237 "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
238 i
, i
+7, g0
, g1
, g2
, g3
, g4
, g5
, g6
, g7
);
241 for (i
= 0; i
< 64; i
+= 8)
243 long f0
= (long)GET_H_FR (i
);
244 long f1
= (long)GET_H_FR (i
+1);
245 long f2
= (long)GET_H_FR (i
+2);
246 long f3
= (long)GET_H_FR (i
+3);
247 long f4
= (long)GET_H_FR (i
+4);
248 long f5
= (long)GET_H_FR (i
+5);
249 long f6
= (long)GET_H_FR (i
+6);
250 long f7
= (long)GET_H_FR (i
+7);
252 if ((f0
| f1
| f2
| f3
| f4
| f5
| f6
| f7
) != 0)
254 "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
255 i
, i
+7, f0
, f1
, f2
, f3
, f4
, f5
, f6
, f7
);
259 "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
260 (long)GET_H_SPR (272),
261 (long)GET_H_SPR (273),
262 (long)GET_H_SPR (256),
263 (long)GET_H_SPR (263));
270 /* Handle the MTRAP insn. */
272 frv_mtrap (SIM_CPU
*current_cpu
)
274 SIM_DESC sd
= CPU_STATE (current_cpu
);
276 /* Check the status of media exceptions in MSR0. */
277 SI msr
= GET_MSR (0);
278 if (GET_MSR_AOVF (msr
) || GET_MSR_MTT (msr
) && STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
279 frv_queue_program_interrupt (current_cpu
, FRV_MP_EXCEPTION
);
282 /* Handle the BREAK insn. */
284 frv_break (SIM_CPU
*current_cpu
)
287 SIM_DESC sd
= CPU_STATE (current_cpu
);
289 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
291 /* Invalidate the insn cache because the debugger will presumably
292 replace the breakpoint insn with the real one. */
293 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
296 frv_queue_break_interrupt (current_cpu
);
299 /* Return from trap. */
301 frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
)
304 /* if (normal running mode and debug_field==0
308 else if (debug running mode and debug_field==1)
312 change to normal running mode
314 int psr_s
= GET_H_PSR_S ();
315 int psr_et
= GET_H_PSR_ET ();
317 /* Check for exceptions in the priority order listed in the FRV Architecture
321 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
324 SIM_DESC sd
= CPU_STATE (current_cpu
);
325 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
328 /* privileged_instruction interrupt will have already been queued by
329 frv_detect_insn_access_interrupts. */
334 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
337 SIM_DESC sd
= CPU_STATE (current_cpu
);
338 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
341 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
344 else if (! CPU_DEBUG_STATE (current_cpu
) && debug_field
== 0)
346 USI psr
= GET_PSR ();
347 /* Return from normal running state. */
348 new_pc
= GET_H_SPR (H_SPR_PCSR
);
350 SET_PSR_S (psr
, GET_PSR_PS (psr
));
351 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
353 else if (CPU_DEBUG_STATE (current_cpu
) && debug_field
== 1)
355 USI psr
= GET_PSR ();
356 /* Return from debug state. */
357 new_pc
= GET_H_SPR (H_SPR_BPCSR
);
358 SET_PSR_ET (psr
, GET_H_BPSR_BET ());
359 SET_PSR_S (psr
, GET_H_BPSR_BS ());
360 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
361 CPU_DEBUG_STATE (current_cpu
) = 0;
369 /* Functions for handling non-excepting instruction side effects. */
370 static SI
next_available_nesr (SIM_CPU
*current_cpu
, SI current_index
)
372 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
373 if (control
->spr
[H_SPR_NECR
].implemented
)
376 USI necr
= GET_NECR ();
378 /* See if any NESRs are implemented. First need to check the validity of
380 if (! GET_NECR_VALID (necr
))
383 limit
= GET_NECR_NEN (necr
);
384 for (++current_index
; current_index
< limit
; ++current_index
)
386 SI nesr
= GET_NESR (current_index
);
387 if (! GET_NESR_VALID (nesr
))
388 return current_index
;
394 static SI
next_valid_nesr (SIM_CPU
*current_cpu
, SI current_index
)
396 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
397 if (control
->spr
[H_SPR_NECR
].implemented
)
400 USI necr
= GET_NECR ();
402 /* See if any NESRs are implemented. First need to check the validity of
404 if (! GET_NECR_VALID (necr
))
407 limit
= GET_NECR_NEN (necr
);
408 for (++current_index
; current_index
< limit
; ++current_index
)
410 SI nesr
= GET_NESR (current_index
);
411 if (GET_NESR_VALID (nesr
))
412 return current_index
;
419 frvbf_check_non_excepting_load (
420 SIM_CPU
*current_cpu
, SI base_index
, SI disp_index
, SI target_index
,
421 SI immediate_disp
, QI data_size
, BI is_float
424 BI rc
= 1; /* perform the load. */
425 SIM_DESC sd
= CPU_STATE (current_cpu
);
435 FRV_REGISTER_CONTROL
*control
;
437 SI address
= GET_H_GR (base_index
);
439 address
+= GET_H_GR (disp_index
);
441 address
+= immediate_disp
;
443 /* Check for interrupt factors. */
461 if (target_index
& 1)
467 if (target_index
& 3)
472 IADDR pc
= GET_H_PC ();
473 sim_engine_abort (sd
, current_cpu
, pc
,
474 "check_non_excepting_load: Incorrect data_size\n");
479 control
= CPU_REGISTER_CONTROL (current_cpu
);
480 if (control
->spr
[H_SPR_NECR
].implemented
)
483 do_elos
= GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
);
488 /* NECR, NESR, NEEAR are only implemented for the full frv machine. */
491 ne_index
= next_available_nesr (current_cpu
, NO_NESR
);
492 if (ne_index
== NO_NESR
)
494 IADDR pc
= GET_H_PC ();
495 sim_engine_abort (sd
, current_cpu
, pc
,
496 "No available NESR register\n");
499 /* Fill in the basic fields of the NESR. */
500 nesr
= GET_NESR (ne_index
);
501 SET_NESR_VALID (nesr
);
503 SET_NESR_DRN (nesr
, target_index
);
504 SET_NESR_SIZE (nesr
, data_size
);
505 SET_NESR_NEAN (nesr
, ne_index
);
509 CLEAR_NESR_FR (nesr
);
511 /* Set the corresponding NEEAR. */
512 SET_NEEAR (ne_index
, address
);
514 SET_NESR_DAEC (nesr
, 0);
515 SET_NESR_REC (nesr
, 0);
516 SET_NESR_EC (nesr
, 0);
519 /* Set the NE flag corresponding to the target register if an interrupt
521 daec is not checked here yet, but is declared for future reference. */
523 NE_base
= H_SPR_FNER0
;
525 NE_base
= H_SPR_GNER0
;
527 GET_NE_FLAGS (NE_flags
, NE_base
);
530 SET_NE_FLAG (NE_flags
, target_index
);
532 SET_NESR_REC (nesr
, NESR_REGISTER_NOT_ALIGNED
);
537 SET_NE_FLAG (NE_flags
, target_index
);
539 SET_NESR_EC (nesr
, NESR_MEM_ADDRESS_NOT_ALIGNED
);
543 SET_NESR (ne_index
, nesr
);
545 /* If no interrupt factor was detected then set the NE flag on the
546 target register if the NE flag on one of the input registers
548 if (! rec
&& ! ec
&& ! daec
)
550 BI ne_flag
= GET_NE_FLAG (NE_flags
, base_index
);
552 ne_flag
|= GET_NE_FLAG (NE_flags
, disp_index
);
555 SET_NE_FLAG (NE_flags
, target_index
);
556 rc
= 0; /* Do not perform the load. */
559 CLEAR_NE_FLAG (NE_flags
, target_index
);
562 SET_NE_FLAGS (NE_base
, NE_flags
);
564 return rc
; /* perform the load? */
567 /* Record state for media exception: media_cr_not_aligned. */
569 frvbf_media_cr_not_aligned (SIM_CPU
*current_cpu
)
571 SIM_DESC sd
= CPU_STATE (current_cpu
);
573 /* On some machines this generates an illegal_instruction interrupt. */
574 switch (STATE_ARCHITECTURE (sd
)->mach
)
576 /* Note: there is a discrepancy between V2.2 of the FR400
577 instruction manual and the various FR4xx LSI specs. The former
578 claims that unaligned registers cause an mp_exception while the
579 latter say it's an illegal_instruction. The LSI specs appear
580 to be correct since MTT is fixed at 1. */
584 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
587 frv_set_mp_exception_registers (current_cpu
, MTT_CR_NOT_ALIGNED
, 0);
592 /* Record state for media exception: media_acc_not_aligned. */
594 frvbf_media_acc_not_aligned (SIM_CPU
*current_cpu
)
596 SIM_DESC sd
= CPU_STATE (current_cpu
);
598 /* On some machines this generates an illegal_instruction interrupt. */
599 switch (STATE_ARCHITECTURE (sd
)->mach
)
601 /* See comment in frvbf_cr_not_aligned(). */
605 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
608 frv_set_mp_exception_registers (current_cpu
, MTT_ACC_NOT_ALIGNED
, 0);
613 /* Record state for media exception: media_register_not_aligned. */
615 frvbf_media_register_not_aligned (SIM_CPU
*current_cpu
)
617 SIM_DESC sd
= CPU_STATE (current_cpu
);
619 /* On some machines this generates an illegal_instruction interrupt. */
620 switch (STATE_ARCHITECTURE (sd
)->mach
)
622 /* See comment in frvbf_cr_not_aligned(). */
626 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
629 frv_set_mp_exception_registers (current_cpu
, MTT_INVALID_FR
, 0);
634 /* Record state for media exception: media_overflow. */
636 frvbf_media_overflow (SIM_CPU
*current_cpu
, int sie
)
638 frv_set_mp_exception_registers (current_cpu
, MTT_OVERFLOW
, sie
);
641 /* Queue a division exception. */
643 frvbf_division_exception (SIM_CPU
*current_cpu
, enum frv_dtt dtt
,
644 int target_index
, int non_excepting
)
646 /* If there was an overflow and it is masked, then record it in
648 USI isr
= GET_ISR ();
649 if ((dtt
& FRV_DTT_OVERFLOW
) && GET_ISR_EDE (isr
))
651 dtt
&= ~FRV_DTT_OVERFLOW
;
655 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
659 /* Non excepting instruction, simply set the NE flag for the target
662 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
663 SET_NE_FLAG (NE_flags
, target_index
);
664 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
667 frv_queue_division_exception_interrupt (current_cpu
, dtt
);
673 frvbf_check_recovering_store (
674 SIM_CPU
*current_cpu
, PCADDR address
, SI regno
, int size
, int is_float
677 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
680 CPU_RSTR_INVALIDATE(current_cpu
) = 0;
682 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
684 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
686 if (address
== GET_H_SPR (H_SPR_NEEAR0
+ reg_ix
))
688 SI nesr
= GET_NESR (reg_ix
);
689 int nesr_drn
= GET_NESR_DRN (nesr
);
690 BI nesr_fr
= GET_NESR_FR (nesr
);
693 /* Invalidate cache block containing this address.
694 If we need to count cycles, then the cache operation will be
695 initiated from the model profiling functions.
696 See frvbf_model_.... */
699 CPU_RSTR_INVALIDATE(current_cpu
) = 1;
700 CPU_LOAD_ADDRESS (current_cpu
) = address
;
703 frv_cache_invalidate (cache
, address
, 1/* flush */);
705 /* Copy the stored value to the register indicated by NESR.DRN. */
706 for (remain
= size
; remain
> 0; remain
-= 4)
711 value
= GET_H_FR (regno
);
713 value
= GET_H_GR (regno
);
728 sim_queue_fn_sf_write (current_cpu
, frvbf_h_fr_set
, nesr_drn
,
731 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, nesr_drn
,
737 break; /* Only consider the first matching register. */
739 } /* loop over active neear registers. */
743 frvbf_check_acc_range (SIM_CPU
*current_cpu
, SI regno
)
745 /* Only applicable to fr550 */
746 SIM_DESC sd
= CPU_STATE (current_cpu
);
747 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
750 /* On the fr550, media insns in slots 0 and 2 can only access
751 accumulators acc0-acc3. Insns in slots 1 and 3 can only access
752 accumulators acc4-acc7 */
753 switch (frv_current_fm_slot
)
758 return 1; /* all is ok */
763 return 1; /* all is ok */
767 /* The specified accumulator is out of range. Queue an illegal_instruction
769 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
774 frvbf_check_swap_address (SIM_CPU
*current_cpu
, SI address
)
776 /* Only applicable to fr550 */
777 SIM_DESC sd
= CPU_STATE (current_cpu
);
778 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
781 /* Adress must be aligned on a word boundary. */
783 frv_queue_data_access_exception_interrupt (current_cpu
);
787 clear_nesr_neear (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
791 /* Only implemented for full frv. */
792 SIM_DESC sd
= CPU_STATE (current_cpu
);
793 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_frv
)
796 /* Clear the appropriate NESR and NEEAR registers. */
797 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
799 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
802 /* The register is available, now check if it is active. */
803 nesr
= GET_NESR (reg_ix
);
804 if (GET_NESR_FR (nesr
) == is_float
)
806 if (target_index
< 0 || GET_NESR_DRN (nesr
) == target_index
)
808 SET_NESR (reg_ix
, 0);
809 SET_NEEAR (reg_ix
, 0);
817 SIM_CPU
*current_cpu
,
827 GET_NE_FLAGS (NE_flags
, NE_base
);
828 if (target_index
>= 0)
829 CLEAR_NE_FLAG (NE_flags
, target_index
);
837 SET_NE_FLAGS (NE_base
, NE_flags
);
840 /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
841 means to check for any register available. */
843 which_registers_available (
844 SIM_CPU
*current_cpu
, int *hi_available
, int *lo_available
, int is_float
848 frv_fr_registers_available (current_cpu
, hi_available
, lo_available
);
850 frv_gr_registers_available (current_cpu
, hi_available
, lo_available
);
854 frvbf_clear_ne_flags (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
861 FRV_REGISTER_CONTROL
*control
;
863 /* Check for availability of the target register(s). */
864 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
867 /* Check to make sure that the target register is available. */
868 if (! frv_check_register_access (current_cpu
, target_index
,
869 hi_available
, lo_available
))
872 /* Determine whether we're working with GR or FR registers. */
874 NE_base
= H_SPR_FNER0
;
876 NE_base
= H_SPR_GNER0
;
878 /* Always clear the appropriate NE flags. */
879 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
882 /* Clear the appropriate NESR and NEEAR registers. */
883 control
= CPU_REGISTER_CONTROL (current_cpu
);
884 if (control
->spr
[H_SPR_NECR
].implemented
)
887 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
))
888 clear_nesr_neear (current_cpu
, target_index
, is_float
);
893 frvbf_commit (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
902 FRV_REGISTER_CONTROL
*control
;
904 /* Check for availability of the target register(s). */
905 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
908 /* Check to make sure that the target register is available. */
909 if (! frv_check_register_access (current_cpu
, target_index
,
910 hi_available
, lo_available
))
913 /* Determine whether we're working with GR or FR registers. */
915 NE_base
= H_SPR_FNER0
;
917 NE_base
= H_SPR_GNER0
;
919 /* Determine whether a ne exception is pending. */
920 GET_NE_FLAGS (NE_flags
, NE_base
);
921 if (target_index
>= 0)
922 NE_flag
= GET_NE_FLAG (NE_flags
, target_index
);
926 hi_available
&& NE_flags
[0] != 0 || lo_available
&& NE_flags
[1] != 0;
929 /* Always clear the appropriate NE flags. */
930 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
933 control
= CPU_REGISTER_CONTROL (current_cpu
);
934 if (control
->spr
[H_SPR_NECR
].implemented
)
937 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
) && NE_flag
)
939 /* Clear the appropriate NESR and NEEAR registers. */
940 clear_nesr_neear (current_cpu
, target_index
, is_float
);
941 frv_queue_program_interrupt (current_cpu
, FRV_COMMIT_EXCEPTION
);
946 /* Generate the appropriate fp_exception(s) based on the given status code. */
948 frvbf_fpu_error (CGEN_FPU
* fpu
, int status
)
950 struct frv_fp_exception_info fp_info
= {
951 FSR_NO_EXCEPTION
, FTT_IEEE_754_EXCEPTION
955 (sim_fpu_status_invalid_snan
|
956 sim_fpu_status_invalid_qnan
|
957 sim_fpu_status_invalid_isi
|
958 sim_fpu_status_invalid_idi
|
959 sim_fpu_status_invalid_zdz
|
960 sim_fpu_status_invalid_imz
|
961 sim_fpu_status_invalid_cvi
|
962 sim_fpu_status_invalid_cmp
|
963 sim_fpu_status_invalid_sqrt
))
964 fp_info
.fsr_mask
|= FSR_INVALID_OPERATION
;
966 if (status
& sim_fpu_status_invalid_div0
)
967 fp_info
.fsr_mask
|= FSR_DIVISION_BY_ZERO
;
969 if (status
& sim_fpu_status_inexact
)
970 fp_info
.fsr_mask
|= FSR_INEXACT
;
972 if (status
& sim_fpu_status_overflow
)
973 fp_info
.fsr_mask
|= FSR_OVERFLOW
;
975 if (status
& sim_fpu_status_underflow
)
976 fp_info
.fsr_mask
|= FSR_UNDERFLOW
;
978 if (status
& sim_fpu_status_denorm
)
980 fp_info
.fsr_mask
|= FSR_DENORMAL_INPUT
;
981 fp_info
.ftt
= FTT_DENORMAL_INPUT
;
984 if (fp_info
.fsr_mask
!= FSR_NO_EXCEPTION
)
986 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
987 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);