Factor out the parts of `_bfd_mips_elf_merge_private_bfd_data'
responsible for ABI flag merging to `mips_elf_merge_obj_abiflags'. No
functional change.
bfd/
* elfxx-mips.c (mips_elf_merge_obj_abiflags): New function,
factored out from...
(_bfd_mips_elf_merge_private_bfd_data): ... here.
MIPS/BFD: Move attribute check after ELF file header flag check
We have a problem in that in making compatibility checks while merging
private BFD data on the MIPS target we give priority to the attribute
check, which may fail and cause the function to abort early on. The
problem with this is the ABI compatibility aspect recorded in the
attributes is relatively minor compared to aspects recorded in the ELF
file header. However the premature exit causes any more important
compatibility aspect violated to be masked and not reported to the user
once a problem with attributes has been noticed.
So move the attribute check after the ELF file header flag check in
`_bfd_mips_elf_merge_private_bfd_data', and do not return prematurely
there. Take advantage of the resulting grouping of ELF file header
handling together and remove the premature success return point for the
first input object being handled, letting the code later on figure out
output ABI flags even for this object.
Update LD test cases according to messages from ELF file header checks
now preceding ones from attribute checks.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Move
attribute check after ELF file header flag check.
ld/
* testsuite/ld-mips-elf/attr-gnu-4-14.d: Update the order of
messages expected according to MIPS BFD private data merge
changes.
* testsuite/ld-mips-elf/attr-gnu-4-24.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-34.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-41.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-42.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-43.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-45.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-46.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-47.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-48.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-49.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-54.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-64.d: Likewise.
* testsuite/ld-mips-elf/attr-gnu-4-74.d: Likewise.
Factor out the parts of `_bfd_mips_elf_merge_private_bfd_data'
responsible for ELF file header flag compatibility checks to
`mips_elf_merge_obj_e_flags'. As a side effect remove a premature
return point from `_bfd_mips_elf_merge_private_bfd_data'. No functional
change otherwise.
bfd/
* elfxx-mips.c (mips_elf_merge_obj_e_flags): New function,
factored out from...
(_bfd_mips_elf_merge_private_bfd_data): ... here.
MIPS/BFD: Fold the handling of input MIPS ABI flags together
Fold the handling of input MIPS ABI flags in private BFD data merging
together, moving the attribute check afterwards, and consequently making
input vs output compatibility checks only start once all input ABI flag
data has been gathered, checked for inconsistencies and put in order.
Consequently also address the issue of input ABI flag inconsistencies
being masked by a failing attribute check, which currently makes
`_bfd_mips_elf_merge_private_bfd_data' exit prematurely and therefore
prevent input ABI flag inconsistencies from being reported. Such
inconsistencies need to be reported as they may be the very cause of an
attribute check failure.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Fold the
handling of input MIPS ABI flags together.
MIPS/BFD: Suppress attribute checks for null input
We currently special-case the handling of attribute checks on input
objects and make them even before we check a given input object actually
contains any sections. This does not add value as empty objects do not
cause a compatibility concern and we already make this observation for
other properties such as ELF file header flags. Moreover the attributes
themselves are stored in a `.gnu.attributes' section so the absence of
any section (except from a few special cases) implies there have been no
attributes provided either. Therefore it is safe to move the attribute
checks later on, after the null-section check has been made.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Suppress
attribute checks for null input.
Correct a warning produced on any FP ABI mismatch observed. Unlike the
other settings, which in the presence of `.MIPS.abiflags' are duplicated
in the `e_flags' member of the ELF file header, information on the FP
ABI in use is duplicated in `.gnu.attributes' rather than in the former
place. Update the warning message accordingly.
bfd/
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Correct
an FP ABI warning.
Mike Frysinger [Mon, 4 Jan 2016 10:08:26 +0000 (05:08 -0500)]
sim: parse_args: polish getopt error message
The cris sim hit a few failures after the recent getopt logic, and the
expected output showed a few ways we can improve things to better match
other utils.
Mike Frysinger [Mon, 4 Jan 2016 09:06:01 +0000 (04:06 -0500)]
sim: punt x86-specific bswap logic
The compiler/C library should produce reasonable code for htonl/ntohl,
and at least glibc tries pretty hard to always produce good code for
them. This logic only had support for 32-bit x86 systems anymore, and
it's unlikely people were even opting into this, so drop it all.
Mike Frysinger [Mon, 4 Jan 2016 08:58:09 +0000 (03:58 -0500)]
sim: d10v: gut endian logic
The compiler should produce reasonable code here in general, so punt the
various arch checks and bswap defines. This code will eventually go away
entirely when we convert it to the common memory code.
Markus Metzger [Wed, 23 Dec 2015 12:53:53 +0000 (13:53 +0100)]
btrace: do not return out of TRY/CATCH
In btrace_pt_readmem_callback, we read memory inside TRY/CATCH and return in
case of an error return value. This corrupts the cleanup chain, which
eventually results in a SEGV when doing or discarding cleanups later on.
gdb/
* btrace.c (btrace_pt_readmem_callback): Do not return in TRY/CATCH.
Mike Frysinger [Mon, 4 Jan 2016 02:40:34 +0000 (21:40 -0500)]
sim: parse_args: display getopt error ourselves
Fix a long standing todo where we let getopt write directly to stderr
when an invalid option is passed. Use the sim io funcs instead as they
go through the filtered callbacks that gdb wants.
Mike Frysinger [Sun, 3 Jan 2016 05:36:13 +0000 (00:36 -0500)]
sim: drop host endian configure option
The --enable-sim-hostendian flag was purely so people had an escape route
for when cross-compiling. This is because historically, AC_C_BIGENDIAN
did not work in those cases. That was fixed a while ago though, so we can
require that macro everywhere now and simplify a good bit of code.
Mike Frysinger [Sat, 2 Jan 2016 22:46:16 +0000 (17:46 -0500)]
sim: convert to bfd_endian
Rather than re-invent endian defines, as well as maintain our own list
of OS & arch-specific includes, punt all that logic in favor of the bfd
ones already set up and maintained elsewhere. We already rely on the
bfd library, so leveraging the endian aspect should be fine.
Mike Frysinger [Sat, 2 Jan 2016 14:23:06 +0000 (09:23 -0500)]
sim: delete dead current_state globals
The global current_state handle to the current simulator state is a
design idea that was half implemented, but never really cleaned up.
The point was to have a global variable pointing to the state so that
funcs could more quickly & easily access the state anywhere. We've
instead moved in the direction of passing state around everywhere and
don't have any intention of moving back.
I also can't find any references to gdb using this variable, or to
cgen related "dump_regs" functions, both of which were used in the
comments related to this code.
Mike Frysinger [Sat, 2 Jan 2016 07:34:05 +0000 (02:34 -0500)]
sim: ppc: do not exit when parsing args w/gdb
When connecting to the simulator in gdb, we don't want it to exit on
us when we pass down unknown/invalid/help/etc... options. Plumb down
the kind argument so we can handle both gdb & psim interfaces.
Andrew Burgess [Wed, 16 Dec 2015 13:57:44 +0000 (13:57 +0000)]
opcodes/arc: Support dmb instruction with no operands
In this GCC commit:
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg00735.html
GCC started emitting dmb instructions with no operands. The intention
was that dmb with no operands should be an alias for 'dmb 0'.
The following patch extends the arc opcodes library to support dmb with
no operands.
opcodes/ChangeLog:
* arc-tbl.h (dmb): Add a no operand version of dmb.
We can leverage the cpu->regs array rather than going through the
function helpers to get nice compact code.
Further, fix up the return values: return -1 when we can't find a
register (and let the caller write out warnings), return 2/4 when
we actually write out that amount, and handle the zero reg.
Mike Frysinger [Wed, 30 Dec 2015 06:49:53 +0000 (01:49 -0500)]
sim: h8300: move unused/buggy lregs array
This array isn't used anywhere, and the init phase actually corrupts
some memory because the array has 18 elements but tries to set the
19th (ZERO) position.
Kevin Buettner [Mon, 16 Nov 2015 21:58:07 +0000 (14:58 -0700)]
sim: ppc: track closed state of file descriptors 0, 1, and 2.
This change tracks the "closed" state of file descriptors 0, 1, and 2,
introducing the function fdbad() to emul_netbsd.c and emul_unix.c.
Note that a function of the same name and purpose exists in
sim/common/callback.c.
This patch eliminates all of the "unresolved testcases" when testing
GDB against the powerpc simulator.
This occurs because the powerpc simulator closes, on behalf of the
testcase, the file descriptors associated with stdin, stdout, and
stderr. GDB still needs these descriptors to communicate with the
user or, in this case, with the testing framework.
Mike Frysinger [Sun, 27 Dec 2015 06:41:27 +0000 (01:41 -0500)]
sim: aarch64/msp430: fix disassembler usage
The disasm framework reserves the private_data field for the disassemblers
themselves, not for people who use the disassembler. Instead, there is an
application_data field for callers such as the sim. Switch to it to avoid
random corruption/crashes when the disassemblers use private_data.
Mike Frysinger [Fri, 10 Apr 2015 23:40:34 +0000 (19:40 -0400)]
sim: unify sim-hload
Pretty much all targets are using this module already, so add it to the
common list of objects. The only oddball out here is cris and that's
because it supports loading via an offset for all the phdrs. We drop
support for that.
Mike Frysinger [Sun, 27 Dec 2015 01:20:23 +0000 (20:20 -0500)]
sim: punt WITH_DEVICES & tconfig.h support
No arch is using this anymore, and we want all new ports using the
hardware framework instead. Punt WITH_DEVICES and the two callbacks
device_io_{read,write}_buffer.
We can also punt the tconfig.h file as no port is using it anymore.
This fixes in-tree builds that get confused by picking up the wrong
one (common/ vs <port>/) caused by commit ae7d0cac8ce971f7108d270c.
Any port that needs to set up a global define can use their own
sim-main.h file that they must provide regardless.
Mike Frysinger [Sun, 27 Dec 2015 00:02:07 +0000 (19:02 -0500)]
sim: bfin: push down mmr address/size checks
The bfin port is using the WITH_DEVICES framework for two reasons:
- get access to the cpu making the request (if available)
- check the alignment & size for core & system MMRs
We addressed the first part with commit dea10706e9159ba6e94eab4c25010f3,
and we handle the second part with this commit. Arguably this is more
correct too because trying to do bad reads/writes directly (when devices
support is disabled) often results in bad memory accesses.
As part of this clean up, we also adjust all of the existing logic that
would reject invalid accesses: the code was relying on the checks never
returning, but that's not the case when things like gdb (via the user's
commands) are making the requests. Thus we'd still end up with bad mem
accesses, or sometimes gdb being hung due to while(1) loops.
Now we can connect (most of) these models into any address and have them
work correctly.
Mike Frysinger [Sat, 26 Dec 2015 23:22:37 +0000 (18:22 -0500)]
sim: bfin: avoid stack error under asan
We set up an array of 3 elements and then index into it with a 2bit
value. We check the range before we actually use the pointer, but
the indexing is enough to make asan upset, so just stuff a fourth
value in there to keep things simple.
Mike Frysinger [Sat, 26 Dec 2015 19:16:51 +0000 (14:16 -0500)]
sim: sim-core: pass down cpu to hw accesses when available
The bfin port has been using the device callback largely so it could be
passed the cpu when available. Add this logic to the common core code
so all ports get access to the active cpu.
The semantics of these buffer functions are changed slightly in that
errors halt the engine synchronously rather than returning the length
to the caller. We'll probably adjust this in a follow up commit.
The bfin code isn't updated just yet as it has a bit more logic in the
device layer that needs to be unwound at which point we can delete it
entirely.
Mike Frysinger [Sat, 26 Dec 2015 16:35:03 +0000 (11:35 -0500)]
sim: mips: delete mmu stubs to move to common sim_{read,write}
The only unique thing about mip's sim_{read,write} helpers is the call to
address_translation on the incoming address. When we look closer at that
function though, we see it's just a stub that maps physical to virtual,
and the cache/return values are hardcoded. If we delete this function,
we can then collapse all the callers and drop the custom sim_{read,write}
logic entirely.
Some day we might want to add MMU support, but when we do, we'll want to
have the common layers handle things so all targets benefit.
Mike Frysinger [Sat, 26 Dec 2015 13:13:38 +0000 (08:13 -0500)]
sim: cris: do not pass cpu when writing memory during init
The point of passing down the cpu to core reads/writes is to signal which
cpu is making the access. For system accesses (such as internal memory
initialization), passing the cpu down doesn't make sense, and in the case
of early init like cris, can cause crashes. Since the cpu isn't fully set
up at this point, if the core code tries to access some fields (like the
PC reg), it'll crash. While cris shouldn't be doing this setup here (it
should be in the inferior stage), we'll deal with that later.
Mike Frysinger [Sat, 26 Dec 2015 12:05:41 +0000 (07:05 -0500)]
sim: standardize sim_create_inferior handling of argv a bit more
For targets that process argv in sim_create_inferior, improve the code:
- provide more details in the comment
- make the check for when to re-init more robust
- clean out legacy sim_copy_argv code
This will be cleaned up more in the future when we have a common inferior
creation function, but at least help new ports get it right until then.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
ld/testsuite/
* ld-arm/arm-elf.exp: Run new test "Thumb-Thumb farcall v6-M (no
profile)".
* ld-arm/farcall-thumb-thumb-m-no-profile-a.s: New file.
* ld-arm/farcall-thumb-thumb-m-no-profile-b.s: Likewise.
* ld-arm/farcall-thumb-thumb-m-no-profile.d: Likewise.
Mike Frysinger [Fri, 25 Dec 2015 18:19:07 +0000 (13:19 -0500)]
sim: frv: punt WITH_DEVICE support
The frv port used the device logic to support a single cache address,
and the comments around that are "these were merely copied from a diff
port and are unused", plus the code to attach the memory is "#if 0".
Just punt it all.
Mike Frysinger [Fri, 25 Dec 2015 18:04:26 +0000 (13:04 -0500)]
sim: m32r: migrate from WITH_DEVICES to WITH_HW
The m32r port was using the device framework to handle two devices: the
cache and uart registers. Both can be implemented in the newer hardware
framework instead which allows us to drop the device logic entirely, as
well as delete the tconfig.h file.
While creating the new uart device model, I also added support for using
stdin to read/write data rather than only supporting sockets.
This has been lightly tested as there doesn't appear to be test coverage
for the code already. If anyone still cares about this port, then they
should (hopefully) file bug reports.
Mike Frysinger [Fri, 25 Dec 2015 11:03:22 +0000 (06:03 -0500)]
sim: cris: migrate from WITH_DEVICES to WITH_HW
The cris port was using the device framework to handle two addresses when
the --cris-900000xx flag was specified. That can be implemented using the
newer hardware framework instead which allows us to drop the device logic
entirely, as well as delete the tconfig.h file. Basically we create a new
cris_900000xx device model and move the read logic out of devices.c and
into that. The rest of the devices logic was callback to the hardware
framework already.
Mike Frysinger [Fri, 25 Dec 2015 10:51:46 +0000 (05:51 -0500)]
sim: cris: set up sane default path to rvdummy
Much like we autodetect the path to the run program when there is none
set explicitly, do the same for the rvdummy program. Otherwise the
default make check fails to execute the helper properly.
Mike Frysinger [Fri, 25 Dec 2015 10:45:47 +0000 (05:45 -0500)]
sim: hw-properties: delete trace calls
These trace calls don't seem to add anything useful and break the cris
hw tests, so punt them. They were disabled before commit 6d519a4606b9
but were re-enabled as part of TRACE macro cleanups.
Mike Frysinger [Fri, 25 Dec 2015 09:27:27 +0000 (04:27 -0500)]
sim: sim-model: build for everyone
Rather than include this for some targets, set it up so we can build it
all the time via the common code. This makes it easier for targets to
opt into it when they're ready, increases build coverage, and allows us
to centralize much of the logic.
We also get to delete tconfig.h from two more targets -- they were
setting WITH_DEVICES to 0 which has the same behavior as not defining
it at all.
While the SIM_HAVE_MODEL knob is gone, we now have WITH_MODEL_P, but it
is only used by the common sim-model code. We use it to declare dummy
model lists when the arch hasn't created its own.
Mike Frysinger [Fri, 25 Dec 2015 09:12:55 +0000 (04:12 -0500)]
sim: move MACH/MODEL types into SIM_xxx namespace
The "MACH" and "MODEL" names are a bit generic and collide with symbols
used by other sections of code (like h8300's opcodes). Since these are
sim-specific types, they really should have a "SIM_" prefix.
Mike Frysinger [Fri, 25 Dec 2015 07:13:18 +0000 (02:13 -0500)]
sim: device_error: punt
Only four targets implement this function, and three of them do nothing.
The 4th merely calls abort. Since calls to this function are followed
by calls to sim_hw_abort or sim_io_error, this is largely useless. In
the two places where we don't, replace the call with sim_engine_abort.
We want to kill off the WITH_DEVICES logic in favor of WITH_HW, so this
is a good first step.
Mike Frysinger [Fri, 25 Dec 2015 05:23:50 +0000 (00:23 -0500)]
sim: always enable callback memory
We enable WITH_CALLBACK_MEMORY everywhere and don't provide a way to
turn it off, and no target does so. Make it unconditional for all
to keep things simple.
Mike Frysinger [Fri, 25 Dec 2015 05:09:48 +0000 (00:09 -0500)]
sim: dv-pal: always use CPU_INDEX
Since the core always provides CPU_INDEX, use it. The current code
doesn't actually use it even though it should since it doesn't include
the right headers.
Mike Frysinger [Fri, 25 Dec 2015 02:36:09 +0000 (21:36 -0500)]
sim: make LMA loading the default for all targets
Most targets already default to loading code via their LMA, but for
a few, this means the default changes from loading VMA to LMA. It's
better to have the different targets be consistent, and allows some
code clean up.
Mike Frysinger [Thu, 24 Dec 2015 20:49:31 +0000 (15:49 -0500)]
sim: cris: move option install to sim_open
We've moved custom option install for other targets to sim_open, so update
cris too. It's the last one using MODULE_LIST, so we can drop that from
the common code too.
Mike Frysinger [Thu, 24 Dec 2015 22:37:01 +0000 (17:37 -0500)]
sim: delete old breakpoint code
This code relies on the old sim-break module, but that was deleted in 2003.
The module only existed for gdb to tell the sim to set breakpoints on its
behalf, but then that logic was abandoned in favor of gdb knowing all about
proper breakpoints (since it does already for non-sim targets). Some dead
code lived on in the older ports though -- clean it up now.
Mike Frysinger [Thu, 24 Dec 2015 22:01:21 +0000 (17:01 -0500)]
sim: enable watchpoint module everywhere
We build & bundle the watchpoint module everywhere, but we don't make
the command line flags available by default. A few targets opted in,
but most did not. Just enable the flag for everyone. Not all targets
will respect the flags (making them nops), but shouldn't be a big deal.
This is how we handle other common modules already.
Mike Frysinger [Thu, 24 Dec 2015 21:41:55 +0000 (16:41 -0500)]
sim: delete SIM_HAVE_FLATMEM support
No target has used this, and it's a cheap hack in place in using the
common memory module. We want everyone using that though, so drop
support for flatmem entirely.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb_only): Check that profile is 'M' and update
logic around Tag_CPU_arch values to return TRUE for ARMv8-M
architectures.
(tag_cpu_arch_combine): Define v8m_baseline and v8m_mainline and update
v4t_plus_v6_m and comb to deal with ARMv8-M Tag_CPU_arch merging logic.
(elf32_arm_merge_eabi_attributes): Add Tag_CPU_name values for
ARMv8-M.
gas/
* config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
shared between ARMv6T2 and ARMv8-M.
(move_or_literal_pool): Check mov.w/mvn and movw availability against
arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
arm_arch_t2.
(do_t_branch): Error out for wide conditional branch instructions if
targetting ARMv8-M Baseline.
(non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
in ARMv8-M Baseline.
(wide_insn_ok): New function.
(md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
adapt error message for unsupported wide instruction to ARMv8-M
Baseline.
(insns): Reorganize instructions shared by ARMv8-M Baseline and
ARMv6t2 architecture.
(arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
marvell-whitney cores.
(arm_archs): Define armv8-m.base architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
(aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well.
gas/testsuite/
* gas/arm/archv8m-base.d: New file.
* gas/arm/attr-march-armv8m.base.d: Likewise.
* gas/arm/armv8m.base-idiv.d: Likewise.
* gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.
include/opcode/
* arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
(ARM_AEXT2_V8A): New architecture extension bitfield.
(ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_AEXT_V8M_BASE): New architecture extension bitfield.
(ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
(ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield.
(ARM_ARCH_V6KT2): Likewise.
(ARM_ARCH_V6ZT2): Likewise.
(ARM_ARCH_V6KZT2): Likewise.
(ARM_ARCH_V7): Likewise.
(ARM_ARCH_V7A): Likewise.
(ARM_ARCH_V7VE): Likewise.
(ARM_ARCH_V7R): Likewise.
(ARM_ARCH_V7M): Likewise.
(ARM_ARCH_V7EM): Likewise.
(ARM_ARCH_V8A): Likewise.
(ARM_ARCH_V8M_BASE): New architecture bitfield.
(ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
(ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield and reindent.
(ARM_ARCH_V7A_MP_SEC): Likewise.
(ARM_ARCH_V7R_IDIV): Likewise.
(ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
availability against arm_ext_v6t2 instead of checking arm_arch_t2,
fixing comments along the way.
(handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
generate IT instruction.
(t1_isa_t32_only_insn): New function.
(md_assemble): Use above new function to check for invalid wide
instruction for CPU Thumb ISA and to determine what Thumb extension
bit is necessary for that instruction.
(md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
branch is out of range.
include/opcode/
* arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
remove extension bit not including any Thumb-2 instruction.