+2015-12-26 Mike Frysinger <vapier@gentoo.org>
+
+ * devices.c (bfin_mmr_invalid): Delete cpu arg and add missing arg.
+ Add cpu, rw, and reason local vars. Rewrite error messages. Add
+ more todo comments.
+ (dv_bfin_mmr_invalid): Update bfin_mmr_invalid call.
+ (dv_bfin_mmr_require): Likewise. Change return to bool. Check
+ alignment of the addr variable.
+ (bfin_mmr_check, dv_bfin_mmr_check, device_io_read_buffer,
+ device_io_write_buffer): Delete.
+ (dv_bfin_mmr_require_16_32): Define.
+ * devices.h (dv_bfin_mmr_require): Change return to bool.
+ (dv_bfin_mmr_check): Delete.
+ (dv_bfin_mmr_require_16_32): Define.
+ Add a few comments.
+ * dv-bfin_cec.c (bfin_cec_io_write_buffer): Call
+ dv_bfin_mmr_require_32.
+ (bfin_cec_io_read_buffer): Likewise.
+ * dv-bfin_ctimer.c (bfin_ctimer_io_write_buffer): Likewise.
+ (bfin_ctimer_io_read_buffer): Likewise.
+ * dv-bfin_dma.c (bfin_dma_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32. Return 0 in the default case.
+ (bfin_dma_io_read_buffer): Call dv_bfin_mmr_require_16_32.
+ * dv-bfin_ebiu_amc.c (bf50x_ebiu_amc_io_write_buffer): Return 0
+ when dv_bfin_mmr_require_16 fails and in the default case.
+ (bf53x_ebiu_amc_io_write_buffer): Likewise.
+ (bf54x_ebiu_amc_io_write_buffer): Likewise.
+ (bfin_ebiu_amc_io_write_buffer): Call dv_bfin_mmr_require_16_32.
+ (bf50x_ebiu_amc_io_read_buffer): Return 0 when
+ dv_bfin_mmr_require_16 fails and in the default case.
+ (bf53x_ebiu_amc_io_read_buffer): Likewise.
+ (bf54x_ebiu_amc_io_read_buffer): Likewise.
+ (bfin_ebiu_amc_io_read_buffer): Call dv_bfin_mmr_require_16_32.
+ * dv-bfin_ebiu_ddrc.c (bfin_ebiu_ddrc_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32. Return 0 when dv_bfin_mmr_require_16 or
+ dv_bfin_mmr_require_32 fails.
+ (bfin_ebiu_ddrc_io_read_buffer): Likewise.
+ * dv-bfin_ebiu_sdc.c (bfin_ebiu_sdc_io_write_buffer): Likewise.
+ (bfin_ebiu_sdc_io_read_buffer): Likewise.
+ * dv-bfin_emac.c (bfin_emac_io_write_buffer): Return 0 when
+ dv_bfin_mmr_require_32 fails and in the default case.
+ (bfin_emac_io_read_buffer): Likewise.
+ * dv-bfin_eppi.c (bfin_eppi_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32 and return 0 when dv_bfin_mmr_require_16
+ or dv_bfin_mmr_require_32 fails and in the default case.
+ (bfin_eppi_io_read_buffer): Likewise.
+ * dv-bfin_evt.c (bfin_evt_io_write_buffer): Call
+ dv_bfin_mmr_require_32.
+ (bfin_evt_io_read_buffer): Likewise.
+ * dv-bfin_gpio.c (bfin_gpio_io_write_buffer): Move call to
+ dv_bfin_mmr_require_16 to earlier in the func. Return 0 when it
+ fails and in the default case.
+ (bfin_gpio_io_read_buffer): Likewise.
+ * dv-bfin_gpio2.c (bfin_gpio_io_write_buffer): Move call to
+ dv_bfin_mmr_require_16 and dv_bfin_mmr_require_32 to earlier in the
+ func. Return 0 when it fails and in the default case.
+ (bfin_gpio_io_read_buffer): Likewise.
+ * dv-bfin_gptimer.c (bfin_gptimer_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32. Return 0 when dv_bfin_mmr_require_16 or
+ dv_bfin_mmr_require_32 fails and in the default case.
+ (bfin_gptimer_io_read_buffer): Likewise.
+ * dv-bfin_jtag.c (bfin_jtag_io_write_buffer): Call
+ dv_bfin_mmr_require_32. Return 0 in the default case.
+ (bfin_jtag_io_read_buffer): Likewise. Delete while(1) loop.
+ * dv-bfin_mmu.c (bfin_mmu_io_write_buffer): Call
+ dv_bfin_mmr_require_32. Return 0 in the default case.
+ (bfin_mmu_io_read_buffer): Likewise. Delete while(1) loop.
+ * dv-bfin_nfc.c (bfin_nfc_io_write_buffer): Move call to
+ dv_bfin_mmr_require_16 to earlier in the func. Return 0 when it
+ fails and in the default case.
+ (bfin_nfc_io_read_buffer): Likewise.
+ * dv-bfin_otp.c (bfin_otp_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32. Return 0 when dv_bfin_mmr_require_16
+ or dv_bfin_mmr_require_32 fails and in the default case.
+ (bfin_otp_io_read_buffer): Likewise.
+ * dv-bfin_pfmon.c (bfin_pfmon_io_write_buffer): Call
+ dv_bfin_mmr_require_32. Return 0 in the default case.
+ (bfin_pfmon_io_read_buffer): Likewise. Delete while(1) loop.
+ * dv-bfin_pint.c (bfin_pint_io_write_buffer): Move call to
+ dv_bfin_mmr_require_32 to earlier in the func. Return 0 when it
+ fails and in the default case.
+ (bfin_pint_io_read_buffer): Likewise.
+ * dv-bfin_pll.c (bfin_pll_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32. Return 0 when dv_bfin_mmr_require_16
+ fails.
+ (bfin_pll_io_read_buffer): Likewise.
+ * dv-bfin_ppi.c (bfin_ppi_io_write_buffer): Move call to
+ dv_bfin_mmr_require_16 to earlier in the func. Return 0 when it
+ fails and in the default case.
+ 9bfin_ppi_io_read_buffer): Likewise.
+ * dv-bfin_rtc.c (bfin_rtc_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32.
+ (bfin_rtc_io_read_buffer): Likewise.
+ * dv-bfin_sic.c (bfin_sic_52x_io_write_buffer): Likewise.
+ (bfin_sic_52x_io_read_buffer, bfin_sic_537_io_write_buffer,
+ bfin_sic_537_io_read_buffer, bfin_sic_54x_io_write_buffer,
+ bfin_sic_54x_io_read_buffer, bfin_sic_561_io_write_buffer,
+ bfin_sic_561_io_read_buffer): Likewise.
+ * dv-bfin_spi.c (bfin_spi_io_write_buffer): Move call to
+ dv_bfin_mmr_require_16 to earlier in the func. Return 0 when it
+ fails and in the default case.
+ (bfin_spi_io_read_buffer): Likewise.
+ * dv-bfin_trace.c (bfin_trace_io_write_buffer): Call
+ dv_bfin_mmr_require_32. Return 0 in the default case.
+ (bfin_trace_io_read_buffer): Likewise. Delete while(1) loop.
+ * dv-bfin_twi.c (bfin_twi_io_write_buffer): Move call to
+ dv_bfin_mmr_require_16 to earlier in the func. Return 0 when it
+ fails and in the default case.
+ (bfin_twi_io_read_buffer): Likewise.
+ * dv-bfin_uart.c (bfin_uart_io_write_buffer): Likewise.
+ (bfin_uart_io_read_buffer): Likewise.
+ * dv-bfin_uart2.c (bfin_uart_io_write_buffer): Likewise.
+ (bfin_uart_io_read_buffer): Likewise.
+ * dv-bfin_wdog.c (bfin_wdog_io_write_buffer): Call
+ dv_bfin_mmr_require_16_32.
+ (bfin_wdog_io_read_buffer): Likewise. Return 0 when
+ dv_bfin_mmr_require_16 fails.
+ * dv-bfin_wp.c (bfin_wp_io_write_buffer): Call
+ dv_bfin_mmr_require_32. Return 0 in the default case.
+ (bfin_wp_io_read_buffer): Likewise. Delete while(1) loop.
+ * tconfig.h: Delete file.
+
2015-12-26 Mike Frysinger <vapier@gentoo.org>
* bfin-sim.c (decode_LDST_0): Add 4th element to posts array.
#include "dv-bfin_mmu.h"
static void
-bfin_mmr_invalid (struct hw *me, SIM_CPU *cpu, address_word addr,
- unsigned nr_bytes, bool write)
+bfin_mmr_invalid (struct hw *me, address_word addr,
+ unsigned nr_bytes, bool write, bool missing)
{
- if (!cpu)
- cpu = hw_system_cpu (me);
+ SIM_CPU *cpu = hw_system_cpu (me);
+ const char *rw = write ? "write" : "read";
+ const char *reason =
+ missing ? "no such register" :
+ (addr & 3) ? "must be 32-bit aligned" : "invalid length";
/* Only throw a fit if the cpu is doing the access. DMA/GDB simply
go unnoticed. Not exactly hardware behavior, but close enough. */
if (!cpu)
{
- sim_io_eprintf (hw_system (me), "%s: invalid MMR access @ %#x\n",
- hw_path (me), addr);
+ sim_io_eprintf (hw_system (me),
+ "%s: invalid MMR %s at %#x length %u: %s\n",
+ hw_path (me), rw, addr, nr_bytes, reason);
return;
}
- HW_TRACE ((me, "invalid MMR %s to 0x%08lx length %u",
- write ? "write" : "read", (unsigned long) addr, nr_bytes));
+ HW_TRACE ((me, "invalid MMR %s at %#x length %u: %s",
+ rw, addr, nr_bytes, reason));
- /* XXX: is this what hardware does ? */
+ /* XXX: is this what hardware does ? What about priority of unaligned vs
+ wrong length vs missing register ? What about system-vs-core ? */
+ /* XXX: We should move this addr check to a model property so we get the
+ same behavior regardless of where we map the model. */
if (addr >= BFIN_CORE_MMR_BASE)
/* XXX: This should be setting up CPLB fault addrs ? */
mmu_process_fault (cpu, addr, write, false, false, true);
dv_bfin_mmr_invalid (struct hw *me, address_word addr, unsigned nr_bytes,
bool write)
{
- bfin_mmr_invalid (me, NULL, addr, nr_bytes, write);
+ bfin_mmr_invalid (me, addr, nr_bytes, write, true);
}
-void
+bool
dv_bfin_mmr_require (struct hw *me, address_word addr, unsigned nr_bytes,
unsigned size, bool write)
{
- if (nr_bytes != size)
- dv_bfin_mmr_invalid (me, addr, nr_bytes, write);
-}
-
-static bool
-bfin_mmr_check (struct hw *me, SIM_CPU *cpu, address_word addr,
- unsigned nr_bytes, bool write)
-{
- if (addr >= BFIN_CORE_MMR_BASE)
- {
- /* All Core MMRs are aligned 32bits. */
- if ((addr & 3) == 0 && nr_bytes == 4)
- return true;
- }
- else if (addr >= BFIN_SYSTEM_MMR_BASE)
- {
- /* All System MMRs are 32bit aligned, but can be 16bits or 32bits. */
- if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4))
- return true;
- }
- else
+ if ((addr & 0x3) == 0 && nr_bytes == size)
return true;
- /* Still here ? Must be crap. */
- bfin_mmr_invalid (me, cpu, addr, nr_bytes, write);
-
+ bfin_mmr_invalid (me, addr, nr_bytes, write, false);
return false;
}
+/* For 32-bit memory mapped registers that allow 16-bit or 32-bit access. */
bool
-dv_bfin_mmr_check (struct hw *me, address_word addr, unsigned nr_bytes,
- bool write)
-{
- return bfin_mmr_check (me, NULL, addr, nr_bytes, write);
-}
-
-int
-device_io_read_buffer (device *me, void *source, int space,
- address_word addr, unsigned nr_bytes,
- SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
+dv_bfin_mmr_require_16_32 (struct hw *me, address_word addr, unsigned nr_bytes,
+ bool write)
{
- struct hw *dv_me = (struct hw *) me;
-
- if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
- return nr_bytes;
-
- if (bfin_mmr_check (dv_me, cpu, addr, nr_bytes, false))
- if (cpu)
- {
- sim_cpu_hw_io_read_buffer (cpu, cia, dv_me, source, space,
- addr, nr_bytes);
- return nr_bytes;
- }
- else
- return sim_hw_io_read_buffer (sd, dv_me, source, space, addr, nr_bytes);
- else
- return 0;
-}
+ if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4))
+ return true;
-int
-device_io_write_buffer (device *me, const void *source, int space,
- address_word addr, unsigned nr_bytes,
- SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
-{
- struct hw *dv_me = (struct hw *) me;
-
- if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
- return nr_bytes;
-
- if (bfin_mmr_check (dv_me, cpu, addr, nr_bytes, true))
- if (cpu)
- {
- sim_cpu_hw_io_write_buffer (cpu, cia, dv_me, source, space,
- addr, nr_bytes);
- return nr_bytes;
- }
- else
- return sim_hw_io_write_buffer (sd, dv_me, source, space, addr, nr_bytes);
- else
- return 0;
+ bfin_mmr_invalid (me, addr, nr_bytes, write, false);
+ return false;
}
unsigned int dv_get_bus_num (struct hw *me)
})
\f
void dv_bfin_mmr_invalid (struct hw *, address_word, unsigned nr_bytes, bool write);
-void dv_bfin_mmr_require (struct hw *, address_word, unsigned nr_bytes, unsigned size, bool write);
-bool dv_bfin_mmr_check (struct hw *, address_word, unsigned nr_bytes, bool write);
-
+bool dv_bfin_mmr_require (struct hw *, address_word, unsigned nr_bytes, unsigned size, bool write);
+/* For 32-bit memory mapped registers that allow 16-bit or 32-bit access. */
+bool dv_bfin_mmr_require_16_32 (struct hw *, address_word, unsigned nr_bytes, bool write);
+/* For 32-bit memory mapped registers that only allow 16-bit access. */
#define dv_bfin_mmr_require_16(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 2, write)
+/* For 32-bit memory mapped registers that only allow 32-bit access. */
#define dv_bfin_mmr_require_32(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 4, write)
\f
#define HW_TRACE_WRITE() \
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - cec->base;
bu32 mmr_off;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - cec->base;
valuep = (void *)((unsigned long)cec + mmr_base() + mmr_off);
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - ctimer->base;
valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off);
bu32 mmr_off;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - ctimer->base;
valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off);
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
default:
/* XXX: The HW lets the pad regions be read/written ... */
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr % dma->base;
valuep = (void *)((unsigned long)dma + mmr_base() + mmr_off);
value16p = valuep;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
bfin_ebiu_amc_write_amgctl (me, amc, value);
break;
case mmr_offset(bf50x.ambctl0):
break;
case mmr_offset(bf50x.mode):
/* XXX: implement this. */
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
break;
case mmr_offset(bf50x.fctl):
/* XXX: implement this. */
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
bfin_ebiu_amc_write_amgctl (me, amc, value);
break;
case mmr_offset(bf53x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
bfin_ebiu_amc_write_amgctl (me, amc, value);
break;
case mmr_offset(bf54x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - amc->base;
{
case mmr_offset(amgctl):
case mmr_offset(bf50x.fctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16);
break;
case mmr_offset(bf50x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16);
break;
case mmr_offset(bf53x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16);
break;
case mmr_offset(bf54x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - amc->base;
valuep = (void *)((unsigned long)amc + mmr_base() + mmr_off);
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
{
case mmr_offset(errmst):
case mmr_offset(rstctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
break;
default:
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
*value32p = value;
break;
}
bu16 *value16p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
mmr_off = addr - ddrc->base;
valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off);
value16p = valuep;
{
case mmr_offset(errmst):
case mmr_offset(rstctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
default:
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
dv_store_4 (dest, *value32p);
break;
}
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
case mmr_offset(sdbctl):
if (sdc->type == 561)
{
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
*value32p = value;
}
else
{
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
}
break;
case mmr_offset(sdrrc):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
break;
case mmr_offset(sdstat):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
/* XXX: Some bits are W1C ... */
break;
}
bu16 *value16p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - sdc->base;
valuep = (void *)((unsigned long)sdc + mmr_base() + mmr_off);
value16p = valuep;
case mmr_offset(sdbctl):
if (sdc->type == 561)
{
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
dv_store_4 (dest, *value32p);
}
else
{
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
}
break;
case mmr_offset(sdrrc):
case mmr_offset(sdstat):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
}
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
/* XXX: 16bit accesses are allowed ... */
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
value = dv_load_4 (source);
mmr_off = addr - emac->base;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
/* XXX: 16bit accesses are allowed ... */
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
mmr_off = addr - emac->base;
valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
switch (mmr_off)
{
case mmr_offset(status):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
dv_w1c_2 (value16p, value, 0x1ff);
break;
case mmr_offset(hcount):
case mmr_offset(frame):
case mmr_offset(line):
case mmr_offset(clkdiv):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
break;
case mmr_offset(control):
case mmr_offset(fs2p_lavf):
case mmr_offset(clip):
case mmr_offset(err):
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
*value32p = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
mmr_off = addr - eppi->base;
valuep = (void *)((unsigned long)eppi + mmr_base() + mmr_off);
value16p = valuep;
case mmr_offset(frame):
case mmr_offset(line):
case mmr_offset(clkdiv):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
case mmr_offset(control):
case mmr_offset(fs2p_lavf):
case mmr_offset(clip):
case mmr_offset(err):
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
dv_store_4 (dest, *value32p);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - evt->base;
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - evt->base;
HW_TRACE_READ ();
bu16 *valuep;
bu32 data = port->data;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - port->base;
valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(data):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
/* If updating masks, make sure we send updated port info. */
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - port->base;
valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(data):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ mmr_off = addr - port->base;
+
+ /* Invalid access mode is higher priority than missing register. */
+ if (mmr_off == mmr_offset (mux))
+ {
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+ }
+ else
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
value = dv_load_2 (source);
- mmr_off = addr - port->base;
valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_WRITE ();
- if (mmr_off == mmr_offset (mux))
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
- else
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(fer):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
/* If tweaking output pins, make sure we send updated port info. */
void *valuep;
mmr_off = addr - port->base;
+
+ /* Invalid access mode is higher priority than missing register. */
+ if (mmr_off == mmr_offset (mux))
+ {
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+ }
+ else
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
value16p = valuep;
value32p = valuep;
HW_TRACE_READ ();
- if (mmr_off == mmr_offset (mux))
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
- else
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(data):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
switch (mmr_off)
{
case mmr_offset(config):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
break;
case mmr_offset(counter):
case mmr_offset(period):
case mmr_offset(width):
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
*value32p = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - gptimer->base;
valuep = (void *)((unsigned long)gptimer + mmr_base() + mmr_off);
value16p = valuep;
switch (mmr_off)
{
case mmr_offset(config):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
case mmr_offset(counter):
case mmr_offset(period):
case mmr_offset(width):
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
dv_store_4 (dest, *value32p);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - jtag->base;
valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - jtag->base;
valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off);
value = *valuep;
break;
default:
- while (1) /* Core MMRs -> exception -> doesn't return. */
- dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
+ return 0;
}
dv_store_4 (dest, value);
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - mmu->base;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - mmu->base;
valuep = (void *)((unsigned long)mmu + mmr_base() + mmr_off);
dv_store_4 (dest, *valuep);
break;
default:
- while (1) /* Core MMRs -> exception -> doesn't return. */
- dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
+ return 0;
}
return nr_bytes;
bu32 value;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - nfc->base;
valuep = (void *)((unsigned long)nfc + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(ctl):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - nfc->base;
valuep = (void *)((unsigned long)nfc + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(ctl):
/* These regs are write only. */
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
{
int page;
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
/* XXX: Seems like these bits aren't writable. */
*value16p = value & 0x39FF;
break;
}
case mmr_offset(ben):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
/* XXX: All bits seem to be writable. */
*value16p = value;
break;
case mmr_offset(status):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
/* XXX: All bits seem to be W1C. */
dv_w1c_2 (value16p, value, -1);
break;
case mmr_offset(data1):
case mmr_offset(data2):
case mmr_offset(data3):
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
*value32p = value;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - otp->base;
valuep = (void *)((unsigned long)otp + mmr_base() + mmr_off);
value16p = valuep;
case mmr_offset(control):
case mmr_offset(ben):
case mmr_offset(status):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
case mmr_offset(timing):
case mmr_offset(data1):
case mmr_offset(data2):
case mmr_offset(data3):
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
dv_store_4 (dest, *value32p);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - pfmon->base;
valuep = (void *)((unsigned long)pfmon + mmr_base() + mmr_off);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - pfmon->base;
valuep = (void *)((unsigned long)pfmon + mmr_base() + mmr_off);
value = *valuep;
break;
default:
- while (1) /* Core MMRs -> exception -> doesn't return. */
- dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
+ return 0;
}
dv_store_4 (dest, value);
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ /* XXX: The hardware allows 16 or 32 bit accesses ... */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
HW_TRACE_WRITE ();
- /* XXX: The hardware allows 16 or 32 bit accesses ... */
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(request):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
#if 0
bu32 mmr_off;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ /* XXX: The hardware allows 16 or 32 bit accesses ... */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - pint->base;
valuep = (void *)((unsigned long)pint + mmr_base() + mmr_off);
HW_TRACE_READ ();
- /* XXX: The hardware allows 16 or 32 bit accesses ... */
- dv_bfin_mmr_require_32 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(request):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
switch (mmr_off)
{
case mmr_offset(pll_stat):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
case mmr_offset(chipid):
/* Discard writes. */
break;
default:
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
*value16p = value;
break;
}
bu16 *value16p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - pll->base;
valuep = (void *)((unsigned long)pll + mmr_base() + mmr_off);
value16p = valuep;
dv_store_4 (dest, *value32p);
break;
default:
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
}
bu32 value;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - ppi->base;
valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(control):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - ppi->base;
valuep = (void *)((unsigned long)ppi + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(control):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - rtc->base;
valuep = (void *)((unsigned long)rtc + mmr_base() + mmr_off);
value16p = valuep;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - sic->base;
valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
value16p = valuep;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - sic->base;
valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
value16p = valuep;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - sic->base;
valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
value16p = valuep;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - sic->base;
valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
value16p = valuep;
bu32 value;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - spi->base;
valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(stat):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - spi->base;
valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(rdbr):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - trace->base;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - trace->base;
HW_TRACE_READ ();
break;
}
default:
- while (1) /* Core MMRs -> exception -> doesn't return. */
- dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
+ return 0;
}
dv_store_4 (dest, value);
bu32 value;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - twi->base;
valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
switch (mmr_off)
{
case mmr_offset(clkdiv):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - twi->base;
valuep = (void *)((unsigned long)twi + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(clkdiv):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - uart->base;
valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
/* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
switch (mmr_off)
{
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - uart->base;
valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(dll):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_2 (source);
mmr_off = addr - uart->base;
valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
HW_TRACE_WRITE ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
-
/* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
switch (mmr_off)
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu16 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - uart->base;
valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
HW_TRACE_READ ();
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
-
switch (mmr_off)
{
case mmr_offset(rbr):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
if (nr_bytes == 4)
value = dv_load_4 (source);
else
bu32 *value32p;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - wdog->base;
valuep = (void *)((unsigned long)wdog + mmr_base() + mmr_off);
value16p = valuep;
switch (mmr_off)
{
case mmr_offset(ctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16p);
break;
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - wp->base;
valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off);
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 value;
bu32 *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - wp->base;
valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off);
value = *valuep;
break;
default:
- while (1) /* Core MMRs -> exception -> doesn't return. */
- dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
+ return 0;
}
dv_store_4 (dest, value);
+++ /dev/null
-/* Blackfin target configuration file. -*- C -*- */
-
-/* We use this so that we are passed the requesting CPU for HW acesses.
- Common sim core by default sets hw_system_cpu to NULL for WITH_HW. */
-#define WITH_DEVICES 1
projects / thirdparty / binutils-gdb.git / commitdiff
