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Commit | Line | Data |
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d006af40 AF |
1 | From 7c44c8a989ad01bd7cd02370d4ca4a742db218be Mon Sep 17 00:00:00 2001 |
2 | From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
3 | Date: Tue, 25 Sep 2012 15:46:34 +0200 | |
4 | Subject: [PATCH 2/6] mt9m032: Fix PLL setup | |
5 | ||
6 | The MT9M032 PLL was assumed to be identical to the MT9P031 PLL but | |
7 | differs significantly. Update the registers definitions and PLL limits | |
8 | according to the datasheet. | |
9 | ||
10 | Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
11 | --- | |
12 | drivers/media/i2c/mt9m032.c | 24 +++++++++++++----------- | |
13 | 1 file changed, 13 insertions(+), 11 deletions(-) | |
14 | ||
15 | diff --git a/drivers/media/i2c/mt9m032.c b/drivers/media/i2c/mt9m032.c | |
16 | index f80c1d7e..30d755a 100644 | |
17 | --- a/drivers/media/i2c/mt9m032.c | |
18 | +++ b/drivers/media/i2c/mt9m032.c | |
19 | @@ -87,7 +87,7 @@ | |
20 | #define MT9M032_RESTART 0x0b | |
21 | #define MT9M032_RESET 0x0d | |
22 | #define MT9M032_PLL_CONFIG1 0x11 | |
23 | -#define MT9M032_PLL_CONFIG1_OUTDIV_MASK 0x3f | |
24 | +#define MT9M032_PLL_CONFIG1_PREDIV_MASK 0x3f | |
25 | #define MT9M032_PLL_CONFIG1_MUL_SHIFT 8 | |
26 | #define MT9M032_READ_MODE1 0x1e | |
27 | #define MT9M032_READ_MODE2 0x20 | |
28 | @@ -106,6 +106,8 @@ | |
29 | #define MT9M032_GAIN_AMUL_SHIFT 6 | |
30 | #define MT9M032_GAIN_ANALOG_MASK 0x3f | |
31 | #define MT9M032_FORMATTER1 0x9e | |
32 | +#define MT9M032_FORMATTER1_PLL_P1_6 (1 << 8) | |
33 | +#define MT9M032_FORMATTER1_PARALLEL (1 << 12) | |
34 | #define MT9M032_FORMATTER2 0x9f | |
35 | #define MT9M032_FORMATTER2_DOUT_EN 0x1000 | |
36 | #define MT9M032_FORMATTER2_PIXCLK_EN 0x2000 | |
37 | @@ -121,8 +123,6 @@ | |
38 | #define MT9P031_PLL_CONTROL_PWROFF 0x0050 | |
39 | #define MT9P031_PLL_CONTROL_PWRON 0x0051 | |
40 | #define MT9P031_PLL_CONTROL_USEPLL 0x0052 | |
41 | -#define MT9P031_PLL_CONFIG2 0x11 | |
42 | -#define MT9P031_PLL_CONFIG2_P1_DIV_MASK 0x1f | |
43 | ||
44 | struct mt9m032 { | |
45 | struct v4l2_subdev subdev; | |
46 | @@ -255,13 +255,14 @@ static int mt9m032_setup_pll(struct mt9m032 *sensor) | |
47 | .n_max = 64, | |
48 | .m_min = 16, | |
49 | .m_max = 255, | |
50 | - .p1_min = 1, | |
51 | - .p1_max = 128, | |
52 | + .p1_min = 6, | |
53 | + .p1_max = 7, | |
54 | }; | |
55 | ||
56 | struct i2c_client *client = v4l2_get_subdevdata(&sensor->subdev); | |
57 | struct mt9m032_platform_data *pdata = sensor->pdata; | |
58 | struct aptina_pll pll; | |
59 | + u16 reg_val; | |
60 | int ret; | |
61 | ||
62 | pll.ext_clock = pdata->ext_clock; | |
63 | @@ -274,18 +275,19 @@ static int mt9m032_setup_pll(struct mt9m032 *sensor) | |
64 | sensor->pix_clock = pdata->pix_clock; | |
65 | ||
66 | ret = mt9m032_write(client, MT9M032_PLL_CONFIG1, | |
67 | - (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) | |
68 | - | (pll.p1 - 1)); | |
69 | - if (!ret) | |
70 | - ret = mt9m032_write(client, MT9P031_PLL_CONFIG2, pll.n - 1); | |
71 | + (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) | | |
72 | + ((pll.n - 1) & MT9M032_PLL_CONFIG1_PREDIV_MASK)); | |
73 | if (!ret) | |
74 | ret = mt9m032_write(client, MT9P031_PLL_CONTROL, | |
75 | MT9P031_PLL_CONTROL_PWRON | | |
76 | MT9P031_PLL_CONTROL_USEPLL); | |
77 | if (!ret) /* more reserved, Continuous, Master Mode */ | |
78 | ret = mt9m032_write(client, MT9M032_READ_MODE1, 0x8006); | |
79 | - if (!ret) /* Set 14-bit mode, select 7 divider */ | |
80 | - ret = mt9m032_write(client, MT9M032_FORMATTER1, 0x111e); | |
81 | + if (!ret) { | |
82 | + reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0) | |
83 | + | MT9M032_FORMATTER1_PARALLEL | 0x001e; /* 14-bit */ | |
84 | + ret = mt9m032_write(client, MT9M032_FORMATTER1, reg_val); | |
85 | + } | |
86 | ||
87 | return ret; | |
88 | } | |
89 | -- | |
90 | 1.7.10.4 | |
91 |