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kernel: update to 6.6.2
[ipfire-2.x.git] / src / patches / linux / aarch64 / 0008-rockchip-dt-add-some-overclocked-rk3328-boards.patch
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AF		 1From 5d1a97bca7efef833d4a9577c8a4951933f01303 Mon Sep 17 00:00:00 2001
2From: Arne Fitzenreiter <arne_f@ipfire.org>
3Date: Sun, 19 Nov 2023 13:27:36 +0000
4Subject: [PATCH 8/8] rockchip: dt: add some overclocked rk3328 boards
5
6nanopi-r2c, nanopi-r2c-plus-oc, nanopi-r2s-oc,
7orangepi-r1-plus-lts-oc, orangepi-r1-plus-oc
8
9Signed-off-by: Arne Fitzenreiter <arne_f@ipfire.org>
10---
11 arch/arm64/boot/dts/rockchip/Makefile | 5 ++++
12 .../dts/rockchip/rk3328-nanopi-r2c-oc.dts | 25 +++++++++++++++++++
13 .../rockchip/rk3328-nanopi-r2c-plus-oc.dts | 25 +++++++++++++++++++
14 .../dts/rockchip/rk3328-nanopi-r2s-oc.dts | 25 +++++++++++++++++++
15 .../rk3328-orangepi-r1-plus-lts-oc.dts | 25 +++++++++++++++++++
16 .../rockchip/rk3328-orangepi-r1-plus-oc.dts | 25 +++++++++++++++++++
17 6 files changed, 130 insertions(+)
18 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts
19 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus-oc.dts
20 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-oc.dts
21 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts-oc.dts
22 create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-oc.dts
23
24diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
25index f32fe64a84ed..4d1cb2b32572 100644
26--- a/arch/arm64/boot/dts/rockchip/Makefile
27+++ b/arch/arm64/boot/dts/rockchip/Makefile
28@@ -15,10 +15,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
29 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
30 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
31 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
32+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-oc.dtb
33 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
34+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus-oc.dtb
35 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
36+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s-oc.dtb
37 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
38+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-oc.dtb
39 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
40+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts-oc.dtb
41 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
42 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
43 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
44diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts
45new file mode 100644
46index 000000000000..617bcefb2122
47--- /dev/null
48+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts
49@@ -0,0 +1,25 @@
50+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
51+/*
52+ * overclock Nanopi R2C to 1.5 Ghz
53+ */
54+
55+/dts-v1/;
56+
57+#include "rk3328-nanopi-r2c.dts"
58+
59+/ {
60+ model = "FriendlyElec NanoPi R2C OC";
61+
62+ cpu0_opp_table: opp-table-0 {
63+ opp-1392000000 {
64+ opp-hz = /bits/ 64 <1392000000>;
65+ opp-microvolt = <1350000>;
66+ clock-latency-ns = <40000>;
67+ };
68+ opp-1512000000 {
69+ opp-hz = /bits/ 64 <1512000000>;
70+ opp-microvolt = <1400000>;
71+ clock-latency-ns = <40000>;
72+ };
73+ };
74+};
75diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus-oc.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus-oc.dts
76new file mode 100644
77index 000000000000..5324afec9271
78--- /dev/null
79+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus-oc.dts
80@@ -0,0 +1,25 @@
81+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
82+/*
83+ * overclock Nanopi R2C to 1.5 Ghz
84+ */
85+
86+/dts-v1/;
87+
88+#include "rk3328-nanopi-r2c-plus.dts"
89+
90+/ {
91+ model = "FriendlyElec NanoPi R2C Plus OC";
92+
93+ cpu0_opp_table: opp-table-0 {
94+ opp-1392000000 {
95+ opp-hz = /bits/ 64 <1392000000>;
96+ opp-microvolt = <1350000>;
97+ clock-latency-ns = <40000>;
98+ };
99+ opp-1512000000 {
100+ opp-hz = /bits/ 64 <1512000000>;
101+ opp-microvolt = <1400000>;
102+ clock-latency-ns = <40000>;
103+ };
104+ };
105+};
106diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-oc.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-oc.dts
107new file mode 100644
108index 000000000000..b94dc24d44e5
109--- /dev/null
110+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-oc.dts
111@@ -0,0 +1,25 @@
112+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
113+/*
114+ * overclock Nanopi R2S to 1.5 Ghz
115+ */
116+
117+/dts-v1/;
118+
119+#include "rk3328-nanopi-r2s.dts"
120+
121+/ {
122+ model = "FriendlyElec NanoPi R2S OC";
123+
124+ cpu0_opp_table: opp-table-0 {
125+ opp-1392000000 {
126+ opp-hz = /bits/ 64 <1392000000>;
127+ opp-microvolt = <1350000>;
128+ clock-latency-ns = <40000>;
129+ };
130+ opp-1512000000 {
131+ opp-hz = /bits/ 64 <1512000000>;
132+ opp-microvolt = <1400000>;
133+ clock-latency-ns = <40000>;
134+ };
135+ };
136+};
137diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts-oc.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts-oc.dts
138new file mode 100644
139index 000000000000..1cc615a5d8e0
140--- /dev/null
141+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts-oc.dts
142@@ -0,0 +1,25 @@
143+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
144+/*
145+ * overclock OrangePi R1 Plus LTS to 1.5 Ghz
146+ */
147+
148+/dts-v1/;
149+
150+#include "rk3328-orangepi-r1-plus-lts.dts"
151+
152+/ {
153+ model = "Xunlong Orange Pi R1 Plus LTS OC";
154+
155+ cpu0_opp_table: opp-table-0 {
156+ opp-1392000000 {
157+ opp-hz = /bits/ 64 <1392000000>;
158+ opp-microvolt = <1350000>;
159+ clock-latency-ns = <40000>;
160+ };
161+ opp-1512000000 {
162+ opp-hz = /bits/ 64 <1512000000>;
163+ opp-microvolt = <1400000>;
164+ clock-latency-ns = <40000>;
165+ };
166+ };
167+};
168diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-oc.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-oc.dts
169new file mode 100644
170index 000000000000..1a420d214f12
171--- /dev/null
172+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-oc.dts
173@@ -0,0 +1,25 @@
174+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
175+/*
176+ * overclock OrangePi R1 Plus to 1.5 Ghz
177+ */
178+
179+/dts-v1/;
180+
181+#include "rk3328-nanopi-r2s.dts"
182+
183+/ {
184+ model = "Xunlong Orange Pi R1 Plus OC";
185+
186+ cpu0_opp_table: opp-table-0 {
187+ opp-1392000000 {
188+ opp-hz = /bits/ 64 <1392000000>;
189+ opp-microvolt = <1350000>;
190+ clock-latency-ns = <40000>;
191+ };
192+ opp-1512000000 {
193+ opp-hz = /bits/ 64 <1512000000>;
194+ opp-microvolt = <1400000>;
195+ clock-latency-ns = <40000>;
196+ };
197+ };
198+};
199--
2002.34.1
201
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