projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 1a33ce65 TL |
1 | /* |
| 2 | * (C) Copyright 2000-2003 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| aa0d99fc | 5 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
| 1a33ce65 TL |
6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 7 | * | |
| 1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 1a33ce65 TL |
9 | */ |
| 10 | ||
| 11 | #include <config.h> | |
| 12 | #include <common.h> | |
| 13 | #include <asm/io.h> | |
| 14 | #include <asm/immap.h> | |
| 15 | ||
| 16 | DECLARE_GLOBAL_DATA_PTR; | |
| 17 | ||
| ab77bc54 | 18 | #if defined(CONFIG_CMD_NAND) |
| 1a33ce65 TL |
19 | #include <nand.h> |
| 20 | #include <linux/mtd/mtd.h> | |
| 21 | ||
| 3ba4c2d6 | 22 | #define SET_CLE 0x10 |
| 3ba4c2d6 | 23 | #define SET_ALE 0x08 |
| 1a33ce65 | 24 | |
| e4f69d1b | 25 | static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) |
| 1a33ce65 | 26 | { |
| 3ba4c2d6 | 27 | struct nand_chip *this = mtdinfo->priv; |
| e4f69d1b | 28 | volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; |
| 1a33ce65 | 29 | |
| cfa460ad | 30 | if (ctrl & NAND_CTRL_CHANGE) { |
| e4f69d1b | 31 | ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
| cfa460ad | 32 | |
| e4f69d1b | 33 | IO_ADDR_W &= ~(SET_ALE | SET_CLE); |
| 1a33ce65 | 34 | |
| e4f69d1b | 35 | if (ctrl & NAND_NCE) |
| 9017d932 TL |
36 | *nCE &= 0xFFFB; |
| 37 | else | |
| e4f69d1b | 38 | *nCE |= 0x0004; |
| 9017d932 | 39 | |
| e4f69d1b TL |
40 | if (ctrl & NAND_CLE) |
| 41 | IO_ADDR_W |= SET_CLE; | |
| 42 | if (ctrl & NAND_ALE) | |
| 43 | IO_ADDR_W |= SET_ALE; | |
| 1a33ce65 | 44 | |
| e4f69d1b TL |
45 | this->IO_ADDR_W = (void *)IO_ADDR_W; |
| 46 | } | |
| 1a33ce65 | 47 | |
| e4f69d1b TL |
48 | if (cmd != NAND_CMD_NONE) |
| 49 | writeb(cmd, this->IO_ADDR_W); | |
| 1a33ce65 TL |
50 | } |
| 51 | ||
| 52 | int board_nand_init(struct nand_chip *nand) | |
| 53 | { | |
| aa0d99fc | 54 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
| 1a33ce65 | 55 | |
| e4f69d1b TL |
56 | /* |
| 57 | * set up pin configuration - enabled 2nd output buffer's signals | |
| 58 | * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) | |
| 59 | * to use nCE signal | |
| 60 | */ | |
| aa0d99fc AW |
61 | clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); |
| 62 | setbits_8(&gpio->pddr_timer, 0x08); | |
| 63 | setbits_8(&gpio->ppd_timer, 0x08); | |
| 64 | out_8(&gpio->pclrr_timer, 0); | |
| 65 | out_8(&gpio->podr_timer, 0); | |
| 1a33ce65 | 66 | |
| 9017d932 | 67 | nand->chip_delay = 60; |
| cfa460ad WJ |
68 | nand->ecc.mode = NAND_ECC_SOFT; |
| 69 | nand->cmd_ctrl = nand_hwcontrol; | |
| 1a33ce65 | 70 | |
| 3ba4c2d6 | 71 | return 0; |
| 1a33ce65 TL |
72 | } |
| 73 | #endif |