[people/ms/u-boot.git] / board / ifm / ac14xx / ac14xx.c

/*
 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
 * (C) Copyright 2009 Dave Srl www.dave.eu
 * (C) Copyright 2010 ifm ecomatic GmbH
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <common.h>
#include <asm/bitops.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mpc512x.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif

static int eeprom_diag;
static int mac_diag;
static int gpio_diag;

DECLARE_GLOBAL_DATA_PTR;

static void gpio_configure(void)
{
	immap_t *im;
	gpio512x_t *gpioregs;

	im = (immap_t *) CONFIG_SYS_IMMR;
	gpioregs = &im->gpio;
	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */

	/*
	 * out_be32(&gpioregs->gpdir, 0xC2293020);
	 * workaround for a hardware effect: configure direction in pieces,
	 * setting all outputs at once drops the reset line too low and
	 * makes us lose the MII connection (breaks ethernet for us)
	 */
	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
	udelay(10);
	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
	udelay(10);
	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
	udelay(10);
	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */

	/* to turn from red to yellow when U-Boot runs */
	setbits_be32(&gpioregs->gpdat, 0x00002020);
	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
}

/* the physical location of the pins */
#define GPIOKEY_ROW_BITMASK	0x40000000
#define GPIOKEY_ROW_UPPER	0
#define GPIOKEY_ROW_LOWER	1

#define GPIOKEY_COL0_BITMASK	0x20000000
#define GPIOKEY_COL1_BITMASK	0x10000000
#define GPIOKEY_COL2_BITMASK	0x08000000

/* the logical presentation of pressed keys */
#define GPIOKEY_BIT_FNLEFT	(1 << 5)
#define GPIOKEY_BIT_FNRIGHT	(1 << 4)
#define GPIOKEY_BIT_DIRUP	(1 << 3)
#define GPIOKEY_BIT_DIRLEFT	(1 << 2)
#define GPIOKEY_BIT_DIRRIGHT	(1 << 1)
#define GPIOKEY_BIT_DIRDOWN	(1 << 0)

/* the hotkey combination which starts recovery */
#define GPIOKEY_BITS_RECOVERY	(GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
				 GPIOKEY_BIT_DIRDOWN)

static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
{

	if (row)
		setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
	else
		clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
	udelay(10);
}

static u32 gpio_querykbd(void)
{
	immap_t *im;
	gpio512x_t *gpioregs;
	u32 keybits;
	u32 input;

	im = (immap_t *)CONFIG_SYS_IMMR;
	gpioregs = &im->gpio;
	keybits = 0;

	/* query upper row */
	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
	input = in_be32(&gpioregs->gpdat);
	if ((input & GPIOKEY_COL0_BITMASK) == 0)
		keybits |= GPIOKEY_BIT_FNLEFT;
	if ((input & GPIOKEY_COL1_BITMASK) == 0)
		keybits |= GPIOKEY_BIT_DIRUP;
	if ((input & GPIOKEY_COL2_BITMASK) == 0)
		keybits |= GPIOKEY_BIT_FNRIGHT;

	/* query lower row */
	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
	input = in_be32(&gpioregs->gpdat);
	if ((input & GPIOKEY_COL0_BITMASK) == 0)
		keybits |= GPIOKEY_BIT_DIRLEFT;
	if ((input & GPIOKEY_COL1_BITMASK) == 0)
		keybits |= GPIOKEY_BIT_DIRRIGHT;
	if ((input & GPIOKEY_COL2_BITMASK) == 0)
		keybits |= GPIOKEY_BIT_DIRDOWN;

	/* return bit pattern for keys */
	return keybits;
}

/* excerpt from the recovery's hw_info.h */

struct __attribute__ ((__packed__)) eeprom_layout {
	char	magic[3];	/** 'ifm' */
	u8	len[2];		/** content length without magic/len fields */
	u8	version[3];	/** structure version */
	u8	type;		/** type of PCB */
	u8	reserved[0x37];	/** padding up to offset 0x40 */
	u8	macaddress[6];	/** ethernet MAC (for the mainboard) @0x40 */
};

#define HW_COMP_MAINCPU 2

static struct eeprom_layout eeprom_content;
static int eeprom_was_read;	/* has_been_read */
static int eeprom_is_valid;
static int eeprom_version;

#define get_eeprom_field_int(name) ({ \
	int value; \
	int idx; \
	value = 0; \
	for (idx = 0; idx < sizeof(name); idx++) { \
		value <<= 8; \
		value |= name[idx]; \
	} \
	value; \
})

static int read_eeprom(void)
{
	int eeprom_datalen;
	int ret;

	if (eeprom_was_read)
		return 0;

	eeprom_is_valid = 0;
	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
			CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
			(uchar *)&eeprom_content, sizeof(eeprom_content));
	if (eeprom_diag) {
		printf("DIAG: %s() read rc[%d], size[%d]\n",
			__func__, ret, sizeof(eeprom_content));
	}

	if (ret != 0)
		return -1;

	eeprom_was_read = 1;

	/*
	 * check validity of EEPROM content
	 * (check version, length, optionally checksum)
	 */
	eeprom_is_valid = 1;
	eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
	eeprom_version = get_eeprom_field_int(eeprom_content.version);

	if (eeprom_diag) {
		printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
			__func__, eeprom_content.magic[0],
			eeprom_content.magic[1], eeprom_content.magic[2],
			eeprom_datalen, eeprom_version, eeprom_content.type);
	}
	if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
		eeprom_is_valid = 0;
	if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
		eeprom_is_valid = 0;
	if ((eeprom_version != 1) && (eeprom_version != 2))
		eeprom_is_valid = 0;
	if (eeprom_content.type != HW_COMP_MAINCPU)
		eeprom_is_valid = 0;

	if (eeprom_diag)
		printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);

	return ret;
}

int mac_read_from_eeprom(void)
{
	const u8 *mac;
	const char *mac_txt;

	if (read_eeprom()) {
		printf("I2C EEPROM read failed.\n");
		return -1;
	}

	if (!eeprom_is_valid) {
		printf("I2C EEPROM content not valid\n");
		return -1;
	}

	mac = NULL;
	switch (eeprom_version) {
	case 1:
	case 2:
		mac = (const u8 *)&eeprom_content.macaddress;
		break;
	}

	if (mac && is_valid_ether_addr(mac)) {
		eth_setenv_enetaddr("ethaddr", mac);
		if (mac_diag) {
			mac_txt = getenv("ethaddr");
			if (mac_txt)
				printf("DIAG: MAC value [%s]\n", mac_txt);
			else
				printf("DIAG: failed to setup MAC env\n");
		}
	}

	return 0;
}

/*
 * BEWARE!
 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
 * which the ADS, Aria or PDM360NG boards are using
 * (the steps outlined here refer to the Micron datasheet)
 */
u32 sdram_init_seq[] = {
	/* item 6, at least one NOP after CKE went high */
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	/* item 7, precharge all; item 8, tRP (20ns) */
	CONFIG_SYS_DDRCMD_PCHG_ALL,
	CONFIG_SYS_DDRCMD_NOP,
	/* item 9, extended mode register; item 10, tMRD 10ns) */
	CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
	CONFIG_SYS_DDRCMD_NOP,
	/*
	 * item 11, (base) mode register _with_ reset DLL;
	 * item 12, tMRD (10ns)
	 */
	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
	CONFIG_SYS_MICRON_BMODE_PARAM,
	CONFIG_SYS_DDRCMD_NOP,
	/* item 13, precharge all; item 14, tRP (20ns) */
	CONFIG_SYS_DDRCMD_PCHG_ALL,
	CONFIG_SYS_DDRCMD_NOP,
	/*
	 * item 15, auto refresh (i.e. refresh with CKE held high);
	 * item 16, tRFC (70ns)
	 */
	CONFIG_SYS_DDRCMD_RFSH,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	/*
	 * item 17, auto refresh (i.e. refresh with CKE held high);
	 * item 18, tRFC (70ns)
	 */
	CONFIG_SYS_DDRCMD_RFSH,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	CONFIG_SYS_DDRCMD_NOP,
	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
	CONFIG_SYS_DDRCMD_NOP,
	/*
	 * item 21, "actually done", but make sure 200 DRAM clock cycles
	 * have passed after DLL reset before READ requests are issued
	 * (200 cycles at 160MHz -> 1.25 usec)
	 */
	/* EMPTY, optional, we don't do it */
};

phys_size_t initdram(int board_type)
{
	return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
}

int misc_init_r(void)
{
	u32 keys;
	char *s;
	int want_recovery;

	/* we use bus I2C-0 for the on-board eeprom */
	i2c_set_bus_num(0);

	/* setup GPIO directions and initial values */
	gpio_configure();

	/*
	 * enforce the start of the recovery system when
	 * - the appropriate keys were pressed
	 * - "some" external software told us to
	 * - a previous installation was aborted or has failed
	 */
	want_recovery = 0;
	keys = gpio_querykbd();
	if (gpio_diag)
		printf("GPIO keyboard status [0x%02X]\n", keys);
	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
		printf("detected recovery request (keyboard)\n");
		want_recovery = 1;
	}
	s = getenv("want_recovery");
	if ((s != NULL) && (*s != '\0')) {
		printf("detected recovery request (environment)\n");
		want_recovery = 1;
	}
	s = getenv("install_in_progress");
	if ((s != NULL) && (*s != '\0')) {
		printf("previous installation has not completed\n");
		want_recovery = 1;
	}
	s = getenv("install_failed");
	if ((s != NULL) && (*s != '\0')) {
		printf("previous installation has failed\n");
		want_recovery = 1;
	}
	if (want_recovery) {
		printf("enforced start of the recovery system\n");
		setenv("bootcmd", "run recovery");
	}

	/*
	 * boot the recovery system without waiting; boot the
	 * production system without waiting by default, only
	 * insert a pause (to provide a chance to get a prompt)
	 * when GPIO keys were pressed during power on
	 */
	if (want_recovery)
		setenv("bootdelay", "0");
	else if (!keys)
		setenv("bootdelay", "0");
	else
		setenv("bootdelay", "2");

	/* get the ethernet MAC from I2C EEPROM */
	mac_read_from_eeprom();

	return 0;
}

/* setup specific IO pad configuration */
static  iopin_t ioregs_init[] = {
	{	/* LPC CS3 */
		offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	{	/* LPC CS1 */
		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{	/* LPC CS2 */
		offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{	/* LPC CS4, CS5 */
		offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	{	/* SDHC CLK, CMD, D0, D1, D2, D3 */
		offsetof(struct ioctrl512x, io_control_pata_ior), 6,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	{	/* GPIO keyboard */
		offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO DN1 PF, LCD power, DN2 PF */
		offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO reset AS-i */
		offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO reset safety */
		offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO reset netX */
		offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO ma2 en */
		offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO SD CD, SD WP */
		offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* FEC RX DV */
		offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(2),
	},
	{	/* GPIO AS-i prog, AS-i done, LCD backlight */
		offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO AS-i wdg */
		offsetof(struct ioctrl512x, io_control_pci_req2), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO safety wdg */
		offsetof(struct ioctrl512x, io_control_pci_req1), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO netX wdg */
		offsetof(struct ioctrl512x, io_control_pci_req0), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO IRQ powerfail */
		offsetof(struct ioctrl512x, io_control_pci_inta), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO AS-i PWRD */
		offsetof(struct ioctrl512x, io_control_pci_frame), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO LED0, LED1 */
		offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
		offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/* DIU clk */
		offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(2),
	},
	{	/* FEC TX ER, CRS */
		offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	{	/* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
		offsetof(struct ioctrl512x, io_control_irq0), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	{	/*
		 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
		 * rdx 3-0, mdio, rx clk
		 */
		offsetof(struct ioctrl512x, io_control_psc0_0), 15,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	/* optional: make sure PSC3 remains the serial console */
	{	/* LPC CS6 */
		offsetof(struct ioctrl512x, io_control_psc3_4), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	/* make sure PSC4 remains available for SPI,
	    *BUT* PSC4_1 is a GPIO kind of SS! */
	{	/* enforce drive strength on the SPI pin */
		offsetof(struct ioctrl512x, io_control_psc4_0), 5,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{
		offsetof(struct ioctrl512x, io_control_psc4_1), 1,
		IO_PIN_OVER_FMUX,
		IO_PIN_FMUX(3),
	},
	/* optional: make sure PSC5 remains available for SPI */
	{	/* enforce drive strength on the SPI pin */
		offsetof(struct ioctrl512x, io_control_psc5_0), 5,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(1),
	},
	{	/* LPC TSIZ1 */
		offsetof(struct ioctrl512x, io_control_psc6_0), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(1) | IO_PIN_DS(2),
	},
	{	/* DIU hsync */
		offsetof(struct ioctrl512x, io_control_psc6_1), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(1),
	},
	{	/* DIU vsync */
		offsetof(struct ioctrl512x, io_control_psc6_4), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(1),
	},
	{	/* PSC7, part of DIU RGB */
		offsetof(struct ioctrl512x, io_control_psc7_0), 2,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(1),
	},
	{	/* PSC7, safety UART */
		offsetof(struct ioctrl512x, io_control_psc7_2), 2,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(0) | IO_PIN_DS(1),
	},
	{	/* DIU (part of) RGB[] */
		offsetof(struct ioctrl512x, io_control_psc8_3), 16,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(1),
	},
	{	/* DIU data enable */
		offsetof(struct ioctrl512x, io_control_psc11_4), 1,
		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
		IO_PIN_FMUX(2) | IO_PIN_DS(1),
	},
	/* reduce LPB drive strength for improved EMI */
	{	/* LPC OE, LPC RW */
		offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{	/* LPC AX03 through LPC AD00 */
		offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{	/* LPC CS5 */
		offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{	/* SDHC CLK */
		offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
	{	/* SDHC DATA */
		offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
		IO_PIN_OVER_DRVSTR,
		IO_PIN_DS(2),
	},
};

int checkboard(void)
{
	puts("Board: ifm AC14xx\n");

	/* initialize function mux & slew rate IO inter alia on IO Pins  */
	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
fcc7fe42 AG	1	/*
	2	* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
	3	* (C) Copyright 2009 Dave Srl www.dave.eu
	4	* (C) Copyright 2010 ifm ecomatic GmbH
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*/
	14
	15	#include <common.h>
	16	#include <asm/bitops.h>
	17	#include <command.h>
	18	#include <asm/io.h>
	19	#include <asm/processor.h>
	20	#include <asm/mpc512x.h>
	21	#include <fdt_support.h>
	22	#ifdef CONFIG_MISC_INIT_R
	23	#include <i2c.h>
	24	#endif
	25
527a1c71 GS	26	static int eeprom_diag;
	27	static int mac_diag;
	28	static int gpio_diag;
	29
fcc7fe42 AG	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	static void gpio_configure(void)
	33	{
	34	immap_t *im;
	35	gpio512x_t *gpioregs;
	36
	37	im = (immap_t *) CONFIG_SYS_IMMR;
	38	gpioregs = &im->gpio;
	39	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
	40	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
	41
	42	/*
	43	* out_be32(&gpioregs->gpdir, 0xC2293020);
b5992e77	44	* workaround for a hardware effect: configure direction in pieces,
fcc7fe42 AG	45	* setting all outputs at once drops the reset line too low and
	46	* makes us lose the MII connection (breaks ethernet for us)
	47	*/
	48	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
	49	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
	50	udelay(10);
	51	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
	52	udelay(10);
	53	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
	54	udelay(10);
	55	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
	56
	57	/* to turn from red to yellow when U-Boot runs */
	58	setbits_be32(&gpioregs->gpdat, 0x00002020);
	59	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
	60	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
	61	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
	62	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
	63	}
	64
	65	/* the physical location of the pins */
	66	#define GPIOKEY_ROW_BITMASK 0x40000000
	67	#define GPIOKEY_ROW_UPPER 0
	68	#define GPIOKEY_ROW_LOWER 1
	69
	70	#define GPIOKEY_COL0_BITMASK 0x20000000
	71	#define GPIOKEY_COL1_BITMASK 0x10000000
	72	#define GPIOKEY_COL2_BITMASK 0x08000000
	73
	74	/* the logical presentation of pressed keys */
	75	#define GPIOKEY_BIT_FNLEFT (1 << 5)
	76	#define GPIOKEY_BIT_FNRIGHT (1 << 4)
	77	#define GPIOKEY_BIT_DIRUP (1 << 3)
	78	#define GPIOKEY_BIT_DIRLEFT (1 << 2)
	79	#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
	80	#define GPIOKEY_BIT_DIRDOWN (1 << 0)
	81
	82	/* the hotkey combination which starts recovery */
	83	#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT \| GPIOKEY_BIT_DIRUP \| \
	84	GPIOKEY_BIT_DIRDOWN)
	85
	86	static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
	87	{
	88
	89	if (row)
	90	setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
	91	else
	92	clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
	93	udelay(10);
	94	}
	95
	96	static u32 gpio_querykbd(void)
	97	{
	98	immap_t *im;
	99	gpio512x_t *gpioregs;
	100	u32 keybits;
	101	u32 input;
	102
	103	im = (immap_t *)CONFIG_SYS_IMMR;
	104	gpioregs = &im->gpio;
	105	keybits = 0;
	106
	107	/* query upper row */
	108	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
109	input = in_be32(&gpioregs->gpdat);
110	if ((input & GPIOKEY_COL0_BITMASK) == 0)
111	keybits \|= GPIOKEY_BIT_FNLEFT;
112	if ((input & GPIOKEY_COL1_BITMASK) == 0)
113	keybits \|= GPIOKEY_BIT_DIRUP;
114	if ((input & GPIOKEY_COL2_BITMASK) == 0)
115	keybits \|= GPIOKEY_BIT_FNRIGHT;
116
117	/* query lower row */
118	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
119	input = in_be32(&gpioregs->gpdat);
120	if ((input & GPIOKEY_COL0_BITMASK) == 0)
121	keybits \|= GPIOKEY_BIT_DIRLEFT;
122	if ((input & GPIOKEY_COL1_BITMASK) == 0)
123	keybits \|= GPIOKEY_BIT_DIRRIGHT;
124	if ((input & GPIOKEY_COL2_BITMASK) == 0)
125	keybits \|= GPIOKEY_BIT_DIRDOWN;
126
127	/* return bit pattern for keys */
128	return keybits;
129	}
130
131	/* excerpt from the recovery's hw_info.h */
132
fcc7fe42 AG	133	struct __attribute__ ((__packed__)) eeprom_layout {
	134	char magic[3]; /** 'ifm' */
	135	u8 len[2]; /** content length without magic/len fields */
	136	u8 version[3]; /** structure version */
	137	u8 type; /** type of PCB */
	138	u8 reserved[0x37]; /** padding up to offset 0x40 */
	139	u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
	140	};
	141
	142	#define HW_COMP_MAINCPU 2
	143
	144	static struct eeprom_layout eeprom_content;
	145	static int eeprom_was_read; /* has_been_read */
	146	static int eeprom_is_valid;
	147	static int eeprom_version;
	148
	149	#define get_eeprom_field_int(name) ({ \
	150	int value; \
	151	int idx; \
	152	value = 0; \
	153	for (idx = 0; idx < sizeof(name); idx++) { \
	154	value <<= 8; \
	155	value \|= name[idx]; \
	156	} \
	157	value; \
	158	})
	159
	160	static int read_eeprom(void)
	161	{
	162	int eeprom_datalen;
	163	int ret;
	164
	165	if (eeprom_was_read)
	166	return 0;
	167
	168	eeprom_is_valid = 0;
	169	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
	170	CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
	171	(uchar *)&eeprom_content, sizeof(eeprom_content));
	172	if (eeprom_diag) {
	173	printf("DIAG: %s() read rc[%d], size[%d]\n",
	174	__func__, ret, sizeof(eeprom_content));
	175	}
	176
	177	if (ret != 0)
	178	return -1;
	179
	180	eeprom_was_read = 1;
	181
	182	/*
	183	* check validity of EEPROM content
	184	* (check version, length, optionally checksum)
	185	*/
	186	eeprom_is_valid = 1;
	187	eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
	188	eeprom_version = get_eeprom_field_int(eeprom_content.version);
	189
	190	if (eeprom_diag) {
	191	printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
	192	__func__, eeprom_content.magic[0],
	193	eeprom_content.magic[1], eeprom_content.magic[2],
	194	eeprom_datalen, eeprom_version, eeprom_content.type);
	195	}
	196	if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
197	eeprom_is_valid = 0;
198	if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
199	eeprom_is_valid = 0;
200	if ((eeprom_version != 1) && (eeprom_version != 2))
201	eeprom_is_valid = 0;
202	if (eeprom_content.type != HW_COMP_MAINCPU)
203	eeprom_is_valid = 0;
204
205	if (eeprom_diag)
206	printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
207
208	return ret;
209	}
210
211	int mac_read_from_eeprom(void)
212	{
213	const u8 *mac;
186f9c13	214	const char *mac_txt;
fcc7fe42 AG	215
	216	if (read_eeprom()) {
	217	printf("I2C EEPROM read failed.\n");
	218	return -1;
	219	}
	220
	221	if (!eeprom_is_valid) {
	222	printf("I2C EEPROM content not valid\n");
	223	return -1;
	224	}
	225
	226	mac = NULL;
	227	switch (eeprom_version) {
	228	case 1:
	229	case 2:
	230	mac = (const u8 *)&eeprom_content.macaddress;
	231	break;
	232	}
	233
	234	if (mac && is_valid_ether_addr(mac)) {
	235	eth_setenv_enetaddr("ethaddr", mac);
527a1c71 GS	236	if (mac_diag) {
	237	mac_txt = getenv("ethaddr");
	238	if (mac_txt)
	239	printf("DIAG: MAC value [%s]\n", mac_txt);
	240	else
	241	printf("DIAG: failed to setup MAC env\n");
	242	}
fcc7fe42 AG	243	}
	244
	245	return 0;
	246	}
	247
	248	/*
	249	* BEWARE!
	250	* this board uses DDR1(!) Micron SDRAM, NOT the DDR2
	251	* which the ADS, Aria or PDM360NG boards are using
	252	* (the steps outlined here refer to the Micron datasheet)
	253	*/
	254	u32 sdram_init_seq[] = {
	255	/* item 6, at least one NOP after CKE went high */
	256	CONFIG_SYS_DDRCMD_NOP,
	257	CONFIG_SYS_DDRCMD_NOP,
	258	CONFIG_SYS_DDRCMD_NOP,
	259	CONFIG_SYS_DDRCMD_NOP,
	260	CONFIG_SYS_DDRCMD_NOP,
	261	CONFIG_SYS_DDRCMD_NOP,
	262	CONFIG_SYS_DDRCMD_NOP,
	263	CONFIG_SYS_DDRCMD_NOP,
	264	CONFIG_SYS_DDRCMD_NOP,
	265	CONFIG_SYS_DDRCMD_NOP,
	266	/* item 7, precharge all; item 8, tRP (20ns) */
	267	CONFIG_SYS_DDRCMD_PCHG_ALL,
	268	CONFIG_SYS_DDRCMD_NOP,
	269	/* item 9, extended mode register; item 10, tMRD 10ns) */
	270	CONFIG_SYS_MICRON_EMODE \| CONFIG_SYS_MICRON_EMODE_PARAM,
	271	CONFIG_SYS_DDRCMD_NOP,
	272	/*
	273	* item 11, (base) mode register _with_ reset DLL;
	274	* item 12, tMRD (10ns)
	275	*/
	276	CONFIG_SYS_MICRON_BMODE \| CONFIG_SYS_MICRON_BMODE_RSTDLL \|
	277	CONFIG_SYS_MICRON_BMODE_PARAM,
	278	CONFIG_SYS_DDRCMD_NOP,
	279	/* item 13, precharge all; item 14, tRP (20ns) */
	280	CONFIG_SYS_DDRCMD_PCHG_ALL,
	281	CONFIG_SYS_DDRCMD_NOP,
	282	/*
	283	* item 15, auto refresh (i.e. refresh with CKE held high);
	284	* item 16, tRFC (70ns)
	285	*/
	286	CONFIG_SYS_DDRCMD_RFSH,
	287	CONFIG_SYS_DDRCMD_NOP,
	288	CONFIG_SYS_DDRCMD_NOP,
	289	CONFIG_SYS_DDRCMD_NOP,
	290	CONFIG_SYS_DDRCMD_NOP,
	291	CONFIG_SYS_DDRCMD_NOP,
	292	CONFIG_SYS_DDRCMD_NOP,
	293	CONFIG_SYS_DDRCMD_NOP,
	294	CONFIG_SYS_DDRCMD_NOP,
	295	/*
	296	* item 17, auto refresh (i.e. refresh with CKE held high);
	297	* item 18, tRFC (70ns)
	298	*/
	299	CONFIG_SYS_DDRCMD_RFSH,
	300	CONFIG_SYS_DDRCMD_NOP,
	301	CONFIG_SYS_DDRCMD_NOP,
	302	CONFIG_SYS_DDRCMD_NOP,
	303	CONFIG_SYS_DDRCMD_NOP,
	304	CONFIG_SYS_DDRCMD_NOP,
	305	CONFIG_SYS_DDRCMD_NOP,
	306	CONFIG_SYS_DDRCMD_NOP,
307	CONFIG_SYS_DDRCMD_NOP,
308	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
309	CONFIG_SYS_MICRON_BMODE \| CONFIG_SYS_MICRON_BMODE_PARAM,
310	CONFIG_SYS_DDRCMD_NOP,
311	/*
312	* item 21, "actually done", but make sure 200 DRAM clock cycles
313	* have passed after DLL reset before READ requests are issued
314	* (200 cycles at 160MHz -> 1.25 usec)
315	*/
316	/* EMPTY, optional, we don't do it */
317	};
318
319	phys_size_t initdram(int board_type)
320	{
321	return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
322	}
323
324	int misc_init_r(void)
325	{
326	u32 keys;
327	char *s;
328	int want_recovery;
329
330	/* we use bus I2C-0 for the on-board eeprom */
331	i2c_set_bus_num(0);
332
333	/* setup GPIO directions and initial values */
334	gpio_configure();
335
336	/*
b5992e77	337	* enforce the start of the recovery system when
fcc7fe42	338	* - the appropriate keys were pressed
fcc7fe42	339	* - "some" external software told us to
14d4c5f3	340	* - a previous installation was aborted or has failed
fcc7fe42 AG	341	*/
	342	want_recovery = 0;
	343	keys = gpio_querykbd();
527a1c71 GS	344	if (gpio_diag)
527a1c71 GS	345	printf("GPIO keyboard status [0x%02X]\n", keys);
fcc7fe42	346	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
527a1c71	347	printf("detected recovery request (keyboard)\n");
fcc7fe42 AG	348	want_recovery = 1;
fcc7fe42 AG	349	}
14d4c5f3 GS	350	s = getenv("want_recovery");
	351	if ((s != NULL) && (*s != '\0')) {
	352	printf("detected recovery request (environment)\n");
	353	want_recovery = 1;
	354	}
fcc7fe42 AG	355	s = getenv("install_in_progress");
fcc7fe42 AG	356	if ((s != NULL) && (*s != '\0')) {
527a1c71	357	printf("previous installation has not completed\n");
fcc7fe42 AG	358	want_recovery = 1;
	359	}
	360	s = getenv("install_failed");
	361	if ((s != NULL) && (*s != '\0')) {
527a1c71	362	printf("previous installation has failed\n");
fcc7fe42 AG	363	want_recovery = 1;
fcc7fe42 AG	364	}
527a1c71 GS	365	if (want_recovery) {
527a1c71 GS	366	printf("enforced start of the recovery system\n");
fcc7fe42	367	setenv("bootcmd", "run recovery");
527a1c71	368	}
fcc7fe42 AG	369
	370	/*
	371	* boot the recovery system without waiting; boot the
	372	* production system without waiting by default, only
	373	* insert a pause (to provide a chance to get a prompt)
	374	* when GPIO keys were pressed during power on
	375	*/
	376	if (want_recovery)
	377	setenv("bootdelay", "0");
	378	else if (!keys)
	379	setenv("bootdelay", "0");
	380	else
	381	setenv("bootdelay", "2");
	382
	383	/* get the ethernet MAC from I2C EEPROM */
	384	mac_read_from_eeprom();
	385
	386	return 0;
	387	}
	388
	389	/* setup specific IO pad configuration */
	390	static iopin_t ioregs_init[] = {
	391	{ /* LPC CS3 */
	392	offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
	393	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
	394	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
	395	},
	396	{ /* LPC CS1 */
	397	offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
	398	IO_PIN_OVER_DRVSTR,
	399	IO_PIN_DS(2),
	400	},
	401	{ /* LPC CS2 */
	402	offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
	403	IO_PIN_OVER_DRVSTR,
	404	IO_PIN_DS(2),
	405	},
	406	{ /* LPC CS4, CS5 */
	407	offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
	408	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
	409	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
	410	},
	411	{ /* SDHC CLK, CMD, D0, D1, D2, D3 */
	412	offsetof(struct ioctrl512x, io_control_pata_ior), 6,
	413	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
	414	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
	415	},
	416	{ /* GPIO keyboard */
	417	offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
	418	IO_PIN_OVER_FMUX,
	419	IO_PIN_FMUX(3),
	420	},
	421	{ /* GPIO DN1 PF, LCD power, DN2 PF */
	422	offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
	423	IO_PIN_OVER_FMUX,
	424	IO_PIN_FMUX(3),
	425	},
	426	{ /* GPIO reset AS-i */
	427	offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
	428	IO_PIN_OVER_FMUX,
	429	IO_PIN_FMUX(3),
	430	},
	431	{ /* GPIO reset safety */
	432	offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
433	IO_PIN_OVER_FMUX,
434	IO_PIN_FMUX(3),
435	},
436	{ /* GPIO reset netX */
437	offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
438	IO_PIN_OVER_FMUX,
439	IO_PIN_FMUX(3),
440	},
441	{ /* GPIO ma2 en */
442	offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
443	IO_PIN_OVER_FMUX,
444	IO_PIN_FMUX(3),
445	},
446	{ /* GPIO SD CD, SD WP */
447	offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
448	IO_PIN_OVER_FMUX,
449	IO_PIN_FMUX(3),
450	},
451	{ /* FEC RX DV */
452	offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
453	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
454	IO_PIN_FMUX(2) \| IO_PIN_DS(2),
455	},
456	{ /* GPIO AS-i prog, AS-i done, LCD backlight */
457	offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
458	IO_PIN_OVER_FMUX,
459	IO_PIN_FMUX(3),
460	},
461	{ /* GPIO AS-i wdg */
462	offsetof(struct ioctrl512x, io_control_pci_req2), 1,
463	IO_PIN_OVER_FMUX,
464	IO_PIN_FMUX(3),
465	},
466	{ /* GPIO safety wdg */
467	offsetof(struct ioctrl512x, io_control_pci_req1), 1,
468	IO_PIN_OVER_FMUX,
469	IO_PIN_FMUX(3),
470	},
471	{ /* GPIO netX wdg */
472	offsetof(struct ioctrl512x, io_control_pci_req0), 1,
473	IO_PIN_OVER_FMUX,
474	IO_PIN_FMUX(3),
475	},
476	{ /* GPIO IRQ powerfail */
477	offsetof(struct ioctrl512x, io_control_pci_inta), 1,
478	IO_PIN_OVER_FMUX,
479	IO_PIN_FMUX(3),
480	},
481	{ /* GPIO AS-i PWRD */
482	offsetof(struct ioctrl512x, io_control_pci_frame), 1,
483	IO_PIN_OVER_FMUX,
484	IO_PIN_FMUX(3),
485	},
486	{ /* GPIO LED0, LED1 */
487	offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
488	IO_PIN_OVER_FMUX,
489	IO_PIN_FMUX(3),
490	},
491	{ /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
492	offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
493	IO_PIN_OVER_FMUX,
494	IO_PIN_FMUX(3),
495	},
496	{ /* DIU clk */
497	offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
498	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
499	IO_PIN_FMUX(2) \| IO_PIN_DS(2),
500	},
501	{ /* FEC TX ER, CRS */
502	offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
503	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
504	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
505	},
506	{ /* GPIO/GPT / / to NOT have the EXT IRQ0 float */
507	offsetof(struct ioctrl512x, io_control_irq0), 1,
508	IO_PIN_OVER_FMUX,
509	IO_PIN_FMUX(3),
510	},
511	{ /*
512	* FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
513	* rdx 3-0, mdio, rx clk
514	*/
515	offsetof(struct ioctrl512x, io_control_psc0_0), 15,
516	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
517	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
518	},
519	/* optional: make sure PSC3 remains the serial console */
520	{ /* LPC CS6 */
521	offsetof(struct ioctrl512x, io_control_psc3_4), 1,
522	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
523	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
524	},
525	/* make sure PSC4 remains available for SPI,
526	BUT PSC4_1 is a GPIO kind of SS! */
527	{ /* enforce drive strength on the SPI pin */
528	offsetof(struct ioctrl512x, io_control_psc4_0), 5,
529	IO_PIN_OVER_DRVSTR,
530	IO_PIN_DS(2),
531	},
532	{
533	offsetof(struct ioctrl512x, io_control_psc4_1), 1,
534	IO_PIN_OVER_FMUX,
535	IO_PIN_FMUX(3),
536	},
537	/* optional: make sure PSC5 remains available for SPI */
538	{ /* enforce drive strength on the SPI pin */
539	offsetof(struct ioctrl512x, io_control_psc5_0), 5,
540	IO_PIN_OVER_DRVSTR,
541	IO_PIN_DS(1),
542	},
543	{ /* LPC TSIZ1 */
544	offsetof(struct ioctrl512x, io_control_psc6_0), 1,
545	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
546	IO_PIN_FMUX(1) \| IO_PIN_DS(2),
547	},
548	{ /* DIU hsync */
549	offsetof(struct ioctrl512x, io_control_psc6_1), 1,
550	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
551	IO_PIN_FMUX(2) \| IO_PIN_DS(1),
552	},
553	{ /* DIU vsync */
554	offsetof(struct ioctrl512x, io_control_psc6_4), 1,
555	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
556	IO_PIN_FMUX(2) \| IO_PIN_DS(1),
557	},
558	{ /* PSC7, part of DIU RGB */
559	offsetof(struct ioctrl512x, io_control_psc7_0), 2,
560	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
561	IO_PIN_FMUX(2) \| IO_PIN_DS(1),
562	},
563	{ /* PSC7, safety UART */
564	offsetof(struct ioctrl512x, io_control_psc7_2), 2,
565	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
566	IO_PIN_FMUX(0) \| IO_PIN_DS(1),
567	},
568	{ /* DIU (part of) RGB[] */
569	offsetof(struct ioctrl512x, io_control_psc8_3), 16,
570	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
571	IO_PIN_FMUX(2) \| IO_PIN_DS(1),
572	},
573	{ /* DIU data enable */
574	offsetof(struct ioctrl512x, io_control_psc11_4), 1,
575	IO_PIN_OVER_FMUX \| IO_PIN_OVER_DRVSTR,
576	IO_PIN_FMUX(2) \| IO_PIN_DS(1),
577	},
578	/* reduce LPB drive strength for improved EMI */
579	{ /* LPC OE, LPC RW */
580	offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
581	IO_PIN_OVER_DRVSTR,
582	IO_PIN_DS(2),
583	},
584	{ /* LPC AX03 through LPC AD00 */
585	offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
586	IO_PIN_OVER_DRVSTR,
587	IO_PIN_DS(2),
588	},
589	{ /* LPC CS5 */
590	offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
591	IO_PIN_OVER_DRVSTR,
592	IO_PIN_DS(2),
593	},
594	{ /* SDHC CLK */
595	offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
596	IO_PIN_OVER_DRVSTR,
597	IO_PIN_DS(2),
598	},
599	{ /* SDHC DATA */
600	offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
601	IO_PIN_OVER_DRVSTR,
602	IO_PIN_DS(2),
603	},
604	};
605
606	int checkboard(void)
607	{
608	puts("Board: ifm AC14xx\n");
609
610	/* initialize function mux & slew rate IO inter alia on IO Pins */
611	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
612
613	return 0;
614	}
615
616	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
617	void ft_board_setup(void blob, bd_t bd)
618	{
619	ft_cpu_setup(blob, bd);
620	}
621	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */