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Commit | Line | Data |
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18a00dfd | 1 | /* |
f905432c | 2 | * Voipac PXA270 Support |
18a00dfd | 3 | * |
f905432c | 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
18a00dfd MV |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <common.h> | |
23 | #include <asm/arch/hardware.h> | |
5d877f42 | 24 | #include <asm/arch/regs-mmc.h> |
4438a45f | 25 | #include <asm/arch/pxa.h> |
c7e61334 | 26 | #include <netdev.h> |
3ba8bf7c MV |
27 | #include <serial.h> |
28 | #include <asm/io.h> | |
18a00dfd MV |
29 | |
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
18a00dfd MV |
32 | /* |
33 | * Miscelaneous platform dependent initialisations | |
34 | */ | |
f905432c | 35 | int board_init(void) |
18a00dfd | 36 | { |
720a650c MV |
37 | /* We have RAM, disable cache */ |
38 | dcache_disable(); | |
39 | icache_disable(); | |
40 | ||
18a00dfd MV |
41 | /* memory and cpu-speed are setup before relocation */ |
42 | /* so we do _nothing_ here */ | |
43 | ||
f905432c | 44 | /* Arch number of vpac270 */ |
18a00dfd MV |
45 | gd->bd->bi_arch_number = MACH_TYPE_VPAC270; |
46 | ||
47 | /* adress of boot parameters */ | |
48 | gd->bd->bi_boot_params = 0xa0000100; | |
49 | ||
50 | return 0; | |
51 | } | |
52 | ||
f905432c | 53 | int dram_init(void) |
6ef6eb91 | 54 | { |
411b9eaf | 55 | #ifndef CONFIG_ONENAND |
f68d2a22 | 56 | pxa2xx_dram_init(); |
411b9eaf | 57 | #endif |
6ef6eb91 | 58 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
6ef6eb91 MV |
59 | return 0; |
60 | } | |
61 | ||
62 | void dram_init_banksize(void) | |
f905432c MV |
63 | { |
64 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
18a00dfd | 65 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
18a00dfd | 66 | |
f97e9c65 | 67 | #ifdef CONFIG_RAM_256M |
f905432c MV |
68 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
69 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; | |
70 | #endif | |
18a00dfd MV |
71 | } |
72 | ||
5d877f42 MV |
73 | #ifdef CONFIG_CMD_MMC |
74 | int board_mmc_init(bd_t *bis) | |
75 | { | |
76 | pxa_mmc_register(0); | |
77 | return 0; | |
78 | } | |
79 | #endif | |
80 | ||
f905432c | 81 | #ifdef CONFIG_CMD_USB |
18a00dfd MV |
82 | int usb_board_init(void) |
83 | { | |
3ba8bf7c MV |
84 | writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
85 | ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), | |
86 | UHCHR); | |
18a00dfd | 87 | |
3ba8bf7c | 88 | writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); |
18a00dfd | 89 | |
3ba8bf7c MV |
90 | while (readl(UHCHR) & UHCHR_FSBIR) |
91 | ; | |
18a00dfd | 92 | |
3ba8bf7c MV |
93 | writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); |
94 | writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); | |
18a00dfd MV |
95 | |
96 | /* Clear any OTG Pin Hold */ | |
3ba8bf7c MV |
97 | if (readl(PSSR) & PSSR_OTGPH) |
98 | writel(readl(PSSR) | PSSR_OTGPH, PSSR); | |
18a00dfd | 99 | |
3ba8bf7c MV |
100 | writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); |
101 | writel(readl(UHCRHDA) | 0x100, UHCRHDA); | |
18a00dfd MV |
102 | |
103 | /* Set port power control mask bits, only 3 ports. */ | |
3ba8bf7c | 104 | writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); |
18a00dfd MV |
105 | |
106 | /* enable port 2 */ | |
3ba8bf7c MV |
107 | writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | |
108 | UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); | |
18a00dfd MV |
109 | |
110 | return 0; | |
111 | } | |
112 | ||
113 | void usb_board_init_fail(void) | |
114 | { | |
115 | return; | |
116 | } | |
117 | ||
118 | void usb_board_stop(void) | |
119 | { | |
3ba8bf7c | 120 | writel(readl(UHCHR) | UHCHR_FHR, UHCHR); |
18a00dfd | 121 | udelay(11); |
3ba8bf7c | 122 | writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); |
18a00dfd | 123 | |
3ba8bf7c | 124 | writel(readl(UHCCOMS) | 1, UHCCOMS); |
18a00dfd MV |
125 | udelay(10); |
126 | ||
3ba8bf7c | 127 | writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); |
18a00dfd MV |
128 | |
129 | return; | |
130 | } | |
f905432c | 131 | #endif |
18a00dfd MV |
132 | |
133 | #ifdef CONFIG_DRIVER_DM9000 | |
134 | int board_eth_init(bd_t *bis) | |
135 | { | |
136 | return dm9000_initialize(bis); | |
137 | } | |
138 | #endif |