projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a111bfbf | 1 | /* |
| 4e3d8406 MY |
2 | * Copyright (C) 2016 Socionext Inc. |
| 3 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| a111bfbf MY |
4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | */ | |
| 7 | ||
| 8 | #include <common.h> | |
| 9 | #include <clk.h> | |
| 10 | #include <fdtdec.h> | |
| a111bfbf | 11 | #include <mmc.h> |
| 9d922450 | 12 | #include <dm.h> |
| a111bfbf | 13 | #include <linux/compat.h> |
| b27af399 | 14 | #include <linux/dma-direction.h> |
| a111bfbf | 15 | #include <linux/io.h> |
| 4f80501b | 16 | #include <linux/sizes.h> |
| a111bfbf | 17 | #include <asm/unaligned.h> |
| a111bfbf MY |
18 | |
| 19 | DECLARE_GLOBAL_DATA_PTR; | |
| 20 | ||
| 21 | #define UNIPHIER_SD_CMD 0x000 /* command */ | |
| 22 | #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ | |
| 23 | #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ | |
| 24 | #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ | |
| 25 | #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ | |
| 26 | #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ | |
| 27 | #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ | |
| 28 | #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ | |
| 29 | #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ | |
| 30 | #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ | |
| 31 | #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ | |
| 32 | #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ | |
| 33 | #define UNIPHIER_SD_ARG 0x008 /* command argument */ | |
| 34 | #define UNIPHIER_SD_STOP 0x010 /* stop action control */ | |
| 35 | #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ | |
| 36 | #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ | |
| 37 | #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ | |
| 38 | #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ | |
| 39 | #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ | |
| 40 | #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ | |
| 41 | #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ | |
| 42 | #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ | |
| 43 | #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ | |
| 44 | #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ | |
| 45 | #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ | |
| 46 | #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ | |
| 47 | #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ | |
| 48 | #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ | |
| 49 | #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ | |
| 50 | #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ | |
| 51 | #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ | |
| 52 | #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ | |
| 53 | #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ | |
| 54 | #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ | |
| 55 | #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ | |
| 56 | #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ | |
| 57 | #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ | |
| 58 | #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ | |
| 59 | #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ | |
| 60 | #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ | |
| 61 | #define UNIPHIER_SD_INFO1_MASK 0x040 | |
| 62 | #define UNIPHIER_SD_INFO2_MASK 0x044 | |
| 63 | #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ | |
| 64 | #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff | |
| 65 | #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ | |
| 66 | #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ | |
| 67 | #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ | |
| 68 | #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ | |
| 69 | #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ | |
| 70 | #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ | |
| 71 | #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ | |
| 72 | #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ | |
| 73 | #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ | |
| 74 | #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ | |
| 75 | #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ | |
| 76 | #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ | |
| 77 | #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ | |
| 78 | #define UNIPHIER_SD_SIZE 0x04c /* block size */ | |
| 79 | #define UNIPHIER_SD_OPTION 0x050 | |
| 80 | #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) | |
| 81 | #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) | |
| 82 | #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) | |
| 83 | #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) | |
| 84 | #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ | |
| 85 | #define UNIPHIER_SD_EXTMODE 0x1b0 | |
| 86 | #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ | |
| 87 | #define UNIPHIER_SD_SOFT_RST 0x1c0 | |
| 88 | #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ | |
| 89 | #define UNIPHIER_SD_VERSION 0x1c4 /* version register */ | |
| 90 | #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ | |
| 91 | #define UNIPHIER_SD_HOST_MODE 0x1c8 | |
| 92 | #define UNIPHIER_SD_IF_MODE 0x1cc | |
| 93 | #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ | |
| 94 | #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ | |
| 95 | #define UNIPHIER_SD_VOLT_MASK (3 << 0) | |
| 96 | #define UNIPHIER_SD_VOLT_OFF (0 << 0) | |
| 97 | #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ | |
| 98 | #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ | |
| 99 | #define UNIPHIER_SD_DMA_MODE 0x410 | |
| 100 | #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ | |
| 101 | #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ | |
| 102 | #define UNIPHIER_SD_DMA_CTL 0x414 | |
| 103 | #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ | |
| 104 | #define UNIPHIER_SD_DMA_RST 0x418 | |
| 105 | #define UNIPHIER_SD_DMA_RST_RD BIT(9) | |
| 106 | #define UNIPHIER_SD_DMA_RST_WR BIT(8) | |
| 107 | #define UNIPHIER_SD_DMA_INFO1 0x420 | |
| 108 | #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ | |
| 109 | #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ | |
| 110 | #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ | |
| 111 | #define UNIPHIER_SD_DMA_INFO1_MASK 0x424 | |
| 112 | #define UNIPHIER_SD_DMA_INFO2 0x428 | |
| 113 | #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) | |
| 114 | #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) | |
| 115 | #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c | |
| 116 | #define UNIPHIER_SD_DMA_ADDR_L 0x440 | |
| 117 | #define UNIPHIER_SD_DMA_ADDR_H 0x444 | |
| 118 | ||
| 119 | /* alignment required by the DMA engine of this controller */ | |
| 120 | #define UNIPHIER_SD_DMA_MINALIGN 0x10 | |
| 121 | ||
| 14f47234 | 122 | struct uniphier_sd_plat { |
| a111bfbf | 123 | struct mmc_config cfg; |
| 14f47234 MY |
124 | struct mmc mmc; |
| 125 | }; | |
| 126 | ||
| 127 | struct uniphier_sd_priv { | |
| a111bfbf MY |
128 | void __iomem *regbase; |
| 129 | unsigned long mclk; | |
| 130 | unsigned int version; | |
| 131 | u32 caps; | |
| 132 | #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ | |
| 133 | #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ | |
| 134 | #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ | |
| 1c99f68e | 135 | #define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ |
| a111bfbf MY |
136 | }; |
| 137 | ||
| 484d9db4 MV |
138 | static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, const u32 reg) |
| 139 | { | |
| 140 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) | |
| 141 | return readq(priv->regbase + (reg << 1)); | |
| 142 | else | |
| 143 | return readq(priv->regbase + reg); | |
| 144 | } | |
| 145 | ||
| 146 | static void uniphier_sd_writeq(struct uniphier_sd_priv *priv, | |
| 147 | const u64 val, const u32 reg) | |
| 148 | { | |
| 149 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) | |
| 150 | writeq(val, priv->regbase + (reg << 1)); | |
| 151 | else | |
| 152 | writeq(val, priv->regbase + reg); | |
| 153 | } | |
| 154 | ||
| 3d7b1d1b MV |
155 | static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg) |
| 156 | { | |
| 1c99f68e MV |
157 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) |
| 158 | return readl(priv->regbase + (reg << 1)); | |
| 159 | else | |
| 160 | return readl(priv->regbase + reg); | |
| 3d7b1d1b MV |
161 | } |
| 162 | ||
| 163 | static void uniphier_sd_writel(struct uniphier_sd_priv *priv, | |
| 164 | const u32 val, const u32 reg) | |
| 165 | { | |
| 1c99f68e MV |
166 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) |
| 167 | writel(val, priv->regbase + (reg << 1)); | |
| 168 | else | |
| 169 | writel(val, priv->regbase + reg); | |
| 3d7b1d1b MV |
170 | } |
| 171 | ||
| a111bfbf MY |
172 | static dma_addr_t __dma_map_single(void *ptr, size_t size, |
| 173 | enum dma_data_direction dir) | |
| 174 | { | |
| 175 | unsigned long addr = (unsigned long)ptr; | |
| 176 | ||
| 177 | if (dir == DMA_FROM_DEVICE) | |
| 178 | invalidate_dcache_range(addr, addr + size); | |
| 179 | else | |
| 180 | flush_dcache_range(addr, addr + size); | |
| 181 | ||
| 182 | return addr; | |
| 183 | } | |
| 184 | ||
| 185 | static void __dma_unmap_single(dma_addr_t addr, size_t size, | |
| 186 | enum dma_data_direction dir) | |
| 187 | { | |
| 188 | if (dir != DMA_TO_DEVICE) | |
| 189 | invalidate_dcache_range(addr, addr + size); | |
| 190 | } | |
| 191 | ||
| 3937404f | 192 | static int uniphier_sd_check_error(struct udevice *dev) |
| a111bfbf | 193 | { |
| 3937404f | 194 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| 3d7b1d1b | 195 | u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2); |
| a111bfbf MY |
196 | |
| 197 | if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { | |
| 198 | /* | |
| 199 | * TIMEOUT must be returned for unsupported command. Do not | |
| 200 | * display error log since this might be a part of sequence to | |
| 201 | * distinguish between SD and MMC. | |
| 202 | */ | |
| 915ffa52 | 203 | return -ETIMEDOUT; |
| a111bfbf MY |
204 | } |
| 205 | ||
| 206 | if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { | |
| 3937404f | 207 | dev_err(dev, "timeout error\n"); |
| a111bfbf MY |
208 | return -ETIMEDOUT; |
| 209 | } | |
| 210 | ||
| 211 | if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | | |
| 212 | UNIPHIER_SD_INFO2_ERR_IDX)) { | |
| 3937404f | 213 | dev_err(dev, "communication out of sync\n"); |
| a111bfbf MY |
214 | return -EILSEQ; |
| 215 | } | |
| 216 | ||
| 217 | if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | | |
| 218 | UNIPHIER_SD_INFO2_ERR_ILW)) { | |
| 3937404f | 219 | dev_err(dev, "illegal access\n"); |
| a111bfbf MY |
220 | return -EIO; |
| 221 | } | |
| 222 | ||
| 223 | return 0; | |
| 224 | } | |
| 225 | ||
| 3937404f MY |
226 | static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, |
| 227 | u32 flag) | |
| a111bfbf | 228 | { |
| 3937404f | 229 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| a111bfbf MY |
230 | long wait = 1000000; |
| 231 | int ret; | |
| 232 | ||
| 3d7b1d1b | 233 | while (!(uniphier_sd_readl(priv, reg) & flag)) { |
| a111bfbf | 234 | if (wait-- < 0) { |
| 3937404f | 235 | dev_err(dev, "timeout\n"); |
| a111bfbf MY |
236 | return -ETIMEDOUT; |
| 237 | } | |
| 238 | ||
| 3937404f | 239 | ret = uniphier_sd_check_error(dev); |
| a111bfbf MY |
240 | if (ret) |
| 241 | return ret; | |
| 242 | ||
| 243 | udelay(1); | |
| 244 | } | |
| 245 | ||
| 246 | return 0; | |
| 247 | } | |
| 248 | ||
| 3937404f | 249 | static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf, |
| a111bfbf MY |
250 | uint blocksize) |
| 251 | { | |
| 3937404f | 252 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| a111bfbf MY |
253 | int i, ret; |
| 254 | ||
| 255 | /* wait until the buffer is filled with data */ | |
| 3937404f | 256 | ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, |
| a111bfbf MY |
257 | UNIPHIER_SD_INFO2_BRE); |
| 258 | if (ret) | |
| 259 | return ret; | |
| 260 | ||
| 261 | /* | |
| 262 | * Clear the status flag _before_ read the buffer out because | |
| 263 | * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. | |
| 264 | */ | |
| 3d7b1d1b | 265 | uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); |
| a111bfbf MY |
266 | |
| 267 | if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { | |
| 484d9db4 MV |
268 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) { |
| 269 | for (i = 0; i < blocksize / 8; i++) { | |
| 270 | u64 data; | |
| 271 | data = uniphier_sd_readq(priv, | |
| 272 | UNIPHIER_SD_BUF); | |
| 273 | *(*pbuf)++ = data; | |
| 274 | *(*pbuf)++ = data >> 32; | |
| 275 | } | |
| 276 | } else { | |
| 277 | for (i = 0; i < blocksize / 4; i++) { | |
| 278 | u32 data; | |
| 279 | data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); | |
| 280 | *(*pbuf)++ = data; | |
| 281 | } | |
| 282 | } | |
| a111bfbf | 283 | } else { |
| 484d9db4 MV |
284 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) { |
| 285 | for (i = 0; i < blocksize / 8; i++) { | |
| 286 | u64 data; | |
| 287 | data = uniphier_sd_readq(priv, | |
| 288 | UNIPHIER_SD_BUF); | |
| 289 | put_unaligned(data, (*pbuf)++); | |
| 290 | put_unaligned(data >> 32, (*pbuf)++); | |
| 291 | } | |
| 292 | } else { | |
| 293 | for (i = 0; i < blocksize / 4; i++) { | |
| 294 | u32 data; | |
| 295 | data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); | |
| 296 | put_unaligned(data, (*pbuf)++); | |
| 297 | } | |
| 298 | } | |
| a111bfbf MY |
299 | } |
| 300 | ||
| 301 | return 0; | |
| 302 | } | |
| 303 | ||
| 3937404f MY |
304 | static int uniphier_sd_pio_write_one_block(struct udevice *dev, |
| 305 | const u32 **pbuf, uint blocksize) | |
| a111bfbf | 306 | { |
| 3937404f | 307 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| a111bfbf MY |
308 | int i, ret; |
| 309 | ||
| 310 | /* wait until the buffer becomes empty */ | |
| 3937404f | 311 | ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, |
| a111bfbf MY |
312 | UNIPHIER_SD_INFO2_BWE); |
| 313 | if (ret) | |
| 314 | return ret; | |
| 315 | ||
| 3d7b1d1b | 316 | uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); |
| a111bfbf MY |
317 | |
| 318 | if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { | |
| 484d9db4 MV |
319 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) { |
| 320 | for (i = 0; i < blocksize / 8; i++) { | |
| 321 | u64 data = *(*pbuf)++; | |
| 322 | data |= (u64)*(*pbuf)++ << 32; | |
| 323 | uniphier_sd_writeq(priv, data, | |
| 324 | UNIPHIER_SD_BUF); | |
| 325 | } | |
| 326 | } else { | |
| 327 | for (i = 0; i < blocksize / 4; i++) { | |
| 328 | uniphier_sd_writel(priv, *(*pbuf)++, | |
| 329 | UNIPHIER_SD_BUF); | |
| 330 | } | |
| 331 | } | |
| a111bfbf | 332 | } else { |
| 484d9db4 MV |
333 | if (priv->caps & UNIPHIER_SD_CAP_64BIT) { |
| 334 | for (i = 0; i < blocksize / 8; i++) { | |
| 335 | u64 data = get_unaligned((*pbuf)++); | |
| 336 | data |= (u64)get_unaligned((*pbuf)++) << 32; | |
| 337 | uniphier_sd_writeq(priv, data, | |
| 338 | UNIPHIER_SD_BUF); | |
| 339 | } | |
| 340 | } else { | |
| 341 | for (i = 0; i < blocksize / 4; i++) { | |
| 342 | u32 data = get_unaligned((*pbuf)++); | |
| 343 | uniphier_sd_writel(priv, data, | |
| 344 | UNIPHIER_SD_BUF); | |
| 345 | } | |
| 346 | } | |
| a111bfbf MY |
347 | } |
| 348 | ||
| 349 | return 0; | |
| 350 | } | |
| 351 | ||
| 3937404f | 352 | static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) |
| a111bfbf MY |
353 | { |
| 354 | u32 *dest = (u32 *)data->dest; | |
| 355 | const u32 *src = (const u32 *)data->src; | |
| 356 | int i, ret; | |
| 357 | ||
| 358 | for (i = 0; i < data->blocks; i++) { | |
| 359 | if (data->flags & MMC_DATA_READ) | |
| 3937404f | 360 | ret = uniphier_sd_pio_read_one_block(dev, &dest, |
| a111bfbf MY |
361 | data->blocksize); |
| 362 | else | |
| 3937404f | 363 | ret = uniphier_sd_pio_write_one_block(dev, &src, |
| a111bfbf MY |
364 | data->blocksize); |
| 365 | if (ret) | |
| 366 | return ret; | |
| 367 | } | |
| 368 | ||
| 369 | return 0; | |
| 370 | } | |
| 371 | ||
| 372 | static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, | |
| 373 | dma_addr_t dma_addr) | |
| 374 | { | |
| 375 | u32 tmp; | |
| 376 | ||
| 3d7b1d1b MV |
377 | uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1); |
| 378 | uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2); | |
| a111bfbf MY |
379 | |
| 380 | /* enable DMA */ | |
| 3d7b1d1b | 381 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); |
| a111bfbf | 382 | tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; |
| 3d7b1d1b | 383 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); |
| a111bfbf | 384 | |
| 3d7b1d1b | 385 | uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L); |
| a111bfbf MY |
386 | |
| 387 | /* suppress the warning "right shift count >= width of type" */ | |
| 388 | dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); | |
| 389 | ||
| 3d7b1d1b | 390 | uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H); |
| a111bfbf | 391 | |
| 3d7b1d1b | 392 | uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL); |
| a111bfbf MY |
393 | } |
| 394 | ||
| 3937404f | 395 | static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, |
| a111bfbf MY |
396 | unsigned int blocks) |
| 397 | { | |
| 3937404f | 398 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| a111bfbf MY |
399 | long wait = 1000000 + 10 * blocks; |
| 400 | ||
| 3d7b1d1b | 401 | while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) { |
| a111bfbf | 402 | if (wait-- < 0) { |
| 3937404f | 403 | dev_err(dev, "timeout during DMA\n"); |
| a111bfbf MY |
404 | return -ETIMEDOUT; |
| 405 | } | |
| 406 | ||
| 407 | udelay(10); | |
| 408 | } | |
| 409 | ||
| 3d7b1d1b | 410 | if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) { |
| 3937404f | 411 | dev_err(dev, "error during DMA\n"); |
| a111bfbf MY |
412 | return -EIO; |
| 413 | } | |
| 414 | ||
| 415 | return 0; | |
| 416 | } | |
| 417 | ||
| 3937404f | 418 | static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) |
| a111bfbf | 419 | { |
| 3937404f | 420 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| a111bfbf MY |
421 | size_t len = data->blocks * data->blocksize; |
| 422 | void *buf; | |
| 423 | enum dma_data_direction dir; | |
| 424 | dma_addr_t dma_addr; | |
| 425 | u32 poll_flag, tmp; | |
| 426 | int ret; | |
| 427 | ||
| 3d7b1d1b | 428 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); |
| a111bfbf MY |
429 | |
| 430 | if (data->flags & MMC_DATA_READ) { | |
| 431 | buf = data->dest; | |
| 432 | dir = DMA_FROM_DEVICE; | |
| 433 | poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; | |
| 434 | tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; | |
| 435 | } else { | |
| 436 | buf = (void *)data->src; | |
| 437 | dir = DMA_TO_DEVICE; | |
| 438 | poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; | |
| 439 | tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; | |
| 440 | } | |
| 441 | ||
| 3d7b1d1b | 442 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); |
| a111bfbf MY |
443 | |
| 444 | dma_addr = __dma_map_single(buf, len, dir); | |
| 445 | ||
| 446 | uniphier_sd_dma_start(priv, dma_addr); | |
| 447 | ||
| 3937404f | 448 | ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); |
| a111bfbf MY |
449 | |
| 450 | __dma_unmap_single(dma_addr, len, dir); | |
| 451 | ||
| 452 | return ret; | |
| 453 | } | |
| 454 | ||
| 455 | /* check if the address is DMA'able */ | |
| 456 | static bool uniphier_sd_addr_is_dmaable(unsigned long addr) | |
| 457 | { | |
| 458 | if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) | |
| 459 | return false; | |
| 460 | ||
| 461 | #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ | |
| 462 | defined(CONFIG_SPL_BUILD) | |
| 463 | /* | |
| 464 | * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways | |
| 465 | * of L2, which is unreachable from the DMA engine. | |
| 466 | */ | |
| 467 | if (addr < CONFIG_SPL_STACK) | |
| 468 | return false; | |
| 469 | #endif | |
| 470 | ||
| 471 | return true; | |
| 472 | } | |
| 473 | ||
| 3937404f | 474 | static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| a111bfbf MY |
475 | struct mmc_data *data) |
| 476 | { | |
| 3937404f | 477 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| a111bfbf MY |
478 | int ret; |
| 479 | u32 tmp; | |
| 480 | ||
| 3d7b1d1b | 481 | if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { |
| 3937404f | 482 | dev_err(dev, "command busy\n"); |
| a111bfbf MY |
483 | return -EBUSY; |
| 484 | } | |
| 485 | ||
| 486 | /* clear all status flags */ | |
| 3d7b1d1b MV |
487 | uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1); |
| 488 | uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); | |
| a111bfbf MY |
489 | |
| 490 | /* disable DMA once */ | |
| 3d7b1d1b | 491 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); |
| a111bfbf | 492 | tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; |
| 3d7b1d1b | 493 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); |
| a111bfbf | 494 | |
| 3d7b1d1b | 495 | uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG); |
| a111bfbf MY |
496 | |
| 497 | tmp = cmd->cmdidx; | |
| 498 | ||
| 499 | if (data) { | |
| 3d7b1d1b MV |
500 | uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE); |
| 501 | uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT); | |
| a111bfbf MY |
502 | |
| 503 | /* Do not send CMD12 automatically */ | |
| 504 | tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; | |
| 505 | ||
| 506 | if (data->blocks > 1) | |
| 507 | tmp |= UNIPHIER_SD_CMD_MULTI; | |
| 508 | ||
| 509 | if (data->flags & MMC_DATA_READ) | |
| 510 | tmp |= UNIPHIER_SD_CMD_RD; | |
| 511 | } | |
| 512 | ||
| 513 | /* | |
| 514 | * Do not use the response type auto-detection on this hardware. | |
| 515 | * CMD8, for example, has different response types on SD and eMMC, | |
| 516 | * while this controller always assumes the response type for SD. | |
| 517 | * Set the response type manually. | |
| 518 | */ | |
| 519 | switch (cmd->resp_type) { | |
| 520 | case MMC_RSP_NONE: | |
| 521 | tmp |= UNIPHIER_SD_CMD_RSP_NONE; | |
| 522 | break; | |
| 523 | case MMC_RSP_R1: | |
| 524 | tmp |= UNIPHIER_SD_CMD_RSP_R1; | |
| 525 | break; | |
| 526 | case MMC_RSP_R1b: | |
| 527 | tmp |= UNIPHIER_SD_CMD_RSP_R1B; | |
| 528 | break; | |
| 529 | case MMC_RSP_R2: | |
| 530 | tmp |= UNIPHIER_SD_CMD_RSP_R2; | |
| 531 | break; | |
| 532 | case MMC_RSP_R3: | |
| 533 | tmp |= UNIPHIER_SD_CMD_RSP_R3; | |
| 534 | break; | |
| 535 | default: | |
| 3937404f | 536 | dev_err(dev, "unknown response type\n"); |
| a111bfbf MY |
537 | return -EINVAL; |
| 538 | } | |
| 539 | ||
| 3937404f | 540 | dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", |
| a111bfbf | 541 | cmd->cmdidx, tmp, cmd->cmdarg); |
| 3d7b1d1b | 542 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD); |
| a111bfbf | 543 | |
| 3937404f | 544 | ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, |
| a111bfbf MY |
545 | UNIPHIER_SD_INFO1_RSP); |
| 546 | if (ret) | |
| 547 | return ret; | |
| 548 | ||
| 549 | if (cmd->resp_type & MMC_RSP_136) { | |
| 3d7b1d1b MV |
550 | u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76); |
| 551 | u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54); | |
| 552 | u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32); | |
| 553 | u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); | |
| a111bfbf | 554 | |
| ac5efc35 MV |
555 | cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | |
| 556 | ((rsp_103_72 & 0xff000000) >> 24); | |
| 557 | cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | | |
| 558 | ((rsp_71_40 & 0xff000000) >> 24); | |
| 559 | cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | | |
| 560 | ((rsp_39_8 & 0xff000000) >> 24); | |
| 561 | cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; | |
| a111bfbf MY |
562 | } else { |
| 563 | /* bit 39-8 */ | |
| 3d7b1d1b | 564 | cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); |
| a111bfbf MY |
565 | } |
| 566 | ||
| 567 | if (data) { | |
| 568 | /* use DMA if the HW supports it and the buffer is aligned */ | |
| 569 | if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && | |
| 570 | uniphier_sd_addr_is_dmaable((long)data->src)) | |
| 3937404f | 571 | ret = uniphier_sd_dma_xfer(dev, data); |
| a111bfbf | 572 | else |
| 3937404f | 573 | ret = uniphier_sd_pio_xfer(dev, data); |
| a111bfbf | 574 | |
| 3937404f | 575 | ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, |
| a111bfbf MY |
576 | UNIPHIER_SD_INFO1_CMP); |
| 577 | if (ret) | |
| 578 | return ret; | |
| 579 | } | |
| 580 | ||
| 581 | return ret; | |
| 582 | } | |
| 583 | ||
| 8be12e28 MY |
584 | static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, |
| 585 | struct mmc *mmc) | |
| a111bfbf MY |
586 | { |
| 587 | u32 val, tmp; | |
| 588 | ||
| 589 | switch (mmc->bus_width) { | |
| 590 | case 1: | |
| 591 | val = UNIPHIER_SD_OPTION_WIDTH_1; | |
| 592 | break; | |
| 593 | case 4: | |
| 594 | val = UNIPHIER_SD_OPTION_WIDTH_4; | |
| 595 | break; | |
| 596 | case 8: | |
| 597 | val = UNIPHIER_SD_OPTION_WIDTH_8; | |
| 598 | break; | |
| 599 | default: | |
| 8be12e28 | 600 | return -EINVAL; |
| a111bfbf MY |
601 | } |
| 602 | ||
| 3d7b1d1b | 603 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION); |
| a111bfbf MY |
604 | tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; |
| 605 | tmp |= val; | |
| 3d7b1d1b | 606 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION); |
| 8be12e28 MY |
607 | |
| 608 | return 0; | |
| a111bfbf MY |
609 | } |
| 610 | ||
| 611 | static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, | |
| 612 | struct mmc *mmc) | |
| 613 | { | |
| 614 | u32 tmp; | |
| 615 | ||
| 3d7b1d1b | 616 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE); |
| a111bfbf MY |
617 | if (mmc->ddr_mode) |
| 618 | tmp |= UNIPHIER_SD_IF_MODE_DDR; | |
| 619 | else | |
| 620 | tmp &= ~UNIPHIER_SD_IF_MODE_DDR; | |
| 3d7b1d1b | 621 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE); |
| a111bfbf MY |
622 | } |
| 623 | ||
| 624 | static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, | |
| 625 | struct mmc *mmc) | |
| 626 | { | |
| 627 | unsigned int divisor; | |
| 628 | u32 val, tmp; | |
| 629 | ||
| 630 | if (!mmc->clock) | |
| 631 | return; | |
| 632 | ||
| 633 | divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); | |
| 634 | ||
| 635 | if (divisor <= 1) | |
| 636 | val = UNIPHIER_SD_CLKCTL_DIV1; | |
| 637 | else if (divisor <= 2) | |
| 638 | val = UNIPHIER_SD_CLKCTL_DIV2; | |
| 639 | else if (divisor <= 4) | |
| 640 | val = UNIPHIER_SD_CLKCTL_DIV4; | |
| 641 | else if (divisor <= 8) | |
| 642 | val = UNIPHIER_SD_CLKCTL_DIV8; | |
| 643 | else if (divisor <= 16) | |
| 644 | val = UNIPHIER_SD_CLKCTL_DIV16; | |
| 645 | else if (divisor <= 32) | |
| 646 | val = UNIPHIER_SD_CLKCTL_DIV32; | |
| 647 | else if (divisor <= 64) | |
| 648 | val = UNIPHIER_SD_CLKCTL_DIV64; | |
| 649 | else if (divisor <= 128) | |
| 650 | val = UNIPHIER_SD_CLKCTL_DIV128; | |
| 651 | else if (divisor <= 256) | |
| 652 | val = UNIPHIER_SD_CLKCTL_DIV256; | |
| 653 | else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) | |
| 654 | val = UNIPHIER_SD_CLKCTL_DIV512; | |
| 655 | else | |
| 656 | val = UNIPHIER_SD_CLKCTL_DIV1024; | |
| 657 | ||
| 3d7b1d1b | 658 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL); |
| 4a89a24e MY |
659 | if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && |
| 660 | (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) | |
| 661 | return; | |
| a111bfbf MY |
662 | |
| 663 | /* stop the clock before changing its rate to avoid a glitch signal */ | |
| 664 | tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; | |
| 3d7b1d1b | 665 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); |
| a111bfbf MY |
666 | |
| 667 | tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; | |
| 668 | tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; | |
| 3d7b1d1b | 669 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); |
| a111bfbf MY |
670 | |
| 671 | tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; | |
| 3d7b1d1b | 672 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); |
| 4a89a24e MY |
673 | |
| 674 | udelay(1000); | |
| a111bfbf MY |
675 | } |
| 676 | ||
| 3937404f | 677 | static int uniphier_sd_set_ios(struct udevice *dev) |
| a111bfbf | 678 | { |
| 3937404f MY |
679 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| 680 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
| 8be12e28 | 681 | int ret; |
| a111bfbf | 682 | |
| 3937404f | 683 | dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", |
| a111bfbf MY |
684 | mmc->clock, mmc->ddr_mode, mmc->bus_width); |
| 685 | ||
| 8be12e28 MY |
686 | ret = uniphier_sd_set_bus_width(priv, mmc); |
| 687 | if (ret) | |
| 688 | return ret; | |
| a111bfbf MY |
689 | uniphier_sd_set_ddr_mode(priv, mmc); |
| 690 | uniphier_sd_set_clk_rate(priv, mmc); | |
| 691 | ||
| 3937404f | 692 | return 0; |
| a111bfbf MY |
693 | } |
| 694 | ||
| 4eb00846 MY |
695 | static int uniphier_sd_get_cd(struct udevice *dev) |
| 696 | { | |
| 697 | struct uniphier_sd_priv *priv = dev_get_priv(dev); | |
| 698 | ||
| 699 | if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) | |
| 700 | return 1; | |
| 701 | ||
| 3d7b1d1b | 702 | return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) & |
| 4eb00846 MY |
703 | UNIPHIER_SD_INFO1_CD); |
| 704 | } | |
| 705 | ||
| 706 | static const struct dm_mmc_ops uniphier_sd_ops = { | |
| 707 | .send_cmd = uniphier_sd_send_cmd, | |
| 708 | .set_ios = uniphier_sd_set_ios, | |
| 709 | .get_cd = uniphier_sd_get_cd, | |
| 710 | }; | |
| 711 | ||
| 712 | static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) | |
| a111bfbf | 713 | { |
| a111bfbf MY |
714 | u32 tmp; |
| 715 | ||
| 716 | /* soft reset of the host */ | |
| 3d7b1d1b | 717 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST); |
| a111bfbf | 718 | tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; |
| 3d7b1d1b | 719 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); |
| a111bfbf | 720 | tmp |= UNIPHIER_SD_SOFT_RST_RSTX; |
| 3d7b1d1b | 721 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); |
| a111bfbf MY |
722 | |
| 723 | /* FIXME: implement eMMC hw_reset */ | |
| 724 | ||
| 3d7b1d1b | 725 | uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP); |
| a111bfbf MY |
726 | |
| 727 | /* | |
| 728 | * Connected to 32bit AXI. | |
| 729 | * This register dropped backward compatibility at version 0x10. | |
| 730 | * Write an appropriate value depending on the IP version. | |
| 731 | */ | |
| 3d7b1d1b MV |
732 | uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000, |
| 733 | UNIPHIER_SD_HOST_MODE); | |
| a111bfbf MY |
734 | |
| 735 | if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { | |
| 3d7b1d1b | 736 | tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); |
| a111bfbf | 737 | tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; |
| 3d7b1d1b | 738 | uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); |
| a111bfbf | 739 | } |
| a111bfbf MY |
740 | } |
| 741 | ||
| 14f47234 MY |
742 | static int uniphier_sd_bind(struct udevice *dev) |
| 743 | { | |
| 744 | struct uniphier_sd_plat *plat = dev_get_platdata(dev); | |
| 745 | ||
| 746 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
| 747 | } | |
| 748 | ||
| 4a70d262 | 749 | static int uniphier_sd_probe(struct udevice *dev) |
| a111bfbf | 750 | { |
| 14f47234 | 751 | struct uniphier_sd_plat *plat = dev_get_platdata(dev); |
| a111bfbf MY |
752 | struct uniphier_sd_priv *priv = dev_get_priv(dev); |
| 753 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
| 4b26d5e3 | 754 | const u32 quirks = dev_get_driver_data(dev); |
| a111bfbf | 755 | fdt_addr_t base; |
| 135aa950 | 756 | struct clk clk; |
| a111bfbf MY |
757 | int ret; |
| 758 | ||
| a821c4af | 759 | base = devfdt_get_addr(dev); |
| 4f80501b MY |
760 | if (base == FDT_ADDR_T_NONE) |
| 761 | return -EINVAL; | |
| 762 | ||
| 4e3d8406 | 763 | priv->regbase = devm_ioremap(dev, base, SZ_2K); |
| a111bfbf MY |
764 | if (!priv->regbase) |
| 765 | return -ENOMEM; | |
| 766 | ||
| 135aa950 SW |
767 | ret = clk_get_by_index(dev, 0, &clk); |
| 768 | if (ret < 0) { | |
| a111bfbf | 769 | dev_err(dev, "failed to get host clock\n"); |
| 135aa950 | 770 | return ret; |
| a111bfbf MY |
771 | } |
| 772 | ||
| 773 | /* set to max rate */ | |
| 135aa950 | 774 | priv->mclk = clk_set_rate(&clk, ULONG_MAX); |
| a111bfbf MY |
775 | if (IS_ERR_VALUE(priv->mclk)) { |
| 776 | dev_err(dev, "failed to set rate for host clock\n"); | |
| 135aa950 | 777 | clk_free(&clk); |
| a111bfbf MY |
778 | return priv->mclk; |
| 779 | } | |
| 780 | ||
| 135aa950 SW |
781 | ret = clk_enable(&clk); |
| 782 | clk_free(&clk); | |
| a111bfbf MY |
783 | if (ret) { |
| 784 | dev_err(dev, "failed to enable host clock\n"); | |
| 785 | return ret; | |
| 786 | } | |
| 787 | ||
| 14f47234 MY |
788 | plat->cfg.name = dev->name; |
| 789 | plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; | |
| a111bfbf | 790 | |
| e160f7d4 SG |
791 | switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", |
| 792 | 1)) { | |
| a111bfbf | 793 | case 8: |
| 14f47234 | 794 | plat->cfg.host_caps |= MMC_MODE_8BIT; |
| a111bfbf MY |
795 | break; |
| 796 | case 4: | |
| 14f47234 | 797 | plat->cfg.host_caps |= MMC_MODE_4BIT; |
| a111bfbf MY |
798 | break; |
| 799 | case 1: | |
| 800 | break; | |
| 801 | default: | |
| 802 | dev_err(dev, "Invalid \"bus-width\" value\n"); | |
| 803 | return -EINVAL; | |
| 804 | } | |
| 805 | ||
| 4b26d5e3 MV |
806 | if (quirks) { |
| 807 | priv->caps = quirks; | |
| 808 | } else { | |
| 809 | priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) & | |
| 810 | UNIPHIER_SD_VERSION_IP; | |
| 811 | dev_dbg(dev, "version %x\n", priv->version); | |
| 812 | if (priv->version >= 0x10) { | |
| 813 | priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; | |
| 814 | priv->caps |= UNIPHIER_SD_CAP_DIV1024; | |
| 815 | } | |
| 816 | } | |
| 817 | ||
| e160f7d4 | 818 | if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", |
| a111bfbf MY |
819 | NULL)) |
| 820 | priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; | |
| 821 | ||
| 4eb00846 | 822 | uniphier_sd_host_init(priv); |
| 3937404f | 823 | |
| 14f47234 MY |
824 | plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; |
| 825 | plat->cfg.f_min = priv->mclk / | |
| a111bfbf | 826 | (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); |
| 14f47234 MY |
827 | plat->cfg.f_max = priv->mclk; |
| 828 | plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ | |
| a111bfbf | 829 | |
| 14f47234 | 830 | upriv->mmc = &plat->mmc; |
| a111bfbf MY |
831 | |
| 832 | return 0; | |
| 833 | } | |
| 834 | ||
| 835 | static const struct udevice_id uniphier_sd_match[] = { | |
| 4b26d5e3 | 836 | { .compatible = "socionext,uniphier-sdhc", .data = 0 }, |
| a111bfbf MY |
837 | { /* sentinel */ } |
| 838 | }; | |
| 839 | ||
| 840 | U_BOOT_DRIVER(uniphier_mmc) = { | |
| 841 | .name = "uniphier-mmc", | |
| 842 | .id = UCLASS_MMC, | |
| 843 | .of_match = uniphier_sd_match, | |
| 14f47234 | 844 | .bind = uniphier_sd_bind, |
| a111bfbf | 845 | .probe = uniphier_sd_probe, |
| a111bfbf | 846 | .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), |
| 14f47234 | 847 | .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat), |
| 3937404f | 848 | .ops = &uniphier_sd_ops, |
| a111bfbf | 849 | }; |