arch/arm/cpu/arm1136/mx31/generic.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <div64.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/sys_proto.h>
  30
  31 static u32 mx31_decode_pll(u32 reg, u32 infreq)
  32 {
  33         u32 mfi = GET_PLL_MFI(reg);
  34         s32 mfn = GET_PLL_MFN(reg);
  35         u32 mfd = GET_PLL_MFD(reg);
  36         u32 pd =  GET_PLL_PD(reg);
  37
  38         mfi = mfi <= 5 ? 5 : mfi;
  39         mfn = mfn >= 512 ? mfn - 1024 : mfn;
  40         mfd += 1;
  41         pd += 1;
  42
  43         return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  44                 mfd * pd);
  45 }
  46
  47 static u32 mx31_get_mpl_dpdgck_clk(void)
  48 {
  49         u32 infreq;
  50
  51         if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
  52                 infreq = MXC_CLK32 * 1024;
  53         else
  54                 infreq = MXC_HCLK;
  55
  56         return mx31_decode_pll(readl(CCM_MPCTL), infreq);
  57 }
  58
  59 static u32 mx31_get_mcu_main_clk(void)
  60 {
  61         /* For now we assume mpl_dpdgck_clk == mcu_main_clk
  62          * which should be correct for most boards
  63          */
  64         return mx31_get_mpl_dpdgck_clk();
  65 }
  66
  67 static u32 mx31_get_ipg_clk(void)
  68 {
  69         u32 freq = mx31_get_mcu_main_clk();
  70         u32 pdr0 = readl(CCM_PDR0);
  71
  72         freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
  73         freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
  74
  75         return freq;
  76 }
  77
  78 /* hsp is the clock for the ipu */
  79 static u32 mx31_get_hsp_clk(void)
  80 {
  81         u32 freq = mx31_get_mcu_main_clk();
  82         u32 pdr0 = readl(CCM_PDR0);
  83
  84         freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
  85
  86         return freq;
  87 }
  88
  89 void mx31_dump_clocks(void)
  90 {
  91         u32 cpufreq = mx31_get_mcu_main_clk();
  92         printf("mx31 cpu clock: %dMHz\n", cpufreq / 1000000);
  93         printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
  94         printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
  95 }
  96
  97 unsigned int mxc_get_clock(enum mxc_clock clk)
  98 {
  99         switch (clk) {
 100         case MXC_ARM_CLK:
 101                 return mx31_get_mcu_main_clk();
 102         case MXC_IPG_CLK:
 103         case MXC_IPG_PERCLK:
 104         case MXC_CSPI_CLK:
 105         case MXC_UART_CLK:
 106         case MXC_ESDHC_CLK:
 107         case MXC_I2C_CLK:
 108                 return mx31_get_ipg_clk();
 109         case MXC_IPU_CLK:
 110                 return mx31_get_hsp_clk();
 111         }
 112         return -1;
 113 }
 114
 115 u32 imx_get_uartclk(void)
 116 {
 117         return mxc_get_clock(MXC_UART_CLK);
 118 }
 119
 120 void mx31_gpio_mux(unsigned long mode)
 121 {
 122         unsigned long reg, shift, tmp;
 123
 124         reg = IOMUXC_BASE + (mode & 0x1fc);
 125         shift = (~mode & 0x3) * 8;
 126
 127         tmp = readl(reg);
 128         tmp &= ~(0xff << shift);
 129         tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
 130         writel(tmp, reg);
 131 }
 132
 133 void mx31_set_pad(enum iomux_pins pin, u32 config)
 134 {
 135         u32 field, l, reg;
 136
 137         pin &= IOMUX_PADNUM_MASK;
 138         reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
 139         field = (pin + 2) % 3;
 140
 141         l = readl(reg);
 142         l &= ~(0x1ff << (field * 10));
 143         l |= config << (field * 10);
 144         writel(l, reg);
 145
 146 }
 147
 148 void mx31_set_gpr(enum iomux_gp_func gp, char en)
 149 {
 150         u32 l;
 151         struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE;
 152
 153         l = readl(&iomuxc->gpr);
 154         if (en)
 155                 l |= gp;
 156         else
 157                 l &= ~gp;
 158
 159         writel(l, &iomuxc->gpr);
 160 }
 161
 162 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
 163 {
 164         struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
 165         struct mx31_weim_cscr *cscr = &weim->cscr[cs];
 166
 167         writel(weimcs->upper, &cscr->upper);
 168         writel(weimcs->lower, &cscr->lower);
 169         writel(weimcs->additional, &cscr->additional);
 170 }
 171
 172 struct mx3_cpu_type mx31_cpu_type[] = {
 173         { .srev = 0x00, .v = 0x10 },
 174         { .srev = 0x10, .v = 0x11 },
 175         { .srev = 0x11, .v = 0x11 },
 176         { .srev = 0x12, .v = 0x1F },
 177         { .srev = 0x13, .v = 0x1F },
 178         { .srev = 0x14, .v = 0x12 },
 179         { .srev = 0x15, .v = 0x12 },
 180         { .srev = 0x28, .v = 0x20 },
 181         { .srev = 0x29, .v = 0x20 },
 182 };
 183
 184 u32 get_cpu_rev(void)
 185 {
 186         u32 i, srev;
 187
 188         /* read SREV register from IIM module */
 189         struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
 190         srev = readl(&iim->iim_srev);
 191
 192         for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
 193                 if (srev == mx31_cpu_type[i].srev)
 194                         return mx31_cpu_type[i].v;
 195
 196         return srev | 0x8000;
 197 }
 198
 199 static char *get_reset_cause(void)
 200 {
 201         /* read RCSR register from CCM module */
 202         struct clock_control_regs *ccm =
 203                 (struct clock_control_regs *)CCM_BASE;
 204
 205         u32 cause = readl(&ccm->rcsr) & 0x07;
 206
 207         switch (cause) {
 208         case 0x0000:
 209                 return "POR";
 210         case 0x0001:
 211                 return "RST";
 212         case 0x0002:
 213                 return "WDOG";
 214         case 0x0006:
 215                 return "JTAG";
 216         case 0x0007:
 217                 return "ARM11P power gating";
 218         default:
 219                 return "unknown reset";
 220         }
 221 }
 222
 223 #if defined(CONFIG_DISPLAY_CPUINFO)
 224 int print_cpuinfo(void)
 225 {
 226         u32 srev = get_cpu_rev();
 227
 228         printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
 229                         (srev & 0xF0) >> 4, (srev & 0x0F),
 230                         ((srev & 0x8000) ? " unknown" : ""),
 231                         mx31_get_mcu_main_clk() / 1000000);
 232         printf("Reset cause: %s\n", get_reset_cause());
 233         return 0;
 234 }
 235 #endif