arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c

   1 /*
   2  * SoC-specific lowlevel code for DA850
   3  *
   4  * Copyright (C) 2011
   5  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24 #include <common.h>
  25 #include <nand.h>
  26 #include <ns16550.h>
  27 #include <post.h>
  28 #include <asm/arch/da850_lowlevel.h>
  29 #include <asm/arch/hardware.h>
  30 #include <asm/arch/davinci_misc.h>
  31 #include <asm/arch/ddr2_defs.h>
  32 #include <asm/arch/emif_defs.h>
  33 #include <asm/arch/pll_defs.h>
  34
  35 void davinci_enable_uart0(void)
  36 {
  37         lpsc_on(DAVINCI_LPSC_UART0);
  38
  39         /* Bringup UART0 out of reset */
  40         REG(UART0_PWREMU_MGMT) = 0x00006001;
  41 }
  42
  43 #if defined(CONFIG_SYS_DA850_PLL_INIT)
  44 void da850_waitloop(unsigned long loopcnt)
  45 {
  46         unsigned long   i;
  47
  48         for (i = 0; i < loopcnt; i++)
  49                 asm("   NOP");
  50 }
  51
  52 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
  53 {
  54         if (reg == davinci_pllc0_regs)
  55                 /* Unlock PLL registers. */
  56                 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
  57
  58         /*
  59          * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
  60          * through MMR
  61          */
  62         clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
  63         /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
  64         clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
  65
  66         /* Set PLLEN=0 => PLL BYPASS MODE */
  67         clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
  68
  69         da850_waitloop(150);
  70
  71         if (reg == davinci_pllc0_regs) {
  72                 /*
  73                  * Select the Clock Mode bit 8 as External Clock or On Chip
  74                  * Oscilator
  75                  */
  76                 dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
  77                 setbits_le32(&reg->pllctl,
  78                         (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
  79         }
  80
  81         /* Clear PLLRST bit to reset the PLL */
  82         clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
  83
  84         /* Disable the PLL output */
  85         setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  86
  87         /* PLL initialization sequence */
  88         /*
  89          * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
  90          * power down bit
  91          */
  92         clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
  93
  94         /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
  95         clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  96
  97 #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
  98         /* program the prediv */
  99         if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
 100                 writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
 101                         &reg->prediv);
 102 #endif
 103
 104         /* Program the required multiplier value in PLLM */
 105         writel(pllmult, &reg->pllm);
 106
 107         /* program the postdiv */
 108         if (reg == davinci_pllc0_regs)
 109                 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
 110                         &reg->postdiv);
 111         else
 112                 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
 113                         &reg->postdiv);
 114
 115         /*
 116          * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
 117          * no GO operation is currently in progress
 118          */
 119         while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
 120                 ;
 121
 122         if (reg == davinci_pllc0_regs) {
 123                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
 124                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
 125                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
 126                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
 127                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
 128                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
 129                 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
 130         } else {
 131                 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
 132                 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
 133                 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
 134         }
 135
 136         /*
 137          * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
 138          * transition.
 139          */
 140         setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
 141
 142         /*
 143          * Wait for the GOSTAT bit in PLLSTAT to clear to 0
 144          * (completion of phase alignment).
 145          */
 146         while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
 147                 ;
 148
 149         /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
 150         da850_waitloop(200);
 151
 152         /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
 153         setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
 154
 155         /* Wait for PLL to lock. See PLL spec for PLL lock time */
 156         da850_waitloop(2400);
 157
 158         /*
 159          * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
 160          * mode
 161          */
 162         setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
 163
 164
 165         /*
 166          * clear EMIFA and EMIFB clock source settings, let them
 167          * run off SYSCLK
 168          */
 169         if (reg == davinci_pllc0_regs)
 170                 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
 171                         ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
 172
 173         return 0;
 174 }
 175 #endif /* CONFIG_SYS_DA850_PLL_INIT */
 176
 177 #if defined(CONFIG_SYS_DA850_DDR_INIT)
 178 int da850_ddr_setup(void)
 179 {
 180         unsigned long   tmp;
 181
 182         /* Enable the Clock to DDR2/mDDR */
 183         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 184
 185         tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 186         if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
 187                 /* Begin VTP Calibration */
 188                 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
 189                 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
 190                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
 191                 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
 192                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
 193
 194                 /* Polling READY bit to see when VTP calibration is done */
 195                 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 196                 while ((tmp & VTP_READY) != VTP_READY)
 197                         tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 198
 199                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
 200                 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
 201         }
 202         setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
 203         writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
 204
 205         if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
 206                 /* DDR2 */
 207                 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
 208                         (1 << DDR_SLEW_DDR_PDENA_BIT) |
 209                         (1 << DDR_SLEW_CMOSEN_BIT));
 210         } else {
 211                 /* MOBILE DDR */
 212                 setbits_le32(&davinci_syscfg1_regs->ddr_slew,
 213                         (1 << DDR_SLEW_DDR_PDENA_BIT) |
 214                         (1 << DDR_SLEW_CMOSEN_BIT));
 215         }
 216
 217         /*
 218          * SDRAM Configuration Register (SDCR):
 219          * First set the BOOTUNLOCK bit to make configuration bits
 220          * writeable.
 221          */
 222         setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
 223
 224         /*
 225          * Write the new value of these bits and clear BOOTUNLOCK.
 226          * At the same time, set the TIMUNLOCK bit to allow changing
 227          * the timing registers
 228          */
 229         tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
 230         tmp &= ~DV_DDR_BOOTUNLOCK;
 231         tmp |= DV_DDR_TIMUNLOCK;
 232         writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 233
 234         /* write memory configuration and timing */
 235         if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
 236                 /* MOBILE DDR only*/
 237                 writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
 238                         &dv_ddr2_regs_ctrl->sdbcr2);
 239         }
 240         writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
 241         writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 242
 243         /* clear the TIMUNLOCK bit and write the value of the CL field */
 244         tmp &= ~DV_DDR_TIMUNLOCK;
 245         writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 246
 247         /*
 248          * LPMODEN and MCLKSTOPEN must be set!
 249          * Without this bits set, PSC don;t switch states !!
 250          */
 251         writel(CONFIG_SYS_DA850_DDR2_SDRCR |
 252                 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
 253                 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
 254                 &dv_ddr2_regs_ctrl->sdrcr);
 255
 256         /* SyncReset the Clock to EMIF3A SDRAM */
 257         lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
 258         /* Enable the Clock to EMIF3A SDRAM */
 259         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 260
 261         /* disable self refresh */
 262         clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
 263                 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
 264         writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 265
 266         return 0;
 267 }
 268 #endif /* CONFIG_SYS_DA850_DDR_INIT */
 269
 270 __attribute__((weak))
 271 void board_gpio_init(void)
 272 {
 273         return;
 274 }
 275
 276 int arch_cpu_init(void)
 277 {
 278         /* Unlock kick registers */
 279         writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
 280         writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
 281
 282         dv_maskbits(&davinci_syscfg_regs->suspsrc,
 283                 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
 284
 285         /* configure pinmux settings */
 286         if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
 287                 return 1;
 288
 289 #if defined(CONFIG_SYS_DA850_PLL_INIT)
 290         /* PLL setup */
 291         da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
 292         da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
 293 #endif
 294         /* setup CSn config */
 295 #if defined(CONFIG_SYS_DA850_CS2CFG)
 296         writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
 297 #endif
 298 #if defined(CONFIG_SYS_DA850_CS3CFG)
 299         writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 300 #endif
 301
 302         da8xx_configure_lpsc_items(lpsc, lpsc_size);
 303
 304         /* GPIO setup */
 305         board_gpio_init();
 306
 307
 308         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 309                         CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 310
 311         /*
 312          * Fix Power and Emulation Management Register
 313          * see sprufw3a.pdf page 37 Table 24
 314          */
 315         writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 316                 DAVINCI_UART_PWREMU_MGMT_UTRST),
 317                &davinci_uart2_ctrl_regs->pwremu_mgmt);
 318
 319 #if defined(CONFIG_SYS_DA850_DDR_INIT)
 320         da850_ddr_setup();
 321 #endif
 322
 323         return 0;
 324 }