arch/arm/cpu/armv7/at91/sama5d3_devices.c

   1 /*
   2  * Copyright (C) 2012-2013 Atmel Corporation
   3  * Bo Shen <voice.shen@atmel.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/arch/sama5d3.h>
  26 #include <asm/arch/at91_common.h>
  27 #include <asm/arch/at91_pmc.h>
  28 #include <asm/arch/clk.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/io.h>
  31
  32 unsigned int has_emac()
  33 {
  34         return cpu_is_sama5d31() || cpu_is_sama5d35();
  35 }
  36
  37 unsigned int has_gmac()
  38 {
  39         return !cpu_is_sama5d31();
  40 }
  41
  42 unsigned int has_lcdc()
  43 {
  44         return !cpu_is_sama5d35();
  45 }
  46
  47 char *get_cpu_name()
  48 {
  49         unsigned int extension_id = get_extension_chip_id();
  50
  51         if (cpu_is_sama5d3())
  52                 switch (extension_id) {
  53                 case ARCH_EXID_SAMA5D31:
  54                         return "SAMA5D31";
  55                 case ARCH_EXID_SAMA5D33:
  56                         return "SAMA5D33";
  57                 case ARCH_EXID_SAMA5D34:
  58                         return "SAMA5D34";
  59                 case ARCH_EXID_SAMA5D35:
  60                         return "SAMA5D35";
  61                 default:
  62                         return "Unknown CPU type";
  63                 }
  64         else
  65                 return "Unknown CPU type";
  66 }
  67
  68 void at91_serial0_hw_init(void)
  69 {
  70         at91_set_a_periph(AT91_PIO_PORTD, 18, 1);       /* TXD0 */
  71         at91_set_a_periph(AT91_PIO_PORTD, 17, 0);       /* RXD0 */
  72
  73         /* Enable clock */
  74         at91_periph_clk_enable(ATMEL_ID_USART0);
  75 }
  76
  77 void at91_serial1_hw_init(void)
  78 {
  79         at91_set_a_periph(AT91_PIO_PORTB, 29, 1);       /* TXD1 */
  80         at91_set_a_periph(AT91_PIO_PORTB, 28, 0);       /* RXD1 */
  81
  82         /* Enable clock */
  83         at91_periph_clk_enable(ATMEL_ID_USART1);
  84 }
  85
  86 void at91_serial2_hw_init(void)
  87 {
  88         at91_set_b_periph(AT91_PIO_PORTE, 26, 1);       /* TXD2 */
  89         at91_set_b_periph(AT91_PIO_PORTE, 25, 0);       /* RXD2 */
  90
  91         /* Enable clock */
  92         at91_periph_clk_enable(ATMEL_ID_USART2);
  93 }
  94
  95 void at91_seriald_hw_init(void)
  96 {
  97         at91_set_a_periph(AT91_PIO_PORTB, 31, 1);       /* DTXD */
  98         at91_set_a_periph(AT91_PIO_PORTB, 30, 0);       /* DRXD */
  99
 100         /* Enable clock */
 101         at91_periph_clk_enable(ATMEL_ID_SYS);
 102 }
 103
 104 #if defined(CONFIG_ATMEL_SPI)
 105 void at91_spi0_hw_init(unsigned long cs_mask)
 106 {
 107         at91_set_a_periph(AT91_PIO_PORTD, 10, 0);       /* SPI0_MISO */
 108         at91_set_a_periph(AT91_PIO_PORTD, 11, 0);       /* SPI0_MOSI */
 109         at91_set_a_periph(AT91_PIO_PORTD, 12, 0);       /* SPI0_SPCK */
 110
 111         if (cs_mask & (1 << 0))
 112                 at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
 113         if (cs_mask & (1 << 1))
 114                 at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
 115         if (cs_mask & (1 << 2))
 116                 at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
 117         if (cs_mask & (1 << 3))
 118                 at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
 119
 120         /* Enable clock */
 121         at91_periph_clk_enable(ATMEL_ID_SPI0);
 122 }
 123 #endif
 124
 125 #ifdef CONFIG_GENERIC_ATMEL_MCI
 126 void at91_mci_hw_init(void)
 127 {
 128         at91_set_a_periph(AT91_PIO_PORTD, 0, 0);        /* MCI0 CMD */
 129         at91_set_a_periph(AT91_PIO_PORTD, 1, 0);        /* MCI0 DA0 */
 130         at91_set_a_periph(AT91_PIO_PORTD, 2, 0);        /* MCI0 DA1 */
 131         at91_set_a_periph(AT91_PIO_PORTD, 3, 0);        /* MCI0 DA2 */
 132         at91_set_a_periph(AT91_PIO_PORTD, 4, 0);        /* MCI0 DA3 */
 133 #ifdef CONFIG_ATMEL_MCI_8BIT
 134         at91_set_a_periph(AT91_PIO_PORTD, 5, 0);        /* MCI0 DA4 */
 135         at91_set_a_periph(AT91_PIO_PORTD, 6, 0);        /* MCI0 DA5 */
 136         at91_set_a_periph(AT91_PIO_PORTD, 7, 0);        /* MCI0 DA6 */
 137         at91_set_a_periph(AT91_PIO_PORTD, 8, 0);        /* MCI0 DA7 */
 138 #endif
 139         at91_set_a_periph(AT91_PIO_PORTD, 9, 0);        /* MCI0 CLK */
 140
 141         /* Enable clock */
 142         at91_periph_clk_enable(ATMEL_ID_MCI0);
 143 }
 144 #endif
 145
 146 #ifdef CONFIG_MACB
 147 void at91_macb_hw_init(void)
 148 {
 149         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* ETXCK_EREFCK */
 150         at91_set_a_periph(AT91_PIO_PORTC, 5, 0);        /* ERXDV */
 151         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* ERX0 */
 152         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* ERX1 */
 153         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* ERXER */
 154         at91_set_a_periph(AT91_PIO_PORTC, 4, 0);        /* ETXEN */
 155         at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* ETX0 */
 156         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* ETX1 */
 157         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* EMDIO */
 158         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* EMDC */
 159
 160         /* Enable clock */
 161         at91_periph_clk_enable(ATMEL_ID_EMAC);
 162 }
 163 #endif
 164
 165 #ifdef CONFIG_LCD
 166 void at91_lcd_hw_init(void)
 167 {
 168         at91_set_a_periph(AT91_PIO_PORTA, 24, 0);       /* LCDPWM */
 169         at91_set_a_periph(AT91_PIO_PORTA, 25, 0);       /* LCDDISP */
 170         at91_set_a_periph(AT91_PIO_PORTA, 26, 0);       /* LCDVSYNC */
 171         at91_set_a_periph(AT91_PIO_PORTA, 27, 0);       /* LCDHSYNC */
 172         at91_set_a_periph(AT91_PIO_PORTA, 28, 0);       /* LCDDOTCK */
 173         at91_set_a_periph(AT91_PIO_PORTA, 29, 0);       /* LCDDEN */
 174
 175         /* The lower 16-bit of LCD only available on Port A */
 176         at91_set_a_periph(AT91_PIO_PORTA,  0, 0);       /* LCDD0 */
 177         at91_set_a_periph(AT91_PIO_PORTA,  1, 0);       /* LCDD1 */
 178         at91_set_a_periph(AT91_PIO_PORTA,  2, 0);       /* LCDD2 */
 179         at91_set_a_periph(AT91_PIO_PORTA,  3, 0);       /* LCDD3 */
 180         at91_set_a_periph(AT91_PIO_PORTA,  4, 0);       /* LCDD4 */
 181         at91_set_a_periph(AT91_PIO_PORTA,  5, 0);       /* LCDD5 */
 182         at91_set_a_periph(AT91_PIO_PORTA,  6, 0);       /* LCDD6 */
 183         at91_set_a_periph(AT91_PIO_PORTA,  7, 0);       /* LCDD7 */
 184         at91_set_a_periph(AT91_PIO_PORTA,  8, 0);       /* LCDD8 */
 185         at91_set_a_periph(AT91_PIO_PORTA,  9, 0);       /* LCDD9 */
 186         at91_set_a_periph(AT91_PIO_PORTA, 10, 0);       /* LCDD10 */
 187         at91_set_a_periph(AT91_PIO_PORTA, 11, 0);       /* LCDD11 */
 188         at91_set_a_periph(AT91_PIO_PORTA, 12, 0);       /* LCDD12 */
 189         at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* LCDD13 */
 190         at91_set_a_periph(AT91_PIO_PORTA, 14, 0);       /* LCDD14 */
 191         at91_set_a_periph(AT91_PIO_PORTA, 15, 0);       /* LCDD15 */
 192
 193         /* Enable clock */
 194         at91_periph_clk_enable(ATMEL_ID_LCDC);
 195 }
 196 #endif