arch/arm/cpu/armv7/mx6/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/errno.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <asm/imx-common/dma.h>
  18 #include <stdbool.h>
  19 #include <asm/arch/mxc_hdmi.h>
  20 #include <asm/arch/crm_regs.h>
  21
  22 struct scu_regs {
  23         u32     ctrl;
  24         u32     config;
  25         u32     status;
  26         u32     invalidate;
  27         u32     fpga_rev;
  28 };
  29
  30 u32 get_cpu_rev(void)
  31 {
  32         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  33         u32 reg = readl(&anatop->digprog_sololite);
  34         u32 type = ((reg >> 16) & 0xff);
  35
  36         if (type != MXC_CPU_MX6SL) {
  37                 reg = readl(&anatop->digprog);
  38                 type = ((reg >> 16) & 0xff);
  39                 if (type == MXC_CPU_MX6DL) {
  40                         struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  41                         u32 cfg = readl(&scu->config) & 3;
  42
  43                         if (!cfg)
  44                                 type = MXC_CPU_MX6SOLO;
  45                 }
  46         }
  47         reg &= 0xff;            /* mx6 silicon revision */
  48         return (type << 12) | (reg + 0x10);
  49 }
  50
  51 #ifdef CONFIG_REVISION_TAG
  52 u32 __weak get_board_rev(void)
  53 {
  54         u32 cpurev = get_cpu_rev();
  55         u32 type = ((cpurev >> 12) & 0xff);
  56         if (type == MXC_CPU_MX6SOLO)
  57                 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  58
  59         return cpurev;
  60 }
  61 #endif
  62
  63 void init_aips(void)
  64 {
  65         struct aipstz_regs *aips1, *aips2;
  66
  67         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  68         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  69
  70         /*
  71          * Set all MPROTx to be non-bufferable, trusted for R/W,
  72          * not forced to user-mode.
  73          */
  74         writel(0x77777777, &aips1->mprot0);
  75         writel(0x77777777, &aips1->mprot1);
  76         writel(0x77777777, &aips2->mprot0);
  77         writel(0x77777777, &aips2->mprot1);
  78
  79         /*
  80          * Set all OPACRx to be non-bufferable, not require
  81          * supervisor privilege level for access,allow for
  82          * write access and untrusted master access.
  83          */
  84         writel(0x00000000, &aips1->opacr0);
  85         writel(0x00000000, &aips1->opacr1);
  86         writel(0x00000000, &aips1->opacr2);
  87         writel(0x00000000, &aips1->opacr3);
  88         writel(0x00000000, &aips1->opacr4);
  89         writel(0x00000000, &aips2->opacr0);
  90         writel(0x00000000, &aips2->opacr1);
  91         writel(0x00000000, &aips2->opacr2);
  92         writel(0x00000000, &aips2->opacr3);
  93         writel(0x00000000, &aips2->opacr4);
  94 }
  95
  96 /*
  97  * Set the VDDSOC
  98  *
  99  * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
 100  * them to the specified millivolt level.
 101  * Possible values are from 0.725V to 1.450V in steps of
 102  * 0.025V (25mV).
 103  */
 104 void set_vddsoc(u32 mv)
 105 {
 106         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 107         u32 val, reg = readl(&anatop->reg_core);
 108
 109         if (mv < 725)
 110                 val = 0x00;     /* Power gated off */
 111         else if (mv > 1450)
 112                 val = 0x1F;     /* Power FET switched full on. No regulation */
 113         else
 114                 val = (mv - 700) / 25;
 115
 116         /*
 117          * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
 118          * and set them to the calculated value (0.7V + val * 0.25V)
 119          */
 120         reg = (reg & ~(0x1F << 18)) | (val << 18);
 121         writel(reg, &anatop->reg_core);
 122 }
 123
 124 static void imx_set_wdog_powerdown(bool enable)
 125 {
 126         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 127         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 128
 129         /* Write to the PDE (Power Down Enable) bit */
 130         writew(enable, &wdog1->wmcr);
 131         writew(enable, &wdog2->wmcr);
 132 }
 133
 134 int arch_cpu_init(void)
 135 {
 136         init_aips();
 137
 138         set_vddsoc(1200);       /* Set VDDSOC to 1.2V */
 139
 140         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
 141
 142 #ifdef CONFIG_APBH_DMA
 143         /* Start APBH DMA */
 144         mxs_dma_init();
 145 #endif
 146
 147         return 0;
 148 }
 149
 150 #ifndef CONFIG_SYS_DCACHE_OFF
 151 void enable_caches(void)
 152 {
 153         /* Enable D-cache. I-cache is already enabled in start.S */
 154         dcache_enable();
 155 }
 156 #endif
 157
 158 #if defined(CONFIG_FEC_MXC)
 159 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 160 {
 161         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 162         struct fuse_bank *bank = &ocotp->bank[4];
 163         struct fuse_bank4_regs *fuse =
 164                         (struct fuse_bank4_regs *)bank->fuse_regs;
 165
 166         u32 value = readl(&fuse->mac_addr_high);
 167         mac[0] = (value >> 8);
 168         mac[1] = value ;
 169
 170         value = readl(&fuse->mac_addr_low);
 171         mac[2] = value >> 24 ;
 172         mac[3] = value >> 16 ;
 173         mac[4] = value >> 8 ;
 174         mac[5] = value ;
 175
 176 }
 177 #endif
 178
 179 void boot_mode_apply(unsigned cfg_val)
 180 {
 181         unsigned reg;
 182         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 183         writel(cfg_val, &psrc->gpr9);
 184         reg = readl(&psrc->gpr10);
 185         if (cfg_val)
 186                 reg |= 1 << 28;
 187         else
 188                 reg &= ~(1 << 28);
 189         writel(reg, &psrc->gpr10);
 190 }
 191 /*
 192  * cfg_val will be used for
 193  * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 194  * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 195  * to SBMR1, which will determine the boot device.
 196  */
 197 const struct boot_mode soc_boot_modes[] = {
 198         {"normal",      MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 199         /* reserved value should start rom usb */
 200         {"usb",         MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 201         {"sata",        MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 202         {"escpi1:0",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
 203         {"escpi1:1",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
 204         {"escpi1:2",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
 205         {"escpi1:3",    MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
 206         /* 4 bit bus width */
 207         {"esdhc1",      MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 208         {"esdhc2",      MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 209         {"esdhc3",      MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 210         {"esdhc4",      MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 211         {NULL,          0},
 212 };
 213
 214 void s_init(void)
 215 {
 216 }
 217
 218 #ifdef CONFIG_IMX_HDMI
 219 void imx_enable_hdmi_phy(void)
 220 {
 221         struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 222         u8 reg;
 223         reg = readb(&hdmi->phy_conf0);
 224         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 225         writeb(reg, &hdmi->phy_conf0);
 226         udelay(3000);
 227         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 228         writeb(reg, &hdmi->phy_conf0);
 229         udelay(3000);
 230         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 231         writeb(reg, &hdmi->phy_conf0);
 232         writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
 233 }
 234
 235 void imx_setup_hdmi(void)
 236 {
 237         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 238         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 239         int reg;
 240
 241         /* Turn on HDMI PHY clock */
 242         reg = readl(&mxc_ccm->CCGR2);
 243         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
 244                  MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 245         writel(reg, &mxc_ccm->CCGR2);
 246         writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
 247         reg = readl(&mxc_ccm->chsccdr);
 248         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
 249                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
 250                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 251         reg |= (CHSCCDR_PODF_DIVIDE_BY_3
 252                  << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 253                  |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 254                  << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 255         writel(reg, &mxc_ccm->chsccdr);
 256 }
 257 #endif