arch/arm/cpu/armv8/Kconfig

   1 if ARM64
   2
   3 config ARMV8_MULTIENTRY
   4         bool "Enable multiple CPUs to enter into U-Boot"
   5
   6 config ARMV8_SET_SMPEN
   7         bool "Enable data coherency with other cores in cluster"
   8         help
   9           Say Y here if there is not any trust firmware to set
  10           CPUECTLR_EL1.SMPEN bit before U-Boot.
  11
  12           For A53, it enables data coherency with other cores in the
  13           cluster, and for A57/A72, it enables receiving of instruction
  14           cache and TLB maintenance operations.
  15           Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
  16           for single core systems. Unfortunately write access to this
  17           register may be controlled by EL3/EL2 firmware. To be more
  18           precise, by default (if there is EL2/EL3 firmware running)
  19           this register is RO for NS EL1.
  20           This switch can be used to avoid writing to CPUECTLR_EL1,
  21           it can be safely enabled when EL2/EL3 initialized SMPEN bit
  22           or when CPU implementation doesn't include that register.
  23
  24 config ARMV8_SPIN_TABLE
  25         bool "Support spin-table enable method"
  26         depends on ARMV8_MULTIENTRY && OF_LIBFDT
  27         help
  28           Say Y here to support "spin-table" enable method for booting Linux.
  29
  30           To use this feature, you must do:
  31             - Specify enable-method = "spin-table" in each CPU node in the
  32               Device Tree you are using to boot the kernel
  33             - Bring secondary CPUs into U-Boot proper in a board specific
  34               manner.  This must be done *after* relocation.  Otherwise, the
  35               secondary CPUs will spin in unprotected memory area because the
  36               master CPU protects the relocated spin code.
  37
  38           U-Boot automatically does:
  39             - Set "cpu-release-addr" property of each CPU node
  40               (overwrites it if already exists).
  41             - Reserve the code for the spin-table and the release address
  42               via a /memreserve/ region in the Device Tree.
  43
  44 menu "ARMv8 secure monitor firmware"
  45 config ARMV8_SEC_FIRMWARE_SUPPORT
  46         bool "Enable ARMv8 secure monitor firmware framework support"
  47         select OF_LIBFDT
  48         select FIT
  49         help
  50           This framework is aimed at making secure monitor firmware load
  51           process brief.
  52           Note: Only FIT format image is supported.
  53           You should prepare and provide the below information:
  54             - Address of secure firmware.
  55             - Address to hold the return address from secure firmware.
  56             - Secure firmware FIT image related information.
  57               Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
  58             - The target exception level that secure monitor firmware will
  59               return to.
  60
  61 config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  62         bool "Enable ARMv8 secure monitor firmware framework support for SPL"
  63         select SPL_OF_LIBFDT
  64         select SPL_FIT
  65         help
  66           Say Y here to support this framework in SPL phase.
  67
  68 config SEC_FIRMWARE_ARMV8_PSCI
  69         bool "PSCI implementation in secure monitor firmware"
  70         depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  71         help
  72           This config enables the ARMv8 PSCI implementation in secure monitor
  73           firmware. This is a private PSCI implementation and different from
  74           those implemented under the common ARMv8 PSCI framework.
  75
  76 config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
  77         bool "ARMv8 secure monitor firmware ERET address byteorder swap"
  78         depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
  79         help
  80           Say Y here when the endianness of the register or memory holding the
  81           Secure firmware exception return address is different with core's.
  82
  83 endmenu
  84
  85 config PSCI_RESET
  86         bool "Use PSCI for reset and shutdown"
  87         default y
  88         depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
  89                    !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
  90                    !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
  91                    !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
  92                    !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
  93                    !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
  94                    !TARGET_LS2081ARDB && \
  95                    !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
  96         help
  97           Most armv8 systems have PSCI support enabled in EL3, either through
  98           ARM Trusted Firmware or other firmware.
  99
 100           On these systems, we do not need to implement system reset manually,
 101           but can instead rely on higher level firmware to deal with it.
 102
 103           Select Y here to make use of PSCI calls for system reset
 104
 105 config ARMV8_PSCI
 106         bool "Enable PSCI support" if EXPERT
 107         default n
 108         help
 109           PSCI is Power State Coordination Interface defined by ARM.
 110           The PSCI in U-boot provides a general framework and each platform
 111           can implement their own specific PSCI functions.
 112           Say Y here to enable PSCI support on ARMv8 platform.
 113
 114 config ARMV8_PSCI_NR_CPUS
 115         int "Maximum supported CPUs for PSCI"
 116         depends on ARMV8_PSCI
 117         default 4
 118         help
 119           The maximum number of CPUs supported in the PSCI firmware.
 120           It is no problem to set a larger value than the number of CPUs in
 121           the actual hardware implementation.
 122
 123 config ARMV8_PSCI_CPUS_PER_CLUSTER
 124         int "Number of CPUs per cluster"
 125         depends on ARMV8_PSCI
 126         default 0
 127         help
 128           The number of CPUs per cluster, suppose each cluster has same number
 129           of CPU cores, platforms with asymmetric clusters don't apply here.
 130           A value 0 or no definition of it works for single cluster system.
 131           System with multi-cluster should difine their own exact value.
 132
 133 if SYS_HAS_ARMV8_SECURE_BASE
 134
 135 config ARMV8_SECURE_BASE
 136         hex "Secure address for PSCI image"
 137         depends on ARMV8_PSCI
 138         help
 139           Address for placing the PSCI text, data and stack sections.
 140           If not defined, the PSCI sections are placed together with the u-boot
 141           but platform can choose to place PSCI code image separately in other
 142           places such as some secure RAM built-in SOC etc.
 143
 144 endif
 145
 146 endif