arch/arm/dts/imx6qdl-icore.dtsi

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/input/input.h>
  45
  46 / {
  47         memory {
  48                 reg = <0x10000000 0x80000000>;
  49         };
  50
  51         reg_3p3v: regulator-3p3v {
  52                 compatible = "regulator-fixed";
  53                 regulator-name = "3P3V";
  54                 regulator-min-microvolt = <3300000>;
  55                 regulator-max-microvolt = <3300000>;
  56                 regulator-boot-on;
  57                 regulator-always-on;
  58         };
  59 };
  60
  61 &can1 {
  62         pinctrl-names = "default";
  63         pinctrl-0 = <&pinctrl_flexcan1>;
  64         xceiver-supply = <&reg_3p3v>;
  65 };
  66
  67 &can2 {
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&pinctrl_flexcan2>;
  70         xceiver-supply = <&reg_3p3v>;
  71 };
  72
  73 &clks {
  74         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
  75         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
  76 };
  77
  78 &fec {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_enet>;
  81         phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
  82         phy-mode = "rmii";
  83         status = "okay";
  84 };
  85
  86 &gpmi {
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&pinctrl_gpmi_nand>;
  89         nand-on-flash-bbt;
  90         status = "okay";
  91 };
  92
  93 &i2c1 {
  94         clock-frequency = <100000>;
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_i2c1>;
  97         status = "okay";
  98 };
  99
 100 &i2c2 {
 101         clock-frequency = <100000>;
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pinctrl_i2c2>;
 104         status = "okay";
 105 };
 106
 107 &i2c3 {
 108         clock-frequency = <100000>;
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_i2c3>;
 111         status = "okay";
 112 };
 113
 114 &uart4 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_uart4>;
 117         status = "okay";
 118 };
 119
 120 &usdhc1 {
 121         u-boot,dm-spl;
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pinctrl_usdhc1>;
 124         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 125         no-1-8-v;
 126         status = "okay";
 127 };
 128
 129 &iomuxc {
 130         pinctrl_enet: enetgrp {
 131                 fsl,pins = <
 132                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 133                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
 134                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 135                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 136                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 137                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 138                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 139                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 140                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 141                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 142                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 143                 >;
 144         };
 145
 146         pinctrl_flexcan1: flexcan1grp {
 147                 fsl,pins = <
 148                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
 149                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
 150                 >;
 151         };
 152
 153         pinctrl_flexcan2: flexcan2grp {
 154                 fsl,pins = <
 155                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
 156                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
 157                 >;
 158         };
 159
 160         pinctrl_gpmi_nand: gpmi-nand {
 161                 fsl,pins = <
 162                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 163                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 164                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 165                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 166                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 167                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 168                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 169                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 170                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 171                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 172                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 173                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 174                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 175                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 176                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 177                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 178                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 179                 >;
 180         };
 181
 182         pinctrl_i2c1: i2c1grp {
 183                 fsl,pins = <
 184                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 185                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 186                 >;
 187         };
 188
 189         pinctrl_i2c2: i2c2grp {
 190                 fsl,pins = <
 191                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 192                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 193                 >;
 194         };
 195
 196         pinctrl_i2c3: i2c3grp {
 197                 fsl,pins = <
 198                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 199                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 200                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 201                 >;
 202         };
 203
 204         pinctrl_uart4: uart4grp {
 205                 fsl,pins = <
 206                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 207                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 208                 >;
 209         };
 210
 211         pinctrl_usdhc1: usdhc1grp {
 212                 u-boot,dm-spl;
 213                 fsl,pins = <
 214                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 215                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
 216                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
 217                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
 218                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
 219                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 220                 >;
 221         };
 222 };