arch/arm/include/asm/arch-lpc32xx/clk.h

   1 /*
   2  * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _LPC32XX_CLK_H
   8 #define _LPC32XX_CLK_H
   9
  10 #include <asm/types.h>
  11
  12 #define OSC_CLK_FREQUENCY       13000000
  13 #define RTC_CLK_FREQUENCY       32768
  14
  15 /* Clocking and Power Control Registers */
  16 struct clk_pm_regs {
  17         u32 reserved0[5];
  18         u32 boot_map;           /* Boot Map Control Register            */
  19         u32 p0_intr_er;         /* Port 0/1 Start and Interrupt Enable  */
  20         u32 usbdiv_ctrl;        /* USB Clock Pre-Divide Register        */
  21         /* Internal Start Signal Sources Registers      */
  22         u32 start_er_int;       /* Start Enable Register                */
  23         u32 start_rsr_int;      /* Start Raw Status Register            */
  24         u32 start_sr_int;       /* Start Status Register                */
  25         u32 start_apr_int;      /* Start Activation Polarity Register   */
  26         /* Device Pin Start Signal Sources Registers    */
  27         u32 start_er_pin;       /* Start Enable Register                */
  28         u32 start_rsr_pin;      /* Start Raw Status Register            */
  29         u32 start_sr_pin;       /* Start Status Register                */
  30         u32 start_apr_pin;      /* Start Activation Polarity Register   */
  31         /* Clock Control Registers                      */
  32         u32 hclkdiv_ctrl;       /* HCLK Divider Control Register        */
  33         u32 pwr_ctrl;           /* Power Control Register               */
  34         u32 pll397_ctrl;        /* PLL397 Control Register              */
  35         u32 osc_ctrl;           /* Main Oscillator Control Register     */
  36         u32 sysclk_ctrl;        /* SYSCLK Control Register              */
  37         u32 lcdclk_ctrl;        /* LCD Clock Control Register           */
  38         u32 hclkpll_ctrl;       /* HCLK PLL Control Register            */
  39         u32 reserved1;
  40         u32 adclk_ctrl1;        /* ADC Clock Control1 Register          */
  41         u32 usb_ctrl;           /* USB Control Register                 */
  42         u32 sdramclk_ctrl;      /* SDRAM Clock Control Register         */
  43         u32 ddr_lap_nom;        /* DDR Calibration Nominal Value        */
  44         u32 ddr_lap_count;      /* DDR Calibration Measured Value       */
  45         u32 ddr_cal_delay;      /* DDR Calibration Delay Value          */
  46         u32 ssp_ctrl;           /* SSP Control Register                 */
  47         u32 i2s_ctrl;           /* I2S Clock Control Register           */
  48         u32 ms_ctrl;            /* Memory Card Control Register         */
  49         u32 reserved2[3];
  50         u32 macclk_ctrl;        /* Ethernet MAC Clock Control Register  */
  51         u32 reserved3[4];
  52         u32 test_clk;           /* Test Clock Selection Register        */
  53         u32 sw_int;             /* Software Interrupt Register          */
  54         u32 i2cclk_ctrl;        /* I2C Clock Control Register           */
  55         u32 keyclk_ctrl;        /* Keyboard Scan Clock Control Register */
  56         u32 adclk_ctrl;         /* ADC Clock Control Register           */
  57         u32 pwmclk_ctrl;        /* PWM Clock Control Register           */
  58         u32 timclk_ctrl;        /* Watchdog and Highspeed Timer Control */
  59         u32 timclk_ctrl1;       /* Motor and Timer Clock Control        */
  60         u32 spi_ctrl;           /* SPI Control Register                 */
  61         u32 flashclk_ctrl;      /* NAND Flash Clock Control Register    */
  62         u32 reserved4;
  63         u32 u3clk;              /* UART 3 Clock Control Register        */
  64         u32 u4clk;              /* UART 4 Clock Control Register        */
  65         u32 u5clk;              /* UART 5 Clock Control Register        */
  66         u32 u6clk;              /* UART 6 Clock Control Register        */
  67         u32 irdaclk;            /* IrDA Clock Control Register          */
  68         u32 uartclk_ctrl;       /* UART Clock Control Register          */
  69         u32 dmaclk_ctrl;        /* DMA Clock Control Register           */
  70         u32 autoclk_ctrl;       /* Autoclock Control Register           */
  71 };
  72
  73 /* HCLK Divider Control Register bits */
  74 #define CLK_HCLK_DDRAM_HALF             (0x2 << 7)
  75 #define CLK_HCLK_DDRAM_NOMINAL          (0x1 << 7)
  76 #define CLK_HCLK_DDRAM_STOPPED          (0x0 << 7)
  77 #define CLK_HCLK_PERIPH_DIV_MASK        (0x1F << 2)
  78 #define CLK_HCLK_PERIPH_DIV(n)          ((((n) - 1) & 0x1F) << 2)
  79 #define CLK_HCLK_ARM_PLL_DIV_MASK       (0x3 << 0)
  80 #define CLK_HCLK_ARM_PLL_DIV_4          (0x2 << 0)
  81 #define CLK_HCLK_ARM_PLL_DIV_2          (0x1 << 0)
  82 #define CLK_HCLK_ARM_PLL_DIV_1          (0x0 << 0)
  83
  84 /* Power Control Register bits */
  85 #define CLK_PWR_HCLK_RUN_PERIPH         (1 << 10)
  86 #define CLK_PWR_EMC_SREFREQ             (1 << 9)
  87 #define CLK_PWR_EMC_SREFREQ_UPDATE      (1 << 8)
  88 #define CLK_PWR_SDRAM_SREFREQ           (1 << 7)
  89 #define CLK_PWR_HIGHCORE_LEVEL          (1 << 5)
  90 #define CLK_PWR_SYSCLKEN_LEVEL          (1 << 4)
  91 #define CLK_PWR_SYSCLKEN_CTRL           (1 << 3)
  92 #define CLK_PWR_NORMAL_RUN              (1 << 2)
  93 #define CLK_PWR_HIGHCORE_CTRL           (1 << 1)
  94 #define CLK_PWR_STOP_MODE               (1 << 0)
  95
  96 /* SYSCLK Control Register bits */
  97 #define CLK_SYSCLK_PLL397               (1 << 1)
  98 #define CLK_SYSCLK_MUX                  (1 << 0)
  99
 100 /* HCLK PLL Control Register bits */
 101 #define CLK_HCLK_PLL_OPERATING          (1 << 16)
 102 #define CLK_HCLK_PLL_BYPASS             (1 << 15)
 103 #define CLK_HCLK_PLL_DIRECT             (1 << 14)
 104 #define CLK_HCLK_PLL_FEEDBACK           (1 << 13)
 105 #define CLK_HCLK_PLL_POSTDIV_MASK       (0x3 << 11)
 106 #define CLK_HCLK_PLL_POSTDIV_16         (0x3 << 11)
 107 #define CLK_HCLK_PLL_POSTDIV_8          (0x2 << 11)
 108 #define CLK_HCLK_PLL_POSTDIV_4          (0x1 << 11)
 109 #define CLK_HCLK_PLL_POSTDIV_2          (0x0 << 11)
 110 #define CLK_HCLK_PLL_PREDIV_MASK        (0x3 << 9)
 111 #define CLK_HCLK_PLL_PREDIV_4           (0x3 << 9)
 112 #define CLK_HCLK_PLL_PREDIV_3           (0x2 << 9)
 113 #define CLK_HCLK_PLL_PREDIV_2           (0x1 << 9)
 114 #define CLK_HCLK_PLL_PREDIV_1           (0x0 << 9)
 115 #define CLK_HCLK_PLL_FEEDBACK_DIV_MASK  (0xFF << 1)
 116 #define CLK_HCLK_PLL_FEEDBACK_DIV(n)    ((((n) - 1) & 0xFF) << 1)
 117 #define CLK_HCLK_PLL_LOCKED             (1 << 0)
 118
 119 /* Ethernet MAC Clock Control Register bits     */
 120 #define CLK_MAC_RMII                    (0x3 << 3)
 121 #define CLK_MAC_MII                     (0x1 << 3)
 122 #define CLK_MAC_MASTER                  (1 << 2)
 123 #define CLK_MAC_SLAVE                   (1 << 1)
 124 #define CLK_MAC_REG                     (1 << 0)
 125
 126 /* Timer Clock Control1 Register bits */
 127 #define CLK_TIMCLK_MOTOR                (1 << 6)
 128 #define CLK_TIMCLK_TIMER3               (1 << 5)
 129 #define CLK_TIMCLK_TIMER2               (1 << 4)
 130 #define CLK_TIMCLK_TIMER1               (1 << 3)
 131 #define CLK_TIMCLK_TIMER0               (1 << 2)
 132 #define CLK_TIMCLK_TIMER5               (1 << 1)
 133 #define CLK_TIMCLK_TIMER4               (1 << 0)
 134
 135 /* Timer Clock Control Register bits */
 136 #define CLK_TIMCLK_HSTIMER              (1 << 1)
 137 #define CLK_TIMCLK_WATCHDOG             (1 << 0)
 138
 139 /* UART Clock Control Register bits */
 140 #define CLK_UART(n)                     (1 << ((n) - 3))
 141
 142 /* UARTn Clock Select Registers bits */
 143 #define CLK_UART_HCLK                   (1 << 16)
 144 #define CLK_UART_X_DIV(n)               (((n) & 0xFF) << 8)
 145 #define CLK_UART_Y_DIV(n)               (((n) & 0xFF) << 0)
 146
 147 /* DMA Clock Control Register bits */
 148 #define CLK_DMA_ENABLE                  (1 << 0)
 149
 150 unsigned int get_sys_clk_rate(void);
 151 unsigned int get_hclk_pll_rate(void);
 152 unsigned int get_hclk_clk_div(void);
 153 unsigned int get_hclk_clk_rate(void);
 154 unsigned int get_periph_clk_div(void);
 155 unsigned int get_periph_clk_rate(void);
 156
 157 #endif /* _LPC32XX_CLK_H */