arch/arm/include/asm/arch-mx35/lowlevel_macro.S

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <asm/arch/imx-regs.h>
  23 #include <generated/asm-offsets.h>
  24 #include <asm/macro.h>
  25
  26 /*
  27  * AIPS setup - Only setup MPROTx registers.
  28  * The PACR default values are good.
  29  *
  30  * Default argument values:
  31  *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
  32  *    user-mode.
  33  *  - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
  34  *    SDMA to access them.
  35  */
  36 .macro init_aips mpr=0x77777777, opacr=0x00000000
  37         ldr     r0, =AIPS1_BASE_ADDR
  38         ldr     r1, =\mpr
  39         str     r1, [r0, #AIPS_MPR_0_7]
  40         str     r1, [r0, #AIPS_MPR_8_15]
  41         ldr     r2, =AIPS2_BASE_ADDR
  42         str     r1, [r2, #AIPS_MPR_0_7]
  43         str     r1, [r2, #AIPS_MPR_8_15]
  44
  45         /* Did not change the AIPS control registers access type. */
  46         ldr     r1, =\opacr
  47         str     r1, [r0, #AIPS_OPACR_0_7]
  48         str     r1, [r0, #AIPS_OPACR_8_15]
  49         str     r1, [r0, #AIPS_OPACR_16_23]
  50         str     r1, [r0, #AIPS_OPACR_24_31]
  51         str     r1, [r0, #AIPS_OPACR_32_39]
  52         str     r1, [r2, #AIPS_OPACR_0_7]
  53         str     r1, [r2, #AIPS_OPACR_8_15]
  54         str     r1, [r2, #AIPS_OPACR_16_23]
  55         str     r1, [r2, #AIPS_OPACR_24_31]
  56         str     r1, [r2, #AIPS_OPACR_32_39]
  57 .endm
  58
  59 /*
  60  * MAX (Multi-Layer AHB Crossbar Switch) setup
  61  *
  62  * Default argument values:
  63  *  - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
  64  *  - SGPCR: always park on last master
  65  *  - MGPCR: restore default values
  66  */
  67 .macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
  68         ldr     r0, =MAX_BASE_ADDR
  69         ldr     r1, =\mpr
  70         str     r1, [r0, #MAX_MPR0]     /* for S0 */
  71         str     r1, [r0, #MAX_MPR1]     /* for S1 */
  72         str     r1, [r0, #MAX_MPR2]     /* for S2 */
  73         str     r1, [r0, #MAX_MPR3]     /* for S3 */
  74         str     r1, [r0, #MAX_MPR4]     /* for S4 */
  75         ldr     r1, =\sgpcr
  76         str     r1, [r0, #MAX_SGPCR0]   /* for S0 */
  77         str     r1, [r0, #MAX_SGPCR1]   /* for S1 */
  78         str     r1, [r0, #MAX_SGPCR2]   /* for S2 */
  79         str     r1, [r0, #MAX_SGPCR3]   /* for S3 */
  80         str     r1, [r0, #MAX_SGPCR4]   /* for S4 */
  81         ldr     r1, =\mgpcr
  82         str     r1, [r0, #MAX_MGPCR0]   /* for M0 */
  83         str     r1, [r0, #MAX_MGPCR1]   /* for M1 */
  84         str     r1, [r0, #MAX_MGPCR2]   /* for M2 */
  85         str     r1, [r0, #MAX_MGPCR3]   /* for M3 */
  86         str     r1, [r0, #MAX_MGPCR4]   /* for M4 */
  87         str     r1, [r0, #MAX_MGPCR5]   /* for M5 */
  88 .endm
  89
  90 /*
  91  * M3IF setup
  92  *
  93  * Default argument values:
  94  *  - CTL:
  95  * MRRP[0] = L2CC0 not on priority list (0 << 0)        = 0x00000000
  96  * MRRP[1] = L2CC1 not on priority list (0 << 1)        = 0x00000000
  97  * MRRP[2] = MBX not on priority list (0 << 2)          = 0x00000000
  98  * MRRP[3] = MAX1 not on priority list (0 << 3)         = 0x00000000
  99  * MRRP[4] = SDMA not on priority list (0 << 4)         = 0x00000000
 100  * MRRP[5] = MPEG4 not on priority list (0 << 5)        = 0x00000000
 101  * MRRP[6] = IPU1 on priority list (1 << 6)             = 0x00000040
 102  * MRRP[7] = IPU2 not on priority list (0 << 7)         = 0x00000000
 103  *                                                      ------------
 104  *                                                        0x00000040
 105  */
 106 .macro init_m3if ctl=0x00000040
 107         /* M3IF Control Register (M3IFCTL) */
 108         write32 M3IF_BASE_ADDR, \ctl
 109 .endm
 110
 111 .macro core_init
 112         mrc     p15, 0, r1, c1, c0, 0
 113
 114         /* Set branch prediction enable */
 115         mrc     p15, 0, r0, c1, c0, 1
 116         orr     r0, r0, #7
 117         mcr     p15, 0, r0, c1, c0, 1
 118         orr     r1, r1, #1 << 11
 119
 120         /* Set unaligned access enable */
 121         orr     r1, r1, #1 << 22
 122
 123         /* Set low int latency enable */
 124         orr     r1, r1, #1 << 21
 125
 126         mcr     p15, 0, r1, c1, c0, 0
 127
 128         mov     r0, #0
 129
 130         mcr     p15, 0, r0, c15, c2, 4
 131
 132         mcr     p15, 0, r0, c7, c7, 0   /* Invalidate I cache and D cache */
 133         mcr     p15, 0, r0, c8, c7, 0   /* Invalidate TLBs */
 134         mcr     p15, 0, r0, c7, c10, 4  /* Drain the write buffer */
 135
 136         /* Setup the Peripheral Port Memory Remap Register */
 137         ldr     r0, =0x40000015         /* Start from AIPS 2-GB region */
 138         mcr     p15, 0, r0, c15, c2, 4
 139 .endm