arch/arm/include/asm/arch-omap3/dma.h

   1 #ifndef __SDMA_H
   2 #define __SDMA_H
   3
   4 /* Copyright (C) 2011
   5  * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /* Functions */
  24 void omap3_dma_init(void);
  25 int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
  26                 uint32_t sze);
  27 int omap3_dma_start_transfer(uint32_t chan);
  28 int omap3_dma_wait_for_transfer(uint32_t chan);
  29 int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
  30 int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
  31
  32 /* Register settings */
  33 #define CSDP_DATA_TYPE_8BIT             0x0
  34 #define CSDP_DATA_TYPE_16BIT            0x1
  35 #define CSDP_DATA_TYPE_32BIT            0x2
  36 #define CSDP_SRC_BURST_SINGLE           (0x0 << 7)
  37 #define CSDP_SRC_BURST_EN_16BYTES       (0x1 << 7)
  38 #define CSDP_SRC_BURST_EN_32BYTES       (0x2 << 7)
  39 #define CSDP_SRC_BURST_EN_64BYTES       (0x3 << 7)
  40 #define CSDP_DST_BURST_SINGLE           (0x0 << 14)
  41 #define CSDP_DST_BURST_EN_16BYTES       (0x1 << 14)
  42 #define CSDP_DST_BURST_EN_32BYTES       (0x2 << 14)
  43 #define CSDP_DST_BURST_EN_64BYTES       (0x3 << 14)
  44 #define CSDP_DST_ENDIAN_LOCK_ADAPT      (0x0 << 18)
  45 #define CSDP_DST_ENDIAN_LOCK_LOCK       (0x1 << 18)
  46 #define CSDP_DST_ENDIAN_LITTLE          (0x0 << 19)
  47 #define CSDP_DST_ENDIAN_BIG             (0x1 << 19)
  48 #define CSDP_SRC_ENDIAN_LOCK_ADAPT      (0x0 << 20)
  49 #define CSDP_SRC_ENDIAN_LOCK_LOCK       (0x1 << 20)
  50 #define CSDP_SRC_ENDIAN_LITTLE          (0x0 << 21)
  51 #define CSDP_SRC_ENDIAN_BIG             (0x1 << 21)
  52
  53 #define CCR_READ_PRIORITY_LOW           (0x0 << 6)
  54 #define CCR_READ_PRIORITY_HIGH          (0x1 << 6)
  55 #define CCR_ENABLE_DISABLED             (0x0 << 7)
  56 #define CCR_ENABLE_ENABLE               (0x1 << 7)
  57 #define CCR_SRC_AMODE_CONSTANT          (0x0 << 12)
  58 #define CCR_SRC_AMODE_POST_INC          (0x1 << 12)
  59 #define CCR_SRC_AMODE_SINGLE_IDX        (0x2 << 12)
  60 #define CCR_SRC_AMODE_DOUBLE_IDX        (0x3 << 12)
  61 #define CCR_DST_AMODE_CONSTANT          (0x0 << 14)
  62 #define CCR_DST_AMODE_POST_INC          (0x1 << 14)
  63 #define CCR_DST_AMODE_SINGLE_IDX        (0x2 << 14)
  64 #define CCR_DST_AMODE_SOUBLE_IDX        (0x3 << 14)
  65
  66 #define CCR_RD_ACTIVE_MASK              (1 << 9)
  67 #define CCR_WR_ACTIVE_MASK              (1 << 10)
  68
  69 #define CSR_TRANS_ERR                   (1 << 8)
  70 #define CSR_SUPERVISOR_ERR              (1 << 10)
  71 #define CSR_MISALIGNED_ADRS_ERR         (1 << 11)
  72
  73 /* others */
  74 #define CHAN_NR_MIN                     0
  75 #define CHAN_NR_MAX                     31
  76
  77 #endif /* __SDMA_H */