arch/arm/include/asm/arch-omap3/emif4.h

   1 /*
   2  * Auther:
   3  *       Vaibhav Hiremath <hvaibhav@ti.com>
   4  *
   5  * Copyright (C) 2010
   6  * Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _EMIF_H_
  25 #define _EMIF_H_
  26
  27 /*
  28  * Configuration values
  29  */
  30 #define EMIF4_TIM1_T_RP         (0x3 << 25)
  31 #define EMIF4_TIM1_T_RCD        (0x3 << 21)
  32 #define EMIF4_TIM1_T_WR         (0x3 << 17)
  33 #define EMIF4_TIM1_T_RAS        (0x8 << 12)
  34 #define EMIF4_TIM1_T_RC         (0xA << 6)
  35 #define EMIF4_TIM1_T_RRD        (0x2 << 3)
  36 #define EMIF4_TIM1_T_WTR        (0x2)
  37
  38 #define EMIF4_TIM2_T_XP         (0x2 << 28)
  39 #define EMIF4_TIM2_T_ODT        (0x0 << 25)
  40 #define EMIF4_TIM2_T_XSNR       (0x1C << 16)
  41 #define EMIF4_TIM2_T_XSRD       (0xC8 << 6)
  42 #define EMIF4_TIM2_T_RTP        (0x1 << 3)
  43 #define EMIF4_TIM2_T_CKE        (0x2)
  44
  45 #define EMIF4_TIM3_T_RFC        (0x25 << 4)
  46 #define EMIF4_TIM3_T_RAS_MAX    (0x7)
  47
  48 #define EMIF4_PWR_IDLE_MODE     (0x2 << 30)
  49 #define EMIF4_PWR_DPD_DIS       (0x0 << 10)
  50 #define EMIF4_PWR_DPD_EN        (0x1 << 10)
  51 #define EMIF4_PWR_LP_MODE       (0x0 << 8)
  52 #define EMIF4_PWR_PM_TIM        (0x0)
  53
  54 #define EMIF4_INITREF_DIS       (0x0 << 31)
  55 #define EMIF4_REFRESH_RATE      (0x50F)
  56
  57 #define EMIF4_CFG_SDRAM_TYP     (0x2 << 29)
  58 #define EMIF4_CFG_IBANK_POS     (0x0 << 27)
  59 #define EMIF4_CFG_DDR_TERM      (0x0 << 24)
  60 #define EMIF4_CFG_DDR2_DDQS     (0x1 << 23)
  61 #define EMIF4_CFG_DDR_DIS_DLL   (0x0 << 20)
  62 #define EMIF4_CFG_SDR_DRV       (0x0 << 18)
  63 #define EMIF4_CFG_NARROW_MD     (0x0 << 14)
  64 #define EMIF4_CFG_CL            (0x5 << 10)
  65 #define EMIF4_CFG_ROWSIZE       (0x0 << 7)
  66 #define EMIF4_CFG_IBANK         (0x3 << 4)
  67 #define EMIF4_CFG_EBANK         (0x0 << 3)
  68 #define EMIF4_CFG_PGSIZE        (0x2)
  69
  70 /*
  71  * EMIF4 PHY Control 1 register configuration
  72  */
  73 #define EMIF4_DDR1_EXT_STRB_EN  (0x1 << 7)
  74 #define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7)
  75 #define EMIF4_DDR1_PWRDN_DIS    (0x0 << 6)
  76 #define EMIF4_DDR1_PWRDN_EN     (0x1 << 6)
  77 #define EMIF4_DDR1_READ_LAT     (0x6 << 0)
  78
  79 #endif /* endif _EMIF_H_ */