arch/arm/include/asm/arch-omap4/cpu.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #ifndef _CPU_H
  26 #define _CPU_H
  27
  28 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  29 #include <asm/types.h>
  30 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  31
  32 #ifndef __KERNEL_STRICT_NAMES
  33 #ifndef __ASSEMBLY__
  34 struct gpmc_cs {
  35         u32 config1;            /* 0x00 */
  36         u32 config2;            /* 0x04 */
  37         u32 config3;            /* 0x08 */
  38         u32 config4;            /* 0x0C */
  39         u32 config5;            /* 0x10 */
  40         u32 config6;            /* 0x14 */
  41         u32 config7;            /* 0x18 */
  42         u32 nand_cmd;           /* 0x1C */
  43         u32 nand_adr;           /* 0x20 */
  44         u32 nand_dat;           /* 0x24 */
  45         u8 res[8];              /* blow up to 0x30 byte */
  46 };
  47
  48 struct gpmc {
  49         u8 res1[0x10];
  50         u32 sysconfig;          /* 0x10 */
  51         u8 res2[0x4];
  52         u32 irqstatus;          /* 0x18 */
  53         u32 irqenable;          /* 0x1C */
  54         u8 res3[0x20];
  55         u32 timeout_control;    /* 0x40 */
  56         u8 res4[0xC];
  57         u32 config;             /* 0x50 */
  58         u32 status;             /* 0x54 */
  59         u8 res5[0x8];   /* 0x58 */
  60         struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
  61         u8 res6[0x14];          /* 0x1E0 */
  62         u32 ecc_config;         /* 0x1F4 */
  63         u32 ecc_control;        /* 0x1F8 */
  64         u32 ecc_size_config;    /* 0x1FC */
  65         u32 ecc1_result;        /* 0x200 */
  66         u32 ecc2_result;        /* 0x204 */
  67         u32 ecc3_result;        /* 0x208 */
  68         u32 ecc4_result;        /* 0x20C */
  69         u32 ecc5_result;        /* 0x210 */
  70         u32 ecc6_result;        /* 0x214 */
  71         u32 ecc7_result;        /* 0x218 */
  72         u32 ecc8_result;        /* 0x21C */
  73         u32 ecc9_result;        /* 0x220 */
  74 };
  75
  76 /* Used for board specific gpmc initialization */
  77 extern struct gpmc *gpmc_cfg;
  78
  79 struct gptimer {
  80         u32 tidr;               /* 0x00 r */
  81         u8 res[0xc];
  82         u32 tiocp_cfg;          /* 0x10 rw */
  83         u32 tistat;             /* 0x14 r */
  84         u32 tisr;               /* 0x18 rw */
  85         u32 tier;               /* 0x1c rw */
  86         u32 twer;               /* 0x20 rw */
  87         u32 tclr;               /* 0x24 rw */
  88         u32 tcrr;               /* 0x28 rw */
  89         u32 tldr;               /* 0x2c rw */
  90         u32 ttgr;               /* 0x30 rw */
  91         u32 twpc;               /* 0x34 r */
  92         u32 tmar;               /* 0x38 rw */
  93         u32 tcar1;              /* 0x3c r */
  94         u32 tcicr;              /* 0x40 rw */
  95         u32 tcar2;              /* 0x44 r */
  96 };
  97 #endif /* __ASSEMBLY__ */
  98 #endif /* __KERNEL_STRICT_NAMES */
  99
 100 /* enable sys_clk NO-prescale /1 */
 101 #define GPT_EN                  ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 102
 103 /* Watchdog */
 104 #ifndef __KERNEL_STRICT_NAMES
 105 #ifndef __ASSEMBLY__
 106 struct watchdog {
 107         u8 res1[0x34];
 108         u32 wwps;               /* 0x34 r */
 109         u8 res2[0x10];
 110         u32 wspr;               /* 0x48 rw */
 111 };
 112 #endif /* __ASSEMBLY__ */
 113 #endif /* __KERNEL_STRICT_NAMES */
 114
 115 #define WD_UNLOCK1              0xAAAA
 116 #define WD_UNLOCK2              0x5555
 117
 118 #define TCLR_ST                 (0x1 << 0)
 119 #define TCLR_AR                 (0x1 << 1)
 120 #define TCLR_PRE                (0x1 << 5)
 121
 122 /* GPMC BASE */
 123 #define GPMC_BASE               (OMAP44XX_GPMC_BASE)
 124
 125 /* I2C base */
 126 #define I2C_BASE1               (OMAP44XX_L4_PER_BASE + 0x70000)
 127 #define I2C_BASE2               (OMAP44XX_L4_PER_BASE + 0x72000)
 128 #define I2C_BASE3               (OMAP44XX_L4_PER_BASE + 0x60000)
 129 #define I2C_BASE4               (OMAP44XX_L4_PER_BASE + 0x350000)
 130
 131 /* MUSB base */
 132 #define MUSB_BASE               (OMAP44XX_L4_CORE_BASE + 0xAB000)
 133
 134 /* OMAP4 GPIO registers */
 135 #define OMAP_GPIO_REVISION              0x0000
 136 #define OMAP_GPIO_SYSCONFIG             0x0010
 137 #define OMAP_GPIO_SYSSTATUS             0x0114
 138 #define OMAP_GPIO_IRQSTATUS1            0x0118
 139 #define OMAP_GPIO_IRQSTATUS2            0x0128
 140 #define OMAP_GPIO_IRQENABLE2            0x012c
 141 #define OMAP_GPIO_IRQENABLE1            0x011c
 142 #define OMAP_GPIO_WAKE_EN               0x0120
 143 #define OMAP_GPIO_CTRL                  0x0130
 144 #define OMAP_GPIO_OE                    0x0134
 145 #define OMAP_GPIO_DATAIN                0x0138
 146 #define OMAP_GPIO_DATAOUT               0x013c
 147 #define OMAP_GPIO_LEVELDETECT0          0x0140
 148 #define OMAP_GPIO_LEVELDETECT1          0x0144
 149 #define OMAP_GPIO_RISINGDETECT          0x0148
 150 #define OMAP_GPIO_FALLINGDETECT         0x014c
 151 #define OMAP_GPIO_DEBOUNCE_EN           0x0150
 152 #define OMAP_GPIO_DEBOUNCE_VAL          0x0154
 153 #define OMAP_GPIO_CLEARIRQENABLE1       0x0160
 154 #define OMAP_GPIO_SETIRQENABLE1         0x0164
 155 #define OMAP_GPIO_CLEARWKUENA           0x0180
 156 #define OMAP_GPIO_SETWKUENA             0x0184
 157 #define OMAP_GPIO_CLEARDATAOUT          0x0190
 158 #define OMAP_GPIO_SETDATAOUT            0x0194
 159
 160 /*
 161  * PRCM
 162  */
 163
 164 /* PRM */
 165 #define PRM_BASE                0x4A306000
 166 #define PRM_DEVICE_BASE         (PRM_BASE + 0x1B00)
 167
 168 #define PRM_RSTCTRL             PRM_DEVICE_BASE
 169 #define PRM_RSTCTRL_RESET       0x01
 170 #define PRM_RSTST               (PRM_DEVICE_BASE + 0x4)
 171 #define PRM_RSTST_WARM_RESET_MASK       0x07EA
 172
 173 #endif /* _CPU_H */