arch/nds32/cpu/n1213/ag102/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011 Andes Technology Corporation
   3  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 .text
   9
  10 #include <common.h>
  11 #include <config.h>
  12
  13 #include <asm/macro.h>
  14 #include <generated/asm-offsets.h>
  15
  16 /*
  17  * parameters for Synopsys DWC DDR2/DDR1 Memory Controller
  18  */
  19 #define DDR2C_BASE_A            (CONFIG_DWCDDR21MCTL_BASE)
  20 #define DDR2C_CCR_A             (DDR2C_BASE_A + DWCDDR21MCTL_CCR)
  21 #define DDR2C_DCR_A             (DDR2C_BASE_A + DWCDDR21MCTL_DCR)
  22 #define DDR2C_IOCR_A            (DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
  23 #define DDR2C_CSR_A             (DDR2C_BASE_A + DWCDDR21MCTL_CSR)
  24 #define DDR2C_DRR_A             (DDR2C_BASE_A + DWCDDR21MCTL_DRR)
  25 #define DDR2C_DLLCR0_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
  26 #define DDR2C_DLLCR1_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
  27 #define DDR2C_DLLCR2_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
  28 #define DDR2C_DLLCR3_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
  29 #define DDR2C_DLLCR4_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
  30 #define DDR2C_DLLCR5_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
  31 #define DDR2C_DLLCR6_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
  32 #define DDR2C_DLLCR7_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
  33 #define DDR2C_DLLCR8_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
  34 #define DDR2C_DLLCR9_A          (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
  35 #define DDR2C_RSLR0_A           (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
  36 #define DDR2C_RDGR0_A           (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
  37 #define DDR2C_DTAR_A            (DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
  38 #define DDR2C_MR_A              (DDR2C_BASE_A + DWCDDR21MCTL_MR)
  39
  40 #define DDR2C_CCR_D             CONFIG_SYS_DWCDDR21MCTL_CCR
  41 #define DDR2C_CCR_D2            CONFIG_SYS_DWCDDR21MCTL_CCR2
  42 #define DDR2C_DCR_D             CONFIG_SYS_DWCDDR21MCTL_DCR
  43 #define DDR2C_IOCR_D            CONFIG_SYS_DWCDDR21MCTL_IOCR
  44 #define DDR2C_CSR_D             CONFIG_SYS_DWCDDR21MCTL_CSR
  45 #define DDR2C_DRR_D             CONFIG_SYS_DWCDDR21MCTL_DRR
  46 #define DDR2C_RSLR0_D           CONFIG_SYS_DWCDDR21MCTL_RSLR0
  47 #define DDR2C_RDGR0_D           CONFIG_SYS_DWCDDR21MCTL_RDGR0
  48 #define DDR2C_DTAR_D            CONFIG_SYS_DWCDDR21MCTL_DTAR
  49 #define DDR2C_MR_D              CONFIG_SYS_DWCDDR21MCTL_MR
  50
  51 #define DDR2C_DLLCR0_D  CONFIG_SYS_DWCDDR21MCTL_DLLCR0  /* 0-9 are same */
  52
  53 /*
  54  * parameters for the ahbc controller
  55  */
  56 #define AHBC_CR_A               (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
  57 #define AHBC_BSR6_A     (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
  58
  59 #define AHBC_BSR6_D             CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
  60
  61 /*
  62  * parameters for the ANDES PCU controller
  63  */
  64 #define PCU_PCS4_A              (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
  65 #define PCU_PCS4_D              CONFIG_SYS_ANDES_CPU_PCS4
  66
  67 /*
  68  * numeric 7 segment display
  69  */
  70 .macro  led, num
  71         write32 CONFIG_DEBUG_LED, \num
  72 .endm
  73
  74 /*
  75  * Waiting for SDRAM to set up
  76  */
  77 /*
  78 .macro  wait_sdram
  79         li      $r0, DDR2C_CSR_A
  80 1:
  81         lwi     $r1, [$r0+FTSDMC021_CR2]
  82         bnez    $r1, 1b
  83 .endm
  84 */
  85
  86 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  87 .globl  lowlevel_init
  88 lowlevel_init:
  89         move    $r10, $lp
  90
  91         /* U200 */
  92 !       led     0x00
  93 !       jal     scale_to_500mhz
  94
  95         led     0x10
  96         jal     mem_init
  97
  98         led     0x20
  99         jal     remap
 100
 101         led     0x30
 102         ret     $r10
 103
 104 scale_to_500mhz:
 105         move    $r11, $lp
 106
 107         /*
 108          * scale to 500Mhz
 109          */
 110         led     0x01
 111         write32 PCU_PCS4_A, 0x1102000f                  ! save data to PCS4
 112
 113         move    $lp, $r11
 114         ret
 115
 116 mem_init:
 117         move    $r11, $lp
 118
 119         /*
 120          * config AHB Controller
 121          */
 122         led     0x12
 123         write32 AHBC_BSR6_A, AHBC_BSR6_D
 124
 125         /*
 126          * config Synopsys DWC DDR2/DDR1 Memory Controller
 127          */
 128 ddr2c_init:
 129 set_dcr:
 130         led     0x14
 131         write32 DDR2C_DCR_A, DDR2C_DCR_D                        ! 0x000020d4
 132
 133 auto_sizing:
 134         /*
 135          * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
 136          */
 137 set_iocr:
 138         led     0x19
 139         write32 DDR2C_IOCR_A, DDR2C_IOCR_D
 140 set_drr:
 141         led     0x16
 142         write32 DDR2C_DRR_A, DDR2C_DRR_D                        ! 0x00034812
 143 set_dllcr:
 144         led     0x18
 145         write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
 146         write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
 147         write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
 148         write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
 149         write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
 150         write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
 151         write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
 152         write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
 153         write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
 154         write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
 155 set_rslr0:
 156         write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D                    ! 0x00000040
 157 set_rdgr0:
 158         write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D                    ! 0x000055cf
 159 set_dtar:
 160         led     0x15
 161         write32 DDR2C_DTAR_A, DDR2C_DTAR_D                      ! 0x00100000
 162 set_mode:
 163         led     0x17
 164         write32 DDR2C_MR_A, DDR2C_MR_D                          ! 0x00000852
 165 set_ccr:
 166         write32 DDR2C_CCR_A, DDR2C_CCR_D
 167
 168 #ifdef TRIGGER_INIT:
 169 trigger_init:
 170         write32 DDR2C_CCR_A, DDR2C_CCR_D                        ! 0x80020000
 171
 172         /* Wait for ddr init state to be set */
 173         msync   ALL
 174         isb
 175
 176         /* Wait until the config initialization is finish */
 177 1:
 178         la      $r4, DDR2C_CSR_A
 179         lwi     $r5, [$r4]
 180         srli    $r5, $r5, 23
 181         bnez    $r5, 1b
 182 #endif
 183
 184 data_training:
 185 !       write32 DDR2C_CCR_A, DDR2C_CCR_D2                       ! 0x40020004
 186
 187         /* Wait for ddr init state to be set */
 188         msync   ALL
 189         isb
 190
 191         /* wait until the ddr data trainning is complete */
 192 1:
 193         la      $r4, DDR2C_CSR_A
 194         lwi     $r5, [$r4]
 195         srli    $r6, $r5, 23
 196         bnez    $r6, 1b
 197
 198         lwi     $r1, [$r4]
 199         srli    $r6, $r5, 20
 200         li      $r5, 0x00ffffff
 201         swi     $r1, [$r4]
 202         bnez    $r6, ddr2c_init
 203
 204         led     0x1a
 205         move    $lp, $r11
 206         ret
 207
 208 remap:
 209         move    $r11, $lp
 210 #ifdef __NDS32_N1213_43U1H__    /* NDS32 V0 ISA - AG101 Only */
 211         bal     2f
 212 relo_base:
 213         move    $r0, $lp
 214 #else
 215 relo_base:
 216         mfusr   $r0, $pc
 217 #endif /* __NDS32_N1213_43U1H__ */
 218
 219         /*
 220          * Remapping
 221          */
 222 #ifdef CONFIG_MEM_REMAP
 223         /*
 224          * Copy ROM code to SDRAM base for memory remap layout.
 225          * This is not the real relocation, the real relocation is the function
 226          * relocate_code() is start.S which supports the systems is memory
 227          * remapped or not.
 228          */
 229         /*
 230          * Doing memory remap is essential for preparing some non-OS or RTOS
 231          * applications.
 232          *
 233          * This is also a must on ADP-AG101 board.
 234          * The reason is because the ROM/FLASH circuit on PCB board.
 235          * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
 236          * ROM/FLASH is used to boot.
 237          *
 238          * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
 239          * and the FLASH is connected to BANK1.
 240          * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
 241          * and the FLASH is connected to BANK0.
 242          * It will occur problem when doing flash probing if the flash is at
 243          * BANK0 (0x00000000) while memory remapping was skipped.
 244          *
 245          * Other board like ADP-AG101P may not enable this since there is only
 246          * a FLASH connected to bank0.
 247          */
 248         led     0x21
 249         li      $r4, PHYS_SDRAM_0_AT_INIT               /* 0x10000000 */
 250         li      $r5, 0x0
 251         la      $r1, relo_base                          /* get $pc or $lp */
 252         sub     $r2, $r0, $r1
 253         sethi   $r6, hi20(_end)
 254         ori     $r6, $r6, lo12(_end)
 255         add     $r6, $r6, $r2
 256 1:
 257         lwi.p   $r7, [$r5], #4
 258         swi.p   $r7, [$r4], #4
 259         blt     $r5, $r6, 1b
 260
 261         /* set remap bit */
 262         /*
 263          * MEM remap bit is operational
 264          * - use it to map writeable memory at 0x00000000, in place of flash
 265          * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
 266          * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
 267          */
 268         led     0x2c
 269         setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP          ! 0x1
 270
 271 #endif /* #ifdef CONFIG_MEM_REMAP */
 272         move    $lp, $r11
 273 2:
 274         ret
 275
 276 .globl show_led
 277 show_led:
 278     li      $r8, (CONFIG_DEBUG_LED)
 279     swi     $r7, [$r8]
 280     ret
 281 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */