2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <asm/fsl_law.h>
23 #include <asm/fsl_serdes.h>
24 #include <asm/fsl_srio.h>
26 #include <linux/compiler.h>
28 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
33 #include "../../../../drivers/block/fsl_sata.h"
35 DECLARE_GLOBAL_DATA_PTR
;
38 extern qe_iop_conf_t qe_iop_conf_tab
[];
39 extern void qe_config_iopin(u8 port
, u8 pin
, int dir
,
40 int open_drain
, int assign
);
41 extern void qe_init(uint qe_base
);
42 extern void qe_reset(void);
44 static void config_qe_ioports(void)
47 int dir
, open_drain
, assign
;
50 for (i
= 0; qe_iop_conf_tab
[i
].assign
!= QE_IOP_TAB_END
; i
++) {
51 port
= qe_iop_conf_tab
[i
].port
;
52 pin
= qe_iop_conf_tab
[i
].pin
;
53 dir
= qe_iop_conf_tab
[i
].dir
;
54 open_drain
= qe_iop_conf_tab
[i
].open_drain
;
55 assign
= qe_iop_conf_tab
[i
].assign
;
56 qe_config_iopin(port
, pin
, dir
, open_drain
, assign
);
62 void config_8560_ioports (volatile ccsr_cpm_t
* cpm
)
66 for (portnum
= 0; portnum
< 4; portnum
++) {
73 iop_conf_t
*iopc
= (iop_conf_t
*) & iop_conf_tab
[portnum
][0];
74 iop_conf_t
*eiopc
= iopc
+ 32;
79 * index 0 refers to pin 31,
80 * index 31 refers to pin 0
82 while (iopc
< eiopc
) {
102 volatile ioport_t
*iop
= ioport_addr (cpm
, portnum
);
106 * the (somewhat confused) paragraph at the
107 * bottom of page 35-5 warns that there might
108 * be "unknown behaviour" when programming
109 * PSORx and PDIRx, if PPARx = 1, so I
110 * decided this meant I had to disable the
111 * dedicated function first, and enable it
115 iop
->psor
= (iop
->psor
& tpmsk
) | psor
;
116 iop
->podr
= (iop
->podr
& tpmsk
) | podr
;
117 iop
->pdat
= (iop
->pdat
& tpmsk
) | pdat
;
118 iop
->pdir
= (iop
->pdir
& tpmsk
) | pdir
;
125 #ifdef CONFIG_SYS_FSL_CPC
126 static void enable_cpc(void)
131 cpc_corenet_t
*cpc
= (cpc_corenet_t
*)CONFIG_SYS_FSL_CPC_ADDR
;
133 for (i
= 0; i
< CONFIG_SYS_NUM_CPC
; i
++, cpc
++) {
134 u32 cpccfg0
= in_be32(&cpc
->cpccfg0
);
135 size
+= CPC_CFG0_SZ_K(cpccfg0
);
136 #ifdef CONFIG_RAMBOOT_PBL
137 if (in_be32(&cpc
->cpcsrcr0
) & CPC_SRCR0_SRAMEN
) {
138 /* find and disable LAW of SRAM */
139 struct law_entry law
= find_law(CONFIG_SYS_INIT_L3_ADDR
);
141 if (law
.index
== -1) {
142 printf("\nFatal error happened\n");
145 disable_law(law
.index
);
147 clrbits_be32(&cpc
->cpchdbcr0
, CPC_HDBCR0_CDQ_SPEC_DIS
);
148 out_be32(&cpc
->cpccsr0
, 0);
149 out_be32(&cpc
->cpcsrcr0
, 0);
153 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
154 setbits_be32(&cpc
->cpchdbcr0
, CPC_HDBCR0_TAG_ECC_SCRUB_DIS
);
156 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
157 setbits_be32(&cpc
->cpchdbcr0
, CPC_HDBCR0_DATA_ECC_SCRUB_DIS
);
159 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
160 setbits_be32(&cpc
->cpchdbcr0
, 1 << (31 - 21));
163 out_be32(&cpc
->cpccsr0
, CPC_CSR0_CE
| CPC_CSR0_PE
);
164 /* Read back to sync write */
165 in_be32(&cpc
->cpccsr0
);
169 printf("Corenet Platform Cache: %d KB enabled\n", size
);
172 static void invalidate_cpc(void)
175 cpc_corenet_t
*cpc
= (cpc_corenet_t
*)CONFIG_SYS_FSL_CPC_ADDR
;
177 for (i
= 0; i
< CONFIG_SYS_NUM_CPC
; i
++, cpc
++) {
178 /* skip CPC when it used as all SRAM */
179 if (in_be32(&cpc
->cpcsrcr0
) & CPC_SRCR0_SRAMEN
)
181 /* Flash invalidate the CPC and clear all the locks */
182 out_be32(&cpc
->cpccsr0
, CPC_CSR0_FI
| CPC_CSR0_LFC
);
183 while (in_be32(&cpc
->cpccsr0
) & (CPC_CSR0_FI
| CPC_CSR0_LFC
))
189 #define invalidate_cpc()
190 #endif /* CONFIG_SYS_FSL_CPC */
193 * Breathe some life into the CPU...
195 * Set up the memory map
196 * initialize a bunch of registers
199 #ifdef CONFIG_FSL_CORENET
200 static void corenet_tb_init(void)
202 volatile ccsr_rcpm_t
*rcpm
=
203 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR
);
204 volatile ccsr_pic_t
*pic
=
205 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR
);
206 u32 whoami
= in_be32(&pic
->whoami
);
208 /* Enable the timebase register for this core */
209 out_be32(&rcpm
->ctbenrl
, (1 << whoami
));
213 void cpu_init_f (void)
215 extern void m8560_cpm_reset (void);
216 #ifdef CONFIG_SYS_DCSRBAR_PHYS
217 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
219 #if defined(CONFIG_SECURE_BOOT)
220 struct law_entry law
;
222 #ifdef CONFIG_MPC8548
223 ccsr_local_ecm_t
*ecm
= (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR
);
224 uint svr
= get_svr();
227 * CPU2 errata workaround: A core hang possible while executing
228 * a msync instruction and a snoopable transaction from an I/O
229 * master tagged to make quick forward progress is present.
230 * Fixed in silicon rev 2.1.
232 if ((SVR_MAJ(svr
) == 1) || ((SVR_MAJ(svr
) == 2 && SVR_MIN(svr
) == 0x0)))
233 out_be32(&ecm
->eebpcr
, in_be32(&ecm
->eebpcr
) | (1 << 16));
239 #if defined(CONFIG_SECURE_BOOT)
240 /* Disable the LAW created for NOR flash by the PBI commands */
241 law
= find_law(CONFIG_SYS_PBI_FLASH_BASE
);
243 disable_law(law
.index
);
247 config_8560_ioports((ccsr_cpm_t
*)CONFIG_SYS_MPC85xx_CPM_ADDR
);
250 init_early_memctl_regs();
252 #if defined(CONFIG_CPM2)
256 /* Config QE ioports */
259 #if defined(CONFIG_FSL_DMA)
262 #ifdef CONFIG_FSL_CORENET
265 init_used_tlb_cams();
267 /* Invalidate the CPC before DDR gets enabled */
270 #ifdef CONFIG_SYS_DCSRBAR_PHYS
271 /* set DCSRCR so that DCSR space is 1G */
272 setbits_be32(&gur
->dcsrcr
, FSL_CORENET_DCSR_SZ_1G
);
273 in_be32(&gur
->dcsrcr
);
278 /* Implement a dummy function for those platforms w/o SERDES */
279 static void __fsl_serdes__init(void)
283 __attribute__((weak
, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
285 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
286 int enable_cluster_l2(void)
290 ccsr_gur_t
*gur
= (void __iomem
*)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
291 struct ccsr_cluster_l2 __iomem
*l2cache
;
293 cluster
= in_be32(&gur
->tp_cluster
[i
].lower
);
294 if (cluster
& TP_CLUSTER_EOC
)
297 /* The first cache has already been set up, so skip it */
300 /* Look through the remaining clusters, and set up their caches */
302 int j
, cluster_valid
= 0;
304 l2cache
= (void __iomem
*)(CONFIG_SYS_FSL_CLUSTER_1_L2
+ i
* 0x40000);
306 cluster
= in_be32(&gur
->tp_cluster
[i
].lower
);
308 /* check that at least one core/accel is enabled in cluster */
309 for (j
= 0; j
< 4; j
++) {
310 u32 idx
= (cluster
>> (j
*8)) & TP_CLUSTER_INIT_MASK
;
311 u32 type
= in_be32(&gur
->tp_ityp
[idx
]);
313 if (type
& TP_ITYP_AV
)
318 /* set stash ID to (cluster) * 2 + 32 + 1 */
319 clrsetbits_be32(&l2cache
->l2csr1
, 0xff, 32 + i
* 2 + 1);
321 printf("enable l2 for cluster %d %p\n", i
, l2cache
);
323 out_be32(&l2cache
->l2csr0
, L2CSR0_L2FI
|L2CSR0_L2LFC
);
324 while ((in_be32(&l2cache
->l2csr0
)
325 & (L2CSR0_L2FI
|L2CSR0_L2LFC
)) != 0)
327 out_be32(&l2cache
->l2csr0
, L2CSR0_L2E
|L2CSR0_L2PE
|L2CSR0_L2REP_MODE
);
330 } while (!(cluster
& TP_CLUSTER_EOC
));
337 * Initialize L2 as cache.
339 * The newer 8548, etc, parts have twice as much cache, but
340 * use the same bit-encoding as the older 8555, etc, parts.
345 __maybe_unused u32 svr
= get_svr();
346 #ifdef CONFIG_SYS_LBC_LCRR
347 fsl_lbc_t
*lbc
= (void __iomem
*)LBC_BASE_ADDR
;
349 #ifdef CONFIG_L2_CACHE
350 ccsr_l2cache_t
*l2cache
= (void __iomem
*)CONFIG_SYS_MPC85xx_L2_ADDR
;
351 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
352 struct ccsr_cluster_l2
* l2cache
= (void __iomem
*)CONFIG_SYS_FSL_CLUSTER_1_L2
;
354 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
355 extern int spin_table_compat
;
359 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
360 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
362 * CPU22 and NMG_CPU_A011 share the same workaround.
363 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
364 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
365 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
366 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
367 * be disabled by hwconfig with syntax:
369 * fsl_cpu_a011:disable
371 extern int enable_cpu_a011_workaround
;
372 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
373 enable_cpu_a011_workaround
= (SVR_MAJ(svr
) < 3);
375 char buffer
[HWCONFIG_BUFFER_SIZE
];
379 n
= getenv_f("hwconfig", buffer
, sizeof(buffer
));
383 res
= hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf
);
385 enable_cpu_a011_workaround
= 0;
387 if (n
>= HWCONFIG_BUFFER_SIZE
) {
388 printf("fsl_cpu_a011 was not found. hwconfig variable "
389 "may be too long\n");
391 enable_cpu_a011_workaround
=
392 (SVR_SOC_VER(svr
) == SVR_P4080
&& SVR_MAJ(svr
) < 3) ||
393 (SVR_SOC_VER(svr
) != SVR_P4080
&& SVR_MAJ(svr
) < 2);
396 if (enable_cpu_a011_workaround
) {
398 mtspr(L1CSR2
, (mfspr(L1CSR2
) | L1CSR2_DCWS
));
403 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
404 spin
= getenv("spin_table_compat");
405 if (spin
&& (*spin
== 'n'))
406 spin_table_compat
= 0;
408 spin_table_compat
= 1;
413 #if defined(CONFIG_L2_CACHE)
414 volatile uint cache_ctl
;
418 ver
= SVR_SOC_VER(svr
);
421 cache_ctl
= l2cache
->l2ctl
;
423 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
424 if (cache_ctl
& MPC85xx_L2CTL_L2E
) {
425 /* Clear L2 SRAM memory-mapped base address */
426 out_be32(&l2cache
->l2srbar0
, 0x0);
427 out_be32(&l2cache
->l2srbar1
, 0x0);
429 /* set MBECCDIS=0, SBECCDIS=0 */
430 clrbits_be32(&l2cache
->l2errdis
,
431 (MPC85xx_L2ERRDIS_MBECC
|
432 MPC85xx_L2ERRDIS_SBECC
));
434 /* set L2E=0, L2SRAM=0 */
435 clrbits_be32(&l2cache
->l2ctl
,
437 MPC85xx_L2CTL_L2SRAM_ENTIRE
));
441 l2siz_field
= (cache_ctl
>> 28) & 0x3;
443 switch (l2siz_field
) {
445 printf(" unknown size (0x%08x)\n", cache_ctl
);
449 if (ver
== SVR_8540
|| ver
== SVR_8560
||
450 ver
== SVR_8541
|| ver
== SVR_8555
) {
452 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
453 cache_ctl
= 0xc4000000;
456 cache_ctl
= 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
460 if (ver
== SVR_8540
|| ver
== SVR_8560
||
461 ver
== SVR_8541
|| ver
== SVR_8555
) {
463 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
464 cache_ctl
= 0xc8000000;
467 /* set L2E=1, L2I=1, & L2SRAM=0 */
468 cache_ctl
= 0xc0000000;
473 /* set L2E=1, L2I=1, & L2SRAM=0 */
474 cache_ctl
= 0xc0000000;
478 if (l2cache
->l2ctl
& MPC85xx_L2CTL_L2E
) {
479 puts("already enabled");
480 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
481 u32 l2srbar
= l2cache
->l2srbar0
;
482 if (l2cache
->l2ctl
& MPC85xx_L2CTL_L2SRAM_ENTIRE
483 && l2srbar
>= CONFIG_SYS_FLASH_BASE
) {
484 l2srbar
= CONFIG_SYS_INIT_L2_ADDR
;
485 l2cache
->l2srbar0
= l2srbar
;
486 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR
);
488 #endif /* CONFIG_SYS_INIT_L2_ADDR */
492 l2cache
->l2ctl
= cache_ctl
; /* invalidate & enable */
496 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
497 if (SVR_SOC_VER(svr
) == SVR_P2040
) {
502 u32 l2cfg0
= mfspr(SPRN_L2CFG0
);
504 /* invalidate the L2 cache */
505 mtspr(SPRN_L2CSR0
, (L2CSR0_L2FI
|L2CSR0_L2LFC
));
506 while (mfspr(SPRN_L2CSR0
) & (L2CSR0_L2FI
|L2CSR0_L2LFC
))
509 #ifdef CONFIG_SYS_CACHE_STASHING
510 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
511 mtspr(SPRN_L2CSR1
, (32 + 1));
514 /* enable the cache */
515 mtspr(SPRN_L2CSR0
, CONFIG_SYS_INIT_L2CSR0
);
517 if (CONFIG_SYS_INIT_L2CSR0
& L2CSR0_L2E
) {
518 while (!(mfspr(SPRN_L2CSR0
) & L2CSR0_L2E
))
520 printf("%d KB enabled\n", (l2cfg0
& 0x3fff) * 64);
524 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
525 if (l2cache
->l2csr0
& L2CSR0_L2E
)
526 printf("%d KB enabled\n", (l2cache
->l2cfg0
& 0x3fff) * 64);
535 /* needs to be in ram since code uses global static vars */
538 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
539 if (IS_SVR_REV(svr
, 1, 0)) {
541 __be32
*p
= (void __iomem
*)CONFIG_SYS_DCSRBAR
+ 0xb004c;
543 for (i
= 0; i
< 12; i
++) {
544 p
+= i
+ (i
> 5 ? 11 : 0);
547 p
= (void __iomem
*)CONFIG_SYS_DCSRBAR
+ 0xb0108;
552 #ifdef CONFIG_SYS_SRIO
554 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
555 char *s
= getenv("bootmaster");
557 if (!strcmp(s
, "SRIO1")) {
559 srio_boot_master_release_slave(1);
561 if (!strcmp(s
, "SRIO2")) {
563 srio_boot_master_release_slave(2);
569 #if defined(CONFIG_MP)
573 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
575 if (SVR_MAJ(svr
) < 3) {
577 p
= (void *)CONFIG_SYS_DCSRBAR
+ 0x20520;
578 setbits_be32(p
, 1 << (31 - 14));
583 #ifdef CONFIG_SYS_LBC_LCRR
585 * Modify the CLKDIV field of LCRR register to improve the writing
586 * speed for NOR flash.
588 clrsetbits_be32(&lbc
->lcrr
, LCRR_CLKDIV
, CONFIG_SYS_LBC_LCRR
);
589 __raw_readl(&lbc
->lcrr
);
591 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
596 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
598 ccsr_usb_phy_t
*usb_phy1
=
599 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
;
600 out_be32(&usb_phy1
->usb_enable_override
,
601 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE
);
604 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
606 ccsr_usb_phy_t
*usb_phy2
=
607 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
;
608 out_be32(&usb_phy2
->usb_enable_override
,
609 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE
);
613 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
614 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
615 * multi-bit ECC errors which has impact on performance, so software
616 * should disable all ECC reporting from USB1 and USB2.
618 if (IS_SVR_REV(get_svr(), 1, 0)) {
619 struct dcsr_dcfg_regs
*dcfg
= (struct dcsr_dcfg_regs
*)
620 (CONFIG_SYS_DCSRBAR
+ CONFIG_SYS_DCSR_DCFG_OFFSET
);
621 setbits_be32(&dcfg
->ecccr1
,
622 (DCSR_DCFG_ECC_DISABLE_USB1
|
623 DCSR_DCFG_ECC_DISABLE_USB2
));
627 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
628 ccsr_usb_phy_t
*usb_phy
=
629 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
;
630 setbits_be32(&usb_phy
->pllprg
[1],
631 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN
|
632 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN
|
633 CONFIG_SYS_FSL_USB_PLLPRG2_MFI
|
634 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN
);
635 setbits_be32(&usb_phy
->port1
.ctrl
,
636 CONFIG_SYS_FSL_USB_CTRL_PHY_EN
);
637 setbits_be32(&usb_phy
->port1
.drvvbuscfg
,
638 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN
);
639 setbits_be32(&usb_phy
->port1
.pwrfltcfg
,
640 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN
);
641 setbits_be32(&usb_phy
->port2
.ctrl
,
642 CONFIG_SYS_FSL_USB_CTRL_PHY_EN
);
643 setbits_be32(&usb_phy
->port2
.drvvbuscfg
,
644 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN
);
645 setbits_be32(&usb_phy
->port2
.pwrfltcfg
,
646 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN
);
649 #ifdef CONFIG_FMAN_ENET
653 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
655 * For P1022/1013 Rev1.0 silicon, after power on SATA host
656 * controller is configured in legacy mode instead of the
657 * expected enterprise mode. Software needs to clear bit[28]
658 * of HControl register to change to enterprise mode from
659 * legacy mode. We assume that the controller is offline.
661 if (IS_SVR_REV(svr
, 1, 0) &&
662 ((SVR_SOC_VER(svr
) == SVR_P1022
) ||
663 (SVR_SOC_VER(svr
) == SVR_P1013
))) {
666 /* first SATA controller */
667 reg
= (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR
;
668 clrbits_le32(®
->hcontrol
, HCONTROL_ENTERPRISE_EN
);
670 /* second SATA controller */
671 reg
= (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR
;
672 clrbits_le32(®
->hcontrol
, HCONTROL_ENTERPRISE_EN
);
680 extern void setup_ivors(void);
682 void arch_preboot_os(void)
687 * We are changing interrupt offsets and are about to boot the OS so
688 * we need to make sure we disable all async interrupts. EE is already
689 * disabled by the time we get called.
692 msr
&= ~(MSR_ME
|MSR_CE
);
698 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
699 int sata_initialize(void)
701 if (is_serdes_configured(SATA1
) || is_serdes_configured(SATA2
))
702 return __sata_initialize();
708 void cpu_secondary_init_r(void)
711 uint qe_base
= CONFIG_SYS_IMMR
+ 0x00080000; /* QE immr base */
712 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
714 size_t fw_length
= CONFIG_SYS_QE_FMAN_FW_LENGTH
;
716 /* load QE firmware from NAND flash to DDR first */
717 ret
= nand_read(&nand_info
[0], (loff_t
)CONFIG_SYS_QE_FMAN_FW_IN_NAND
,
718 &fw_length
, (u_char
*)CONFIG_SYS_QE_FMAN_FW_ADDR
);
720 if (ret
&& ret
== -EUCLEAN
) {
721 printf ("NAND read for QE firmware at offset %x failed %d\n",
722 CONFIG_SYS_QE_FMAN_FW_IN_NAND
, ret
);