arch/powerpc/cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <asm/processor.h>
  32 #include <ioports.h>
  33 #include <sata.h>
  34 #include <fm_eth.h>
  35 #include <asm/io.h>
  36 #include <asm/cache.h>
  37 #include <asm/mmu.h>
  38 #include <asm/fsl_law.h>
  39 #include <asm/fsl_serdes.h>
  40 #include "mp.h"
  41 #ifdef CONFIG_SYS_QE_FW_IN_NAND
  42 #include <nand.h>
  43 #include <errno.h>
  44 #endif
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 extern void srio_init(void);
  49
  50 #ifdef CONFIG_QE
  51 extern qe_iop_conf_t qe_iop_conf_tab[];
  52 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  53                                 int open_drain, int assign);
  54 extern void qe_init(uint qe_base);
  55 extern void qe_reset(void);
  56
  57 static void config_qe_ioports(void)
  58 {
  59         u8      port, pin;
  60         int     dir, open_drain, assign;
  61         int     i;
  62
  63         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  64                 port            = qe_iop_conf_tab[i].port;
  65                 pin             = qe_iop_conf_tab[i].pin;
  66                 dir             = qe_iop_conf_tab[i].dir;
  67                 open_drain      = qe_iop_conf_tab[i].open_drain;
  68                 assign          = qe_iop_conf_tab[i].assign;
  69                 qe_config_iopin(port, pin, dir, open_drain, assign);
  70         }
  71 }
  72 #endif
  73
  74 #ifdef CONFIG_CPM2
  75 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  76 {
  77         int portnum;
  78
  79         for (portnum = 0; portnum < 4; portnum++) {
  80                 uint pmsk = 0,
  81                      ppar = 0,
  82                      psor = 0,
  83                      pdir = 0,
  84                      podr = 0,
  85                      pdat = 0;
  86                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  87                 iop_conf_t *eiopc = iopc + 32;
  88                 uint msk = 1;
  89
  90                 /*
  91                  * NOTE:
  92                  * index 0 refers to pin 31,
  93                  * index 31 refers to pin 0
  94                  */
  95                 while (iopc < eiopc) {
  96                         if (iopc->conf) {
  97                                 pmsk |= msk;
  98                                 if (iopc->ppar)
  99                                         ppar |= msk;
 100                                 if (iopc->psor)
 101                                         psor |= msk;
 102                                 if (iopc->pdir)
 103                                         pdir |= msk;
 104                                 if (iopc->podr)
 105                                         podr |= msk;
 106                                 if (iopc->pdat)
 107                                         pdat |= msk;
 108                         }
 109
 110                         msk <<= 1;
 111                         iopc++;
 112                 }
 113
 114                 if (pmsk != 0) {
 115                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 116                         uint tpmsk = ~pmsk;
 117
 118                         /*
 119                          * the (somewhat confused) paragraph at the
 120                          * bottom of page 35-5 warns that there might
 121                          * be "unknown behaviour" when programming
 122                          * PSORx and PDIRx, if PPARx = 1, so I
 123                          * decided this meant I had to disable the
 124                          * dedicated function first, and enable it
 125                          * last.
 126                          */
 127                         iop->ppar &= tpmsk;
 128                         iop->psor = (iop->psor & tpmsk) | psor;
 129                         iop->podr = (iop->podr & tpmsk) | podr;
 130                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 131                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 132                         iop->ppar |= ppar;
 133                 }
 134         }
 135 }
 136 #endif
 137
 138 #ifdef CONFIG_SYS_FSL_CPC
 139 static void enable_cpc(void)
 140 {
 141         int i;
 142         u32 size = 0;
 143
 144         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 145
 146         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 147                 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
 148                 size += CPC_CFG0_SZ_K(cpccfg0);
 149 #ifdef CONFIG_RAMBOOT_PBL
 150                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 151                         /* find and disable LAW of SRAM */
 152                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 153
 154                         if (law.index == -1) {
 155                                 printf("\nFatal error happened\n");
 156                                 return;
 157                         }
 158                         disable_law(law.index);
 159
 160                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 161                         out_be32(&cpc->cpccsr0, 0);
 162                         out_be32(&cpc->cpcsrcr0, 0);
 163                 }
 164 #endif
 165
 166 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 167                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 168 #endif
 169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 170                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 171 #endif
 172
 173                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 174                 /* Read back to sync write */
 175                 in_be32(&cpc->cpccsr0);
 176
 177         }
 178
 179         printf("Corenet Platform Cache: %d KB enabled\n", size);
 180 }
 181
 182 void invalidate_cpc(void)
 183 {
 184         int i;
 185         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 186
 187         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 188                 /* skip CPC when it used as all SRAM */
 189                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 190                         continue;
 191                 /* Flash invalidate the CPC and clear all the locks */
 192                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 193                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 194                         ;
 195         }
 196 }
 197 #else
 198 #define enable_cpc()
 199 #define invalidate_cpc()
 200 #endif /* CONFIG_SYS_FSL_CPC */
 201
 202 /*
 203  * Breathe some life into the CPU...
 204  *
 205  * Set up the memory map
 206  * initialize a bunch of registers
 207  */
 208
 209 #ifdef CONFIG_FSL_CORENET
 210 static void corenet_tb_init(void)
 211 {
 212         volatile ccsr_rcpm_t *rcpm =
 213                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 214         volatile ccsr_pic_t *pic =
 215                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 216         u32 whoami = in_be32(&pic->whoami);
 217
 218         /* Enable the timebase register for this core */
 219         out_be32(&rcpm->ctbenrl, (1 << whoami));
 220 }
 221 #endif
 222
 223 void cpu_init_f (void)
 224 {
 225         extern void m8560_cpm_reset (void);
 226 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 227         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 228 #endif
 229 #if defined(CONFIG_SECURE_BOOT)
 230         struct law_entry law;
 231 #endif
 232 #ifdef CONFIG_MPC8548
 233         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 234         uint svr = get_svr();
 235
 236         /*
 237          * CPU2 errata workaround: A core hang possible while executing
 238          * a msync instruction and a snoopable transaction from an I/O
 239          * master tagged to make quick forward progress is present.
 240          * Fixed in silicon rev 2.1.
 241          */
 242         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 243                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 244 #endif
 245
 246         disable_tlb(14);
 247         disable_tlb(15);
 248
 249 #if defined(CONFIG_SECURE_BOOT)
 250         /* Disable the LAW created for NOR flash by the PBI commands */
 251         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 252         if (law.index != -1)
 253                 disable_law(law.index);
 254 #endif
 255
 256 #ifdef CONFIG_CPM2
 257         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 258 #endif
 259
 260        init_early_memctl_regs();
 261
 262 #if defined(CONFIG_CPM2)
 263         m8560_cpm_reset();
 264 #endif
 265 #ifdef CONFIG_QE
 266         /* Config QE ioports */
 267         config_qe_ioports();
 268 #endif
 269 #if defined(CONFIG_FSL_DMA)
 270         dma_init();
 271 #endif
 272 #ifdef CONFIG_FSL_CORENET
 273         corenet_tb_init();
 274 #endif
 275         init_used_tlb_cams();
 276
 277         /* Invalidate the CPC before DDR gets enabled */
 278         invalidate_cpc();
 279
 280  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 281         /* set DCSRCR so that DCSR space is 1G */
 282         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 283         in_be32(&gur->dcsrcr);
 284 #endif
 285
 286 }
 287
 288 /* Implement a dummy function for those platforms w/o SERDES */
 289 static void __fsl_serdes__init(void)
 290 {
 291         return ;
 292 }
 293 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 294
 295 /*
 296  * Initialize L2 as cache.
 297  *
 298  * The newer 8548, etc, parts have twice as much cache, but
 299  * use the same bit-encoding as the older 8555, etc, parts.
 300  *
 301  */
 302 int cpu_init_r(void)
 303 {
 304 #ifdef CONFIG_SYS_LBC_LCRR
 305         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 306 #endif
 307
 308 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
 309         flush_dcache();
 310         mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 311         sync();
 312 #endif
 313
 314         puts ("L2:    ");
 315
 316 #if defined(CONFIG_L2_CACHE)
 317         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 318         volatile uint cache_ctl;
 319         uint svr, ver;
 320         uint l2srbar;
 321         u32 l2siz_field;
 322
 323         svr = get_svr();
 324         ver = SVR_SOC_VER(svr);
 325
 326         asm("msync;isync");
 327         cache_ctl = l2cache->l2ctl;
 328
 329 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 330         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 331                 /* Clear L2 SRAM memory-mapped base address */
 332                 out_be32(&l2cache->l2srbar0, 0x0);
 333                 out_be32(&l2cache->l2srbar1, 0x0);
 334
 335                 /* set MBECCDIS=0, SBECCDIS=0 */
 336                 clrbits_be32(&l2cache->l2errdis,
 337                                 (MPC85xx_L2ERRDIS_MBECC |
 338                                  MPC85xx_L2ERRDIS_SBECC));
 339
 340                 /* set L2E=0, L2SRAM=0 */
 341                 clrbits_be32(&l2cache->l2ctl,
 342                                 (MPC85xx_L2CTL_L2E |
 343                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 344         }
 345 #endif
 346
 347         l2siz_field = (cache_ctl >> 28) & 0x3;
 348
 349         switch (l2siz_field) {
 350         case 0x0:
 351                 printf(" unknown size (0x%08x)\n", cache_ctl);
 352                 return -1;
 353                 break;
 354         case 0x1:
 355                 if (ver == SVR_8540 || ver == SVR_8560   ||
 356                     ver == SVR_8541 || ver == SVR_8541_E ||
 357                     ver == SVR_8555 || ver == SVR_8555_E) {
 358                         puts("128 KB ");
 359                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
 360                         cache_ctl = 0xc4000000;
 361                 } else {
 362                         puts("256 KB ");
 363                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 364                 }
 365                 break;
 366         case 0x2:
 367                 if (ver == SVR_8540 || ver == SVR_8560   ||
 368                     ver == SVR_8541 || ver == SVR_8541_E ||
 369                     ver == SVR_8555 || ver == SVR_8555_E) {
 370                         puts("256 KB ");
 371                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 372                         cache_ctl = 0xc8000000;
 373                 } else {
 374                         puts ("512 KB ");
 375                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 376                         cache_ctl = 0xc0000000;
 377                 }
 378                 break;
 379         case 0x3:
 380                 puts("1024 KB ");
 381                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 382                 cache_ctl = 0xc0000000;
 383                 break;
 384         }
 385
 386         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 387                 puts("already enabled");
 388                 l2srbar = l2cache->l2srbar0;
 389 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 390                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 391                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 392                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 393                         l2cache->l2srbar0 = l2srbar;
 394                         printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 395                 }
 396 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 397                 puts("\n");
 398         } else {
 399                 asm("msync;isync");
 400                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 401                 asm("msync;isync");
 402                 puts("enabled\n");
 403         }
 404 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 405         if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
 406             (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
 407                 puts("N/A\n");
 408                 goto skip_l2;
 409         }
 410
 411         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 412
 413         /* invalidate the L2 cache */
 414         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 415         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 416                 ;
 417
 418 #ifdef CONFIG_SYS_CACHE_STASHING
 419         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 420         mtspr(SPRN_L2CSR1, (32 + 1));
 421 #endif
 422
 423         /* enable the cache */
 424         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 425
 426         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 427                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 428                         ;
 429                 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
 430         }
 431
 432 skip_l2:
 433 #else
 434         puts("disabled\n");
 435 #endif
 436
 437         enable_cpc();
 438
 439         /* needs to be in ram since code uses global static vars */
 440         fsl_serdes_init();
 441
 442 #ifdef CONFIG_SYS_SRIO
 443         srio_init();
 444 #endif
 445
 446 #if defined(CONFIG_MP)
 447         setup_mp();
 448 #endif
 449
 450 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
 451         {
 452                 void *p;
 453                 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 454                 setbits_be32(p, 1 << (31 - 14));
 455         }
 456 #endif
 457
 458 #ifdef CONFIG_SYS_LBC_LCRR
 459         /*
 460          * Modify the CLKDIV field of LCRR register to improve the writing
 461          * speed for NOR flash.
 462          */
 463         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 464         __raw_readl(&lbc->lcrr);
 465         isync();
 466 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 467         udelay(100);
 468 #endif
 469 #endif
 470
 471 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 472         {
 473                 ccsr_usb_phy_t *usb_phy1 =
 474                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 475                 out_be32(&usb_phy1->usb_enable_override,
 476                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 477         }
 478 #endif
 479 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 480         {
 481                 ccsr_usb_phy_t *usb_phy2 =
 482                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 483                 out_be32(&usb_phy2->usb_enable_override,
 484                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 485         }
 486 #endif
 487
 488 #ifdef CONFIG_FMAN_ENET
 489         fman_enet_init();
 490 #endif
 491
 492         return 0;
 493 }
 494
 495 extern void setup_ivors(void);
 496
 497 void arch_preboot_os(void)
 498 {
 499         u32 msr;
 500
 501         /*
 502          * We are changing interrupt offsets and are about to boot the OS so
 503          * we need to make sure we disable all async interrupts. EE is already
 504          * disabled by the time we get called.
 505          */
 506         msr = mfmsr();
 507         msr &= ~(MSR_ME|MSR_CE|MSR_DE);
 508         mtmsr(msr);
 509
 510         setup_ivors();
 511 }
 512
 513 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
 514 int sata_initialize(void)
 515 {
 516         if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
 517                 return __sata_initialize();
 518
 519         return 1;
 520 }
 521 #endif
 522
 523 void cpu_secondary_init_r(void)
 524 {
 525 #ifdef CONFIG_QE
 526         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 527 #ifdef CONFIG_SYS_QE_FW_IN_NAND
 528         int ret;
 529         size_t fw_length = CONFIG_SYS_QE_FW_LENGTH;
 530
 531         /* load QE firmware from NAND flash to DDR first */
 532         ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND,
 533                         &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR);
 534
 535         if (ret && ret == -EUCLEAN) {
 536                 printf ("NAND read for QE firmware at offset %x failed %d\n",
 537                                 CONFIG_SYS_QE_FW_IN_NAND, ret);
 538         }
 539 #endif
 540         qe_init(qe_base);
 541         qe_reset();
 542 #endif
 543 }