arch/powerpc/cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <asm/processor.h>
  32 #include <ioports.h>
  33 #include <sata.h>
  34 #include <fm_eth.h>
  35 #include <asm/io.h>
  36 #include <asm/cache.h>
  37 #include <asm/mmu.h>
  38 #include <asm/fsl_law.h>
  39 #include <asm/fsl_serdes.h>
  40 #include <asm/fsl_srio.h>
  41 #include <hwconfig.h>
  42 #include <linux/compiler.h>
  43 #include "mp.h"
  44 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  45 #include <nand.h>
  46 #include <errno.h>
  47 #endif
  48
  49 #include "../../../../drivers/block/fsl_sata.h"
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 #ifdef CONFIG_QE
  54 extern qe_iop_conf_t qe_iop_conf_tab[];
  55 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  56                                 int open_drain, int assign);
  57 extern void qe_init(uint qe_base);
  58 extern void qe_reset(void);
  59
  60 static void config_qe_ioports(void)
  61 {
  62         u8      port, pin;
  63         int     dir, open_drain, assign;
  64         int     i;
  65
  66         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  67                 port            = qe_iop_conf_tab[i].port;
  68                 pin             = qe_iop_conf_tab[i].pin;
  69                 dir             = qe_iop_conf_tab[i].dir;
  70                 open_drain      = qe_iop_conf_tab[i].open_drain;
  71                 assign          = qe_iop_conf_tab[i].assign;
  72                 qe_config_iopin(port, pin, dir, open_drain, assign);
  73         }
  74 }
  75 #endif
  76
  77 #ifdef CONFIG_CPM2
  78 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  79 {
  80         int portnum;
  81
  82         for (portnum = 0; portnum < 4; portnum++) {
  83                 uint pmsk = 0,
  84                      ppar = 0,
  85                      psor = 0,
  86                      pdir = 0,
  87                      podr = 0,
  88                      pdat = 0;
  89                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  90                 iop_conf_t *eiopc = iopc + 32;
  91                 uint msk = 1;
  92
  93                 /*
  94                  * NOTE:
  95                  * index 0 refers to pin 31,
  96                  * index 31 refers to pin 0
  97                  */
  98                 while (iopc < eiopc) {
  99                         if (iopc->conf) {
 100                                 pmsk |= msk;
 101                                 if (iopc->ppar)
 102                                         ppar |= msk;
 103                                 if (iopc->psor)
 104                                         psor |= msk;
 105                                 if (iopc->pdir)
 106                                         pdir |= msk;
 107                                 if (iopc->podr)
 108                                         podr |= msk;
 109                                 if (iopc->pdat)
 110                                         pdat |= msk;
 111                         }
 112
 113                         msk <<= 1;
 114                         iopc++;
 115                 }
 116
 117                 if (pmsk != 0) {
 118                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 119                         uint tpmsk = ~pmsk;
 120
 121                         /*
 122                          * the (somewhat confused) paragraph at the
 123                          * bottom of page 35-5 warns that there might
 124                          * be "unknown behaviour" when programming
 125                          * PSORx and PDIRx, if PPARx = 1, so I
 126                          * decided this meant I had to disable the
 127                          * dedicated function first, and enable it
 128                          * last.
 129                          */
 130                         iop->ppar &= tpmsk;
 131                         iop->psor = (iop->psor & tpmsk) | psor;
 132                         iop->podr = (iop->podr & tpmsk) | podr;
 133                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 134                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 135                         iop->ppar |= ppar;
 136                 }
 137         }
 138 }
 139 #endif
 140
 141 #ifdef CONFIG_SYS_FSL_CPC
 142 static void enable_cpc(void)
 143 {
 144         int i;
 145         u32 size = 0;
 146
 147         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 148
 149         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 150                 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
 151                 size += CPC_CFG0_SZ_K(cpccfg0);
 152 #ifdef CONFIG_RAMBOOT_PBL
 153                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 154                         /* find and disable LAW of SRAM */
 155                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 156
 157                         if (law.index == -1) {
 158                                 printf("\nFatal error happened\n");
 159                                 return;
 160                         }
 161                         disable_law(law.index);
 162
 163                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 164                         out_be32(&cpc->cpccsr0, 0);
 165                         out_be32(&cpc->cpcsrcr0, 0);
 166                 }
 167 #endif
 168
 169 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 170                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 171 #endif
 172 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 173                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 174 #endif
 175
 176                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 177                 /* Read back to sync write */
 178                 in_be32(&cpc->cpccsr0);
 179
 180         }
 181
 182         printf("Corenet Platform Cache: %d KB enabled\n", size);
 183 }
 184
 185 static void invalidate_cpc(void)
 186 {
 187         int i;
 188         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 189
 190         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 191                 /* skip CPC when it used as all SRAM */
 192                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 193                         continue;
 194                 /* Flash invalidate the CPC and clear all the locks */
 195                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 196                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 197                         ;
 198         }
 199 }
 200 #else
 201 #define enable_cpc()
 202 #define invalidate_cpc()
 203 #endif /* CONFIG_SYS_FSL_CPC */
 204
 205 /*
 206  * Breathe some life into the CPU...
 207  *
 208  * Set up the memory map
 209  * initialize a bunch of registers
 210  */
 211
 212 #ifdef CONFIG_FSL_CORENET
 213 static void corenet_tb_init(void)
 214 {
 215         volatile ccsr_rcpm_t *rcpm =
 216                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 217         volatile ccsr_pic_t *pic =
 218                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 219         u32 whoami = in_be32(&pic->whoami);
 220
 221         /* Enable the timebase register for this core */
 222         out_be32(&rcpm->ctbenrl, (1 << whoami));
 223 }
 224 #endif
 225
 226 void cpu_init_f (void)
 227 {
 228         extern void m8560_cpm_reset (void);
 229 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 230         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 231 #endif
 232 #if defined(CONFIG_SECURE_BOOT)
 233         struct law_entry law;
 234 #endif
 235 #ifdef CONFIG_MPC8548
 236         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 237         uint svr = get_svr();
 238
 239         /*
 240          * CPU2 errata workaround: A core hang possible while executing
 241          * a msync instruction and a snoopable transaction from an I/O
 242          * master tagged to make quick forward progress is present.
 243          * Fixed in silicon rev 2.1.
 244          */
 245         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 246                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 247 #endif
 248
 249         disable_tlb(14);
 250         disable_tlb(15);
 251
 252 #if defined(CONFIG_SECURE_BOOT)
 253         /* Disable the LAW created for NOR flash by the PBI commands */
 254         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 255         if (law.index != -1)
 256                 disable_law(law.index);
 257 #endif
 258
 259 #ifdef CONFIG_CPM2
 260         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 261 #endif
 262
 263        init_early_memctl_regs();
 264
 265 #if defined(CONFIG_CPM2)
 266         m8560_cpm_reset();
 267 #endif
 268 #ifdef CONFIG_QE
 269         /* Config QE ioports */
 270         config_qe_ioports();
 271 #endif
 272 #if defined(CONFIG_FSL_DMA)
 273         dma_init();
 274 #endif
 275 #ifdef CONFIG_FSL_CORENET
 276         corenet_tb_init();
 277 #endif
 278         init_used_tlb_cams();
 279
 280         /* Invalidate the CPC before DDR gets enabled */
 281         invalidate_cpc();
 282
 283  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 284         /* set DCSRCR so that DCSR space is 1G */
 285         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 286         in_be32(&gur->dcsrcr);
 287 #endif
 288
 289 }
 290
 291 /* Implement a dummy function for those platforms w/o SERDES */
 292 static void __fsl_serdes__init(void)
 293 {
 294         return ;
 295 }
 296 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 297
 298 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 299 int enable_cluster_l2(void)
 300 {
 301         int i = 0;
 302         u32 cluster;
 303         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 304         struct ccsr_cluster_l2 __iomem *l2cache;
 305
 306         cluster = in_be32(&gur->tp_cluster[i].lower);
 307         if (cluster & TP_CLUSTER_EOC)
 308                 return 0;
 309
 310         /* The first cache has already been set up, so skip it */
 311         i++;
 312
 313         /* Look through the remaining clusters, and set up their caches */
 314         do {
 315                 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 316                 cluster = in_be32(&gur->tp_cluster[i].lower);
 317
 318                 /* set stash ID to (cluster) * 2 + 32 + 1 */
 319                 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 320
 321                 printf("enable l2 for cluster %d %p\n", i, l2cache);
 322
 323                 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
 324                 while ((in_be32(&l2cache->l2csr0) &
 325                         (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 326                         ;
 327                 out_be32(&l2cache->l2csr0, L2CSR0_L2E);
 328                 i++;
 329         } while (!(cluster & TP_CLUSTER_EOC));
 330
 331         return 0;
 332 }
 333 #endif
 334
 335 /*
 336  * Initialize L2 as cache.
 337  *
 338  * The newer 8548, etc, parts have twice as much cache, but
 339  * use the same bit-encoding as the older 8555, etc, parts.
 340  *
 341  */
 342 int cpu_init_r(void)
 343 {
 344         __maybe_unused u32 svr = get_svr();
 345 #ifdef CONFIG_SYS_LBC_LCRR
 346         fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 347 #endif
 348 #ifdef CONFIG_L2_CACHE
 349         ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
 350 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 351         struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 352 #endif
 353
 354 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 355         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 356         /*
 357          * CPU22 and NMG_CPU_A011 share the same workaround.
 358          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 359          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 360          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
 361          * fixed in 2.0. NMG_CPU_A011 is activated by default and can
 362          * be disabled by hwconfig with syntax:
 363          *
 364          * fsl_cpu_a011:disable
 365          */
 366         extern int enable_cpu_a011_workaround;
 367 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
 368         enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
 369 #else
 370         char buffer[HWCONFIG_BUFFER_SIZE];
 371         char *buf = NULL;
 372         int n, res;
 373
 374         n = getenv_f("hwconfig", buffer, sizeof(buffer));
 375         if (n > 0)
 376                 buf = buffer;
 377
 378         res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
 379         if (res > 0)
 380                 enable_cpu_a011_workaround = 0;
 381         else {
 382                 if (n >= HWCONFIG_BUFFER_SIZE) {
 383                         printf("fsl_cpu_a011 was not found. hwconfig variable "
 384                                 "may be too long\n");
 385                 }
 386                 enable_cpu_a011_workaround =
 387                         (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
 388                         (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
 389         }
 390 #endif
 391         if (enable_cpu_a011_workaround) {
 392                 flush_dcache();
 393                 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 394                 sync();
 395         }
 396 #endif
 397
 398         puts ("L2:    ");
 399
 400 #if defined(CONFIG_L2_CACHE)
 401         volatile uint cache_ctl;
 402         uint ver;
 403         u32 l2siz_field;
 404
 405         ver = SVR_SOC_VER(svr);
 406
 407         asm("msync;isync");
 408         cache_ctl = l2cache->l2ctl;
 409
 410 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 411         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 412                 /* Clear L2 SRAM memory-mapped base address */
 413                 out_be32(&l2cache->l2srbar0, 0x0);
 414                 out_be32(&l2cache->l2srbar1, 0x0);
 415
 416                 /* set MBECCDIS=0, SBECCDIS=0 */
 417                 clrbits_be32(&l2cache->l2errdis,
 418                                 (MPC85xx_L2ERRDIS_MBECC |
 419                                  MPC85xx_L2ERRDIS_SBECC));
 420
 421                 /* set L2E=0, L2SRAM=0 */
 422                 clrbits_be32(&l2cache->l2ctl,
 423                                 (MPC85xx_L2CTL_L2E |
 424                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 425         }
 426 #endif
 427
 428         l2siz_field = (cache_ctl >> 28) & 0x3;
 429
 430         switch (l2siz_field) {
 431         case 0x0:
 432                 printf(" unknown size (0x%08x)\n", cache_ctl);
 433                 return -1;
 434                 break;
 435         case 0x1:
 436                 if (ver == SVR_8540 || ver == SVR_8560   ||
 437                     ver == SVR_8541 || ver == SVR_8555) {
 438                         puts("128 KB ");
 439                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
 440                         cache_ctl = 0xc4000000;
 441                 } else {
 442                         puts("256 KB ");
 443                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 444                 }
 445                 break;
 446         case 0x2:
 447                 if (ver == SVR_8540 || ver == SVR_8560   ||
 448                     ver == SVR_8541 || ver == SVR_8555) {
 449                         puts("256 KB ");
 450                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
 451                         cache_ctl = 0xc8000000;
 452                 } else {
 453                         puts ("512 KB ");
 454                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 455                         cache_ctl = 0xc0000000;
 456                 }
 457                 break;
 458         case 0x3:
 459                 puts("1024 KB ");
 460                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 461                 cache_ctl = 0xc0000000;
 462                 break;
 463         }
 464
 465         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 466                 puts("already enabled");
 467 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 468                 u32 l2srbar = l2cache->l2srbar0;
 469                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 470                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 471                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 472                         l2cache->l2srbar0 = l2srbar;
 473                         printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 474                 }
 475 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 476                 puts("\n");
 477         } else {
 478                 asm("msync;isync");
 479                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 480                 asm("msync;isync");
 481                 puts("enabled\n");
 482         }
 483 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 484         if (SVR_SOC_VER(svr) == SVR_P2040) {
 485                 puts("N/A\n");
 486                 goto skip_l2;
 487         }
 488
 489         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 490
 491         /* invalidate the L2 cache */
 492         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 493         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 494                 ;
 495
 496 #ifdef CONFIG_SYS_CACHE_STASHING
 497         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 498         mtspr(SPRN_L2CSR1, (32 + 1));
 499 #endif
 500
 501         /* enable the cache */
 502         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 503
 504         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 505                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 506                         ;
 507                 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
 508         }
 509
 510 skip_l2:
 511 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 512         if (l2cache->l2csr0 & L2CSR0_L2E)
 513                 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
 514
 515         enable_cluster_l2();
 516 #else
 517         puts("disabled\n");
 518 #endif
 519
 520         enable_cpc();
 521
 522         /* needs to be in ram since code uses global static vars */
 523         fsl_serdes_init();
 524
 525 #ifdef CONFIG_SYS_SRIO
 526         srio_init();
 527 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 528         char *s = getenv("bootmaster");
 529         if (s) {
 530                 if (!strcmp(s, "SRIO1")) {
 531                         srio_boot_master(1);
 532                         srio_boot_master_release_slave(1);
 533                 }
 534                 if (!strcmp(s, "SRIO2")) {
 535                         srio_boot_master(2);
 536                         srio_boot_master_release_slave(2);
 537                 }
 538         }
 539 #endif
 540 #endif
 541
 542 #if defined(CONFIG_MP)
 543         setup_mp();
 544 #endif
 545
 546 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 547         {
 548                 if (SVR_MAJ(svr) < 3) {
 549                         void *p;
 550                         p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 551                         setbits_be32(p, 1 << (31 - 14));
 552                 }
 553         }
 554 #endif
 555
 556 #ifdef CONFIG_SYS_LBC_LCRR
 557         /*
 558          * Modify the CLKDIV field of LCRR register to improve the writing
 559          * speed for NOR flash.
 560          */
 561         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 562         __raw_readl(&lbc->lcrr);
 563         isync();
 564 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 565         udelay(100);
 566 #endif
 567 #endif
 568
 569 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 570         {
 571                 ccsr_usb_phy_t *usb_phy1 =
 572                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 573                 out_be32(&usb_phy1->usb_enable_override,
 574                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 575         }
 576 #endif
 577 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 578         {
 579                 ccsr_usb_phy_t *usb_phy2 =
 580                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 581                 out_be32(&usb_phy2->usb_enable_override,
 582                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 583         }
 584 #endif
 585
 586 #ifdef CONFIG_FMAN_ENET
 587         fman_enet_init();
 588 #endif
 589
 590 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 591         /*
 592          * For P1022/1013 Rev1.0 silicon, after power on SATA host
 593          * controller is configured in legacy mode instead of the
 594          * expected enterprise mode. Software needs to clear bit[28]
 595          * of HControl register to change to enterprise mode from
 596          * legacy mode.  We assume that the controller is offline.
 597          */
 598         if (IS_SVR_REV(svr, 1, 0) &&
 599             ((SVR_SOC_VER(svr) == SVR_P1022) ||
 600              (SVR_SOC_VER(svr) == SVR_P1013))) {
 601                 fsl_sata_reg_t *reg;
 602
 603                 /* first SATA controller */
 604                 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
 605                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 606
 607                 /* second SATA controller */
 608                 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
 609                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 610         }
 611 #endif
 612
 613
 614         return 0;
 615 }
 616
 617 extern void setup_ivors(void);
 618
 619 void arch_preboot_os(void)
 620 {
 621         u32 msr;
 622
 623         /*
 624          * We are changing interrupt offsets and are about to boot the OS so
 625          * we need to make sure we disable all async interrupts. EE is already
 626          * disabled by the time we get called.
 627          */
 628         msr = mfmsr();
 629         msr &= ~(MSR_ME|MSR_CE);
 630         mtmsr(msr);
 631
 632         setup_ivors();
 633 }
 634
 635 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
 636 int sata_initialize(void)
 637 {
 638         if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
 639                 return __sata_initialize();
 640
 641         return 1;
 642 }
 643 #endif
 644
 645 void cpu_secondary_init_r(void)
 646 {
 647 #ifdef CONFIG_QE
 648         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 649 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 650         int ret;
 651         size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
 652
 653         /* load QE firmware from NAND flash to DDR first */
 654         ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
 655                         &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
 656
 657         if (ret && ret == -EUCLEAN) {
 658                 printf ("NAND read for QE firmware at offset %x failed %d\n",
 659                                 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
 660         }
 661 #endif
 662         qe_init(qe_base);
 663         qe_reset();
 664 #endif
 665 }