arch/powerpc/cpu/mpc85xx/tlb.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/processor.h>
  28 #include <asm/mmu.h>
  29 #ifdef CONFIG_ADDR_MAP
  30 #include <addr_map.h>
  31 #endif
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 void invalidate_tlb(u8 tlb)
  36 {
  37         if (tlb == 0)
  38                 mtspr(MMUCSR0, 0x4);
  39         if (tlb == 1)
  40                 mtspr(MMUCSR0, 0x2);
  41 }
  42
  43 void init_tlbs(void)
  44 {
  45         int i;
  46
  47         for (i = 0; i < num_tlb_entries; i++) {
  48                 write_tlb(tlb_table[i].mas0,
  49                           tlb_table[i].mas1,
  50                           tlb_table[i].mas2,
  51                           tlb_table[i].mas3,
  52                           tlb_table[i].mas7);
  53         }
  54
  55         return ;
  56 }
  57
  58 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
  59 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  60                        phys_addr_t *rpn)
  61 {
  62         u32 _mas1;
  63
  64         mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
  65         asm volatile("tlbre;isync");
  66         _mas1 = mfspr(MAS1);
  67
  68         *valid = (_mas1 & MAS1_VALID);
  69         *tsize = (_mas1 >> 7) & 0x1f;
  70         *epn = mfspr(MAS2) & MAS2_EPN;
  71         *rpn = mfspr(MAS3) & MAS3_RPN;
  72 #ifdef CONFIG_ENABLE_36BIT_PHYS
  73         *rpn |= ((u64)mfspr(MAS7)) << 32;
  74 #endif
  75 }
  76
  77 void print_tlbcam(void)
  78 {
  79         int i;
  80         unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
  81
  82         /* walk all the entries */
  83         printf("TLBCAM entries\n");
  84         for (i = 0; i < num_cam; i++) {
  85                 unsigned long epn;
  86                 u32 tsize, valid;
  87                 phys_addr_t rpn;
  88
  89                 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
  90                 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
  91                         i, (valid == 0) ? 0 : 1, (unsigned int)epn,
  92                         (unsigned long long)rpn);
  93                 print_size(TSIZE_TO_BYTES(tsize), "\n");
  94         }
  95 }
  96
  97 static inline void use_tlb_cam(u8 idx)
  98 {
  99         int i = idx / 32;
 100         int bit = idx % 32;
 101
 102         gd->arch.used_tlb_cams[i] |= (1 << bit);
 103 }
 104
 105 static inline void free_tlb_cam(u8 idx)
 106 {
 107         int i = idx / 32;
 108         int bit = idx % 32;
 109
 110         gd->arch.used_tlb_cams[i] &= ~(1 << bit);
 111 }
 112
 113 void init_used_tlb_cams(void)
 114 {
 115         int i;
 116         unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
 117
 118         for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
 119                 gd->arch.used_tlb_cams[i] = 0;
 120
 121         /* walk all the entries */
 122         for (i = 0; i < num_cam; i++) {
 123                 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
 124                 asm volatile("tlbre;isync");
 125                 if (mfspr(MAS1) & MAS1_VALID)
 126                         use_tlb_cam(i);
 127         }
 128 }
 129
 130 int find_free_tlbcam(void)
 131 {
 132         int i;
 133         u32 idx;
 134
 135         for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
 136                 idx = ffz(gd->arch.used_tlb_cams[i]);
 137
 138                 if (idx != 32)
 139                         break;
 140         }
 141
 142         idx += i * 32;
 143
 144         if (idx >= CONFIG_SYS_NUM_TLBCAMS)
 145                 return -1;
 146
 147         return idx;
 148 }
 149
 150 void set_tlb(u8 tlb, u32 epn, u64 rpn,
 151              u8 perms, u8 wimge,
 152              u8 ts, u8 esel, u8 tsize, u8 iprot)
 153 {
 154         u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 155
 156         if (tlb == 1)
 157                 use_tlb_cam(esel);
 158
 159         if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
 160             tsize & 1) {
 161                 printf("%s: bad tsize %d on entry %d at 0x%08x\n",
 162                         __func__, tsize, tlb, epn);
 163                 return;
 164         }
 165
 166         _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
 167         _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
 168         _mas2 = FSL_BOOKE_MAS2(epn, wimge);
 169         _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
 170         _mas7 = FSL_BOOKE_MAS7(rpn);
 171
 172         write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
 173
 174 #ifdef CONFIG_ADDR_MAP
 175         if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
 176                 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
 177 #endif
 178 }
 179
 180 void disable_tlb(u8 esel)
 181 {
 182         u32 _mas0, _mas1, _mas2, _mas3;
 183
 184         free_tlb_cam(esel);
 185
 186         _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
 187         _mas1 = 0;
 188         _mas2 = 0;
 189         _mas3 = 0;
 190
 191         mtspr(MAS0, _mas0);
 192         mtspr(MAS1, _mas1);
 193         mtspr(MAS2, _mas2);
 194         mtspr(MAS3, _mas3);
 195 #ifdef CONFIG_ENABLE_36BIT_PHYS
 196         mtspr(MAS7, 0);
 197 #endif
 198         asm volatile("isync;msync;tlbwe;isync");
 199
 200 #ifdef CONFIG_ADDR_MAP
 201         if (gd->flags & GD_FLG_RELOC)
 202                 addrmap_set_entry(0, 0, 0, esel);
 203 #endif
 204 }
 205
 206 static void tlbsx (const volatile unsigned *addr)
 207 {
 208         __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
 209 }
 210
 211 /* return -1 if we didn't find anything */
 212 int find_tlb_idx(void *addr, u8 tlbsel)
 213 {
 214         u32 _mas0, _mas1;
 215
 216         /* zero out Search PID, AS */
 217         mtspr(MAS6, 0);
 218
 219         tlbsx(addr);
 220
 221         _mas0 = mfspr(MAS0);
 222         _mas1 = mfspr(MAS1);
 223
 224         /* we found something, and its in the TLB we expect */
 225         if ((MAS1_VALID & _mas1) &&
 226                 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
 227                 return ((_mas0 & MAS0_ESEL_MSK) >> 16);
 228         }
 229
 230         return -1;
 231 }
 232
 233 #ifdef CONFIG_ADDR_MAP
 234 void init_addr_map(void)
 235 {
 236         int i;
 237         unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
 238
 239         /* walk all the entries */
 240         for (i = 0; i < num_cam; i++) {
 241                 unsigned long epn;
 242                 u32 tsize, valid;
 243                 phys_addr_t rpn;
 244
 245                 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
 246                 if (valid & MAS1_VALID)
 247                         addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
 248         }
 249
 250         return ;
 251 }
 252 #endif
 253
 254 unsigned int
 255 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 256 {
 257         int i;
 258         unsigned int tlb_size;
 259         unsigned int wimge = MAS2_M;
 260         unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
 261         unsigned int max_cam, tsize_mask;
 262         u64 size, memsize = (u64)memsize_in_meg << 20;
 263
 264 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
 265         wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 266 #endif
 267         size = min(memsize, CONFIG_MAX_MEM_MAPPED);
 268         if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 269                 /* Convert (4^max) kB to (2^max) bytes */
 270                 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
 271                 tsize_mask = ~1U;
 272         } else {
 273                 /* Convert (2^max) kB to (2^max) bytes */
 274                 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
 275                 tsize_mask = ~0U;
 276         }
 277
 278         for (i = 0; size && i < 8; i++) {
 279                 int ram_tlb_index = find_free_tlbcam();
 280                 u32 camsize = __ilog2_u64(size) & tsize_mask;
 281                 u32 align = __ilog2(ram_tlb_address) & tsize_mask;
 282
 283                 if (ram_tlb_index == -1)
 284                         break;
 285
 286                 if (align == -2) align = max_cam;
 287                 if (camsize > align)
 288                         camsize = align;
 289
 290                 if (camsize > max_cam)
 291                         camsize = max_cam;
 292
 293                 tlb_size = camsize - 10;
 294
 295                 set_tlb(1, ram_tlb_address, p_addr,
 296                         MAS3_SX|MAS3_SW|MAS3_SR, wimge,
 297                         0, ram_tlb_index, tlb_size, 1);
 298
 299                 size -= 1ULL << camsize;
 300                 memsize -= 1ULL << camsize;
 301                 ram_tlb_address += 1UL << camsize;
 302                 p_addr += 1UL << camsize;
 303         }
 304
 305         if (memsize)
 306                 print_size(memsize, " left unmapped\n");
 307         return memsize_in_meg;
 308 }
 309
 310 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 311 {
 312         return
 313                 setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
 314 }
 315
 316 /* Invalidate the DDR TLBs for the requested size */
 317 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 318 {
 319         u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
 320         unsigned long epn;
 321         u32 tsize, valid, ptr;
 322         phys_addr_t rpn = 0;
 323         int ddr_esel;
 324         u64 memsize = (u64)memsize_in_meg << 20;
 325
 326         ptr = vstart;
 327
 328         while (ptr < (vstart + memsize)) {
 329                 ddr_esel = find_tlb_idx((void *)ptr, 1);
 330                 if (ddr_esel != -1) {
 331                         read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
 332                         disable_tlb(ddr_esel);
 333                 }
 334                 ptr += TSIZE_TO_BYTES(tsize);
 335         }
 336 }
 337
 338 void clear_ddr_tlbs(unsigned int memsize_in_meg)
 339 {
 340         clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
 341 }
 342
 343
 344 #endif /* not SPL */